diff mbox series

[take,#2] PR target/43892: Some carry flag (CA) optimizations on PowerPC.

Message ID 03ae01d7e87d$f67f1a80$e37d4f80$@nextmovesoftware.com
State New
Headers
Series [take,#2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. |

Commit Message

Roger Sayle Dec. 3, 2021, 7:42 p.m. UTC 
  Doh!  This time with the patch attached...

This patch resolves PR target/43892 (suboptimal add with carry) by adding
four new define_insn_and_split to the rs6000 backend, that all recognize
pairs of instructions where the first instruction sets the carry flag and
the second one consumes it.  It also adds a commutative variant of
add<mode>3_carry_in_0 (aka "addze") to catch cases, not caught by recog's
insn canonicalization, where CA_REG appears first.

For the add32carry function in the original PR:

unsigned int add32carry(unsigned int sum, unsigned int x) {
  unsigned int z = sum + x;
  if (sum + x < x)
    z++;
  return z;
}

previously "-O2 -m32" would generate:

add32carry:
        add 3,3,4
        subfc 4,4,3
        subfe 9,9,9
        subf 3,9,3
        blr

with this patch we now generate:

add32carry:
        addc 3,3,4
        addze 3,3
        blr

And for the related examples in the new test case,

unsigned long add_leu(unsigned long a, unsigned long b, unsigned long c) {
  return a + (b <= c);
}

unsigned long add_geu(unsigned long a, unsigned long b, unsigned long c) {
  return a + (b >= c);
}

On powerpc64 with -O2 we'd previously generate:

add_leu:
        subfc 4,4,5
        subfe 9,9,9
        addi 9,9,1
        add 3,9,3
        blr
add_geu:
        subfc 5,5,4
        subfe 9,9,9
        addi 9,9,1
        add 3,9,3
        blr

but with this patch we now generate:

add_leu:
        subfc 4,4,5
        addze 3,3
        blr
add_geu:
        subfc 5,5,4
        addze 3,3
        blr

This patch has been tested on powerpc64-unknown-linux-gnu (many thanks to
gcc203.fsffrance.org on the GCC compile farm) with a make bootstrap and make
-k check with now new failures.

Ok for mainline?


2021-12-03  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	PR target/43892
	* config/rs6000/rs6000.md (*add<mode>3_carry_in_0_2): New
	define_insn to recognize commutative form of add<mode>3_carry_in_0.
	(*add<mode>3_geu, *add<mode>3_leu, *subf<mode>3_carry_in_xx_subf,
	*add<mode>3_carry_in_addc): New define_insn_and_split patterns.

gcc/testsuite/ChangeLog
	PR target/43892
	* gcc.target/powerpc/addcmp.c: New test case.
	* gcc.target/powerpc/pr43892.c: New test case.


Many thanks in advance.
Roger
--

Comments

Segher Boessenkool Dec. 15, 2021, 2:11 a.m. UTC | #1 
Hi!

On Fri, Dec 03, 2021 at 07:42:52PM -0000, Roger Sayle wrote:
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/addcmp.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +unsigned long add_leu(unsigned long a, unsigned long b, unsigned long c) {
> +  return a + (b <= c);
> +}
> +
> +unsigned long add_geu(unsigned long a, unsigned long b, unsigned long c) {
> +  return a + (b >= c);
> +}
> +
> +/* { dg-final { scan-assembler-times "addze " 2 } } */

Does this work with -mcpu=power10 after your patch?  (It doesn't before
it :-) )

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr43892.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +unsigned long foo(unsigned long sum, unsigned long x)
> +{
> +  unsigned long z = sum + x;
> +  if (sum + x < x)
> +    z++;
> +  return z;
> +}
> +
> +/* { dg-final { scan-assembler "addze " } } */

Same question here.

Thanks!


Segher
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6bec2bddbde..90c23556ccb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2067,6 +2067,16 @@ 
   "addze %0,%1"
   [(set_attr "type" "add")])
 
+;; Non-canonical form of add<mode>3_carry_in_0
+(define_insn "*add<mode>3_carry_in_0_2"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+	(plus:GPR (reg:GPR CA_REGNO)
+		  (match_operand:GPR 1 "gpc_reg_operand" "r")))
+   (clobber (reg:GPR CA_REGNO))]
+  ""
+  "addze %0,%1"
+  [(set_attr "type" "add")])
+
 (define_insn "add<mode>3_carry_in_m1"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
@@ -2078,6 +2088,95 @@ 
   [(set_attr "type" "add")])
 
 
+;; PR target/43892 -> subf<mode>3_carry ; add<mode>3_carry_in_0
+(define_insn_and_split "*add<mode>3_geu"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r")
+		       (match_operand:P 2 "gpc_reg_operand" "r"))
+		(match_operand:P 3 "gpc_reg_operand" "r")))
+   (clobber (match_scratch:P 4 "=r"))
+   (clobber (reg:P CA_REGNO))]
+  ""
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  if (GET_CODE (operands[4]) == SCRATCH)
+    operands[4] = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_subf<mode>3_carry (operands[4], operands[1], operands[2]));
+  emit_insn (gen_add<mode>3_carry_in_0 (operands[0], operands[3]));
+  DONE;
+}
+  [(set_attr "type" "two")
+   (set_attr "length" "8")])
+
+;; PR target/43892 -> subf<mode>3_carry ; add<mode>3_carry_in_0
+(define_insn_and_split "*add<mode>3_leu"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
+		       (match_operand:P 2 "gpc_reg_operand" "r"))
+		(match_operand:P 3 "gpc_reg_operand" "r")))
+   (clobber (match_scratch:P 4 "=r"))
+   (clobber (reg:P CA_REGNO))]
+  ""
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  if (GET_CODE (operands[4]) == SCRATCH)
+    operands[4] = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_subf<mode>3_carry (operands[4], operands[2], operands[1]));
+  emit_insn (gen_add<mode>3_carry_in_0 (operands[0], operands[3]));
+  DONE;
+}
+  [(set_attr "type" "two")
+   (set_attr "length" "8")])
+
+;; PR target/43892 -> subf<mode>3_carry_in_xx ; subf<mode>3
+(define_insn_and_split "*subf<mode>3_carry_in_xx_subf"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(plus:P (minus:P (match_operand:P 1 "gpc_reg_operand" "r")
+			 (reg:P CA_REGNO))
+		(const_int 1)))
+   (clobber (match_scratch:P 2 "=r"))
+   (clobber (reg:P CA_REGNO))]
+  ""
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  if (GET_CODE (operands[2]) == SCRATCH)
+    operands[2] = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_subf<mode>3_carry_in_xx (operands[2]));
+  emit_insn (gen_sub<mode>3 (operands[0], operands[1], operands[2]));
+  DONE;
+}
+  [(set_attr "type" "two")
+   (set_attr "length" "8")])
+
+;; PR target/43892 -> add<mode>3_carry ; add<mode>3_carry_in_0
+(define_insn_and_split "*add<mode>3_carry_in_addc"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(plus:P (plus:P
+		 (ltu:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
+		                (match_operand:P 2 "gpc_reg_operand" "r"))
+			(match_dup 1))
+		 (match_dup 2))
+		(match_dup 1)))
+   (clobber (reg:P CA_REGNO))]
+  ""
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  emit_insn (gen_add<mode>3_carry (operands[0], operands[1], operands[2]));
+  emit_insn (gen_add<mode>3_carry_in_0 (operands[0], operands[0]));
+  DONE;
+}
+  [(set_attr "type" "two")
+   (set_attr "length" "8")])
+
+
 (define_expand "one_cmpl<mode>2"
   [(set (match_operand:SDI 0 "gpc_reg_operand")
 	(not:SDI (match_operand:SDI 1 "gpc_reg_operand")))]
diff --git a/gcc/testsuite/gcc.target/powerpc/addcmp.c b/gcc/testsuite/gcc.target/powerpc/addcmp.c
new file mode 100644
index 00000000000..6ca971bfc66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/addcmp.c
@@ -0,0 +1,12 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned long add_leu(unsigned long a, unsigned long b, unsigned long c) {
+  return a + (b <= c);
+}
+
+unsigned long add_geu(unsigned long a, unsigned long b, unsigned long c) {
+  return a + (b >= c);
+}
+
+/* { dg-final { scan-assembler-times "addze " 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr43892.c b/gcc/testsuite/gcc.target/powerpc/pr43892.c
new file mode 100644
index 00000000000..f5d6b852c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr43892.c
@@ -0,0 +1,11 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+unsigned long foo(unsigned long sum, unsigned long x)
+{
+  unsigned long z = sum + x;
+  if (sum + x < x)
+    z++;
+  return z;
+}
+
+/* { dg-final { scan-assembler "addze " } } */