From patchwork Fri Aug 5 18:36:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 56573 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7ECA23856948 for ; Fri, 5 Aug 2022 18:37:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id BE41E3858C2F for ; Fri, 5 Aug 2022 18:36:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BE41E3858C2F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=7TCqWWrj5XN7/Ja9s4lPQq0tqFEZDQCQVceYB/0Q9dw=; b=R//bJP+fUZhmJXfVmZyuSX/sY0 TQ+57/PXpAC8B2QmkoPo/jvNq3tg/gYoTcxGz+wO8Oriyu2rVT/deQ8DBqcjt+HMzocnxxgdvKA2O bzS0lYRO9htyQiHiIU5JIptSAB6KOLY9CkAiUIJupWGy44BB8rUoT5U0V+oWkioiR3pmO6s+md+xH 50Igdf8NeksZvxEp8ioMtOySwlhg/42txEborQRDvWasHVsjC2RoQGj/PyKReFRZsVS86XyezGtgb y+boEvoyK1YXm2Bbmlyiiz7MatNwku4fP5dFecDY++ardcHM0tNls2iz7IuXGdX3B/hj2x9OvmU5K /xedSGhQ==; Received: from [185.62.158.67] (port=49983 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oK2Bf-000195-L6; Fri, 05 Aug 2022 14:36:43 -0400 From: "Roger Sayle" To: Subject: [x86 PATCH] Move V1TI shift/rotate lowering from expand to pre-reload split. Date: Fri, 5 Aug 2022 19:36:42 +0100 Message-ID: <037701d8a8fa$4f65ed80$ee31c880$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adio+V0h2VTKXwKNTRiac0OhB3XYTw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch moves the lowering of 128-bit V1TImode shifts and rotations by constant bit counts to sequences of SSE operations from the RTL expansion pass to the pre-reload split pass. Postponing this splitting of shifts and rotates enables (will enable) the TImode equivalents of these operations/ instructions to be considered as candidates by the (TImode) STV pass. Technically, this patch changes the existing expanders to continue to lower shifts by variable amounts, but constant operands become RTL instructions, specified by define_insn_and_split that are triggered by x86_pre_reload_split. The one minor complication is that logical shifts by multiples of eight, don't get split, but are handled by existing insn patterns, such as sse2_ashlv1ti3 and sse2_lshrv1ti3. There should be no changes in generated code with this patch, which just adjusts the pass in which transformations get applied. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2022-08-05 Roger Sayle gcc/ChangeLog * config/i386/sse.md (ashlv1ti3): Delay lowering of logical left shifts by constant bit counts. (*ashlvti3_internal): New define_insn_and_split that lowers logical left shifts by constant bit counts, that aren't multiples of 8, before reload. (lshrv1ti3): Delay lowering of logical right shifts by constant. (*lshrv1ti3_internal): New define_insn_and_split that lowers logical right shifts by constant bit counts, that aren't multiples of 8, before reload. (ashrv1ti3):: Delay lowering of arithmetic right shifts by constant bit counts. (*ashrv1ti3_internal): New define_insn_and_split that lowers arithmetic right shifts by constant bit counts before reload. (rotlv1ti3): Delay lowering of rotate left by constant. (*rotlv1ti3_internal): New define_insn_and_split that lowers rotate left by constant bits counts before reload. (rotrv1ti3): Delay lowering of rotate right by constant. (*rotrv1ti3_internal): New define_insn_and_split that lowers rotate right by constant bits counts before reload. Thanks in advance, Roger diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 14d12d1..d3ea52f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15995,10 +15995,30 @@ (define_expand "ashlv1ti3" [(set (match_operand:V1TI 0 "register_operand") + (ashift:V1TI + (match_operand:V1TI 1 "register_operand") + (match_operand:QI 2 "general_operand")))] + "TARGET_SSE2 && TARGET_64BIT" +{ + if (!CONST_INT_P (operands[2])) + { + ix86_expand_v1ti_shift (ASHIFT, operands); + DONE; + } +}) + +(define_insn_and_split "*ashlv1ti3_internal" + [(set (match_operand:V1TI 0 "register_operand") (ashift:V1TI (match_operand:V1TI 1 "register_operand") - (match_operand:QI 2 "general_operand")))] - "TARGET_SSE2 && TARGET_64BIT" + (match_operand:SI 2 "const_0_to_255_operand")))] + "TARGET_SSE2 + && TARGET_64BIT + && (INTVAL (operands[2]) & 7) != 0 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] { ix86_expand_v1ti_shift (ASHIFT, operands); DONE; @@ -16011,6 +16031,26 @@ (match_operand:QI 2 "general_operand")))] "TARGET_SSE2 && TARGET_64BIT" { + if (!CONST_INT_P (operands[2])) + { + ix86_expand_v1ti_shift (LSHIFTRT, operands); + DONE; + } +}) + +(define_insn_and_split "*lshrv1ti3_internal" + [(set (match_operand:V1TI 0 "register_operand") + (lshiftrt:V1TI + (match_operand:V1TI 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_operand")))] + "TARGET_SSE2 + && TARGET_64BIT + && (INTVAL (operands[2]) & 7) != 0 + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] +{ ix86_expand_v1ti_shift (LSHIFTRT, operands); DONE; }) @@ -16022,6 +16062,26 @@ (match_operand:QI 2 "general_operand")))] "TARGET_SSE2 && TARGET_64BIT" { + if (!CONST_INT_P (operands[2])) + { + ix86_expand_v1ti_ashiftrt (operands); + DONE; + } +}) + + +(define_insn_and_split "*ashrv1ti3_internal" + [(set (match_operand:V1TI 0 "register_operand") + (ashiftrt:V1TI + (match_operand:V1TI 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_operand")))] + "TARGET_SSE2 + && TARGET_64BIT + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] +{ ix86_expand_v1ti_ashiftrt (operands); DONE; }) @@ -16033,6 +16093,25 @@ (match_operand:QI 2 "general_operand")))] "TARGET_SSE2 && TARGET_64BIT" { + if (!CONST_INT_P (operands[2])) + { + ix86_expand_v1ti_rotate (ROTATE, operands); + DONE; + } +}) + +(define_insn_and_split "*rotlv1ti3_internal" + [(set (match_operand:V1TI 0 "register_operand") + (rotate:V1TI + (match_operand:V1TI 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_operand")))] + "TARGET_SSE2 + && TARGET_64BIT + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] +{ ix86_expand_v1ti_rotate (ROTATE, operands); DONE; }) @@ -16044,6 +16123,25 @@ (match_operand:QI 2 "general_operand")))] "TARGET_SSE2 && TARGET_64BIT" { + if (!CONST_INT_P (operands[2])) + { + ix86_expand_v1ti_rotate (ROTATERT, operands); + DONE; + } +}) + +(define_insn_and_split "*rotrv1ti3_internal" + [(set (match_operand:V1TI 0 "register_operand") + (rotatert:V1TI + (match_operand:V1TI 1 "register_operand") + (match_operand:SI 2 "const_0_to_255_operand")))] + "TARGET_SSE2 + && TARGET_64BIT + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] +{ ix86_expand_v1ti_rotate (ROTATERT, operands); DONE; })