From patchwork Tue Apr 12 16:43:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 52820 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 57FDD3857809 for ; Tue, 12 Apr 2022 16:44:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 6F7F93858427 for ; Tue, 12 Apr 2022 16:43:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6F7F93858427 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=aP7CoS/6BPcrvCARio4K0Rrggcm1TpSue2D7Gtj6u4Y=; b=U8rCq2TUmX3LPDDYi80p9BgFkn YQlCHlrNTZ3BSc+dDEhJ5Y5i22cWjUR41dDp89aQK9ReUlkxa+XIHwYrgJ5mvFbz8JHIdoN1xAHQd d/sSuaf+5XsJ0vtjHkYipWb6uHhD01141neOL50dIDzDLUORUaPzGO5UhyBhvCfzxQvA5buVhFVpn 2yzgfujbha7gdAAivyMINXJ/X9VINiIRsbHytVkW8d3iEV1E/vJiWOKYj237hNe/jVuSokSS77wqc XgjHcgYmAdCrwxonNCll9gDqhfCHRdweaDCl0vCiQP/2SFZjBDJ81q7cAmtKeBLjOMXB1yGBRFLx9 aeaY2uWQ==; Received: from [185.62.158.67] (port=55959 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1neJcS-0005GZ-0S for gcc-patches@gcc.gnu.org; Tue, 12 Apr 2022 12:43:56 -0400 From: "Roger Sayle" To: Subject: [x86 PATCH] Peephole pand;pxor into pandn. Date: Tue, 12 Apr 2022 17:43:54 +0100 Message-ID: <020d01d84e8c$7fa90180$7efb0480$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdhOi6gSn6hzkFxOSuy9qS1fmdjz6w== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" As a side-effect, a patch I have for PR 70321 causes the failure of gcc.target/i386/pr65105-5.c by generating the code: vmovq (%eax), %xmm1 vpand %xmm1, %xmm2, %xmm0 vpxor %xmm0, %xmm2, %xmm0 vpunpcklqdq %xmm0, %xmm0, %xmm0 vptest %xmm0, %xmm0 instead of the pandn sequence that the test is expecting: vmovq (%eax), %xmm1 vpandn %xmm2, %xmm1, %xmm0 vpunpcklqdq %xmm0, %xmm0, %xmm0 vptest %xmm0, %xmm0 This patch prevents the above FAIL by providing a peephole2 to convert a suitable pand followed by pxor, i.e. (X & Y) ^ X, into the equivalent pandn, i.e. X & ~Y. For GCC 13, the above sequence can actually be implemented in just two instructions (neither the pandn nor the punpcklqdq are necessary if vptest %xmm1, %xmm2 is used), but for now, this preserves the sequence that the test case is expecting. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Alas there's no new test case as this optimization is normally caught by (or before) combine, and therefore tricky to trigger. Ok for mainline? 2022-04-12 Roger Sayle gcc/ChangeLog * config/i386/sse.md (peephole2): Convert suitable pand followed by pxor into pandn, i.e. (X&Y)^X into X & ~Y. Thanks in advance, Roger diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a852c16..f7ef81a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16887,6 +16887,44 @@ (match_dup 2)))] "operands[3] = gen_reg_rtx (mode);") +;; Combine pand;pxor into pandn. (X&Y)^X -> X & ~Y. +(define_peephole2 + [(set (match_operand:VMOVE 0 "register_operand") + (and:VMOVE (match_operand:VMOVE 1 "register_operand") + (match_operand:VMOVE 2 "register_operand"))) + (set (match_operand:VMOVE 3 "register_operand") + (xor:VMOVE (match_operand:VMOVE 4 "register_operand") + (match_operand:VMOVE 5 "register_operand")))] + "TARGET_SSE + && REGNO (operands[1]) != REGNO (operands[2]) + && REGNO (operands[4]) != REGNO (operands[5]) + && (REGNO (operands[0]) == REGNO (operands[3]) + || peep2_reg_dead_p (2, operands[0]))" + [(set (match_dup 3) + (and:VMOVE (not:VMOVE (match_dup 6)) (match_dup 7)))] +{ + if (REGNO (operands[0]) != REGNO (operands[1]) + && ((REGNO (operands[4]) == REGNO (operands[0]) + && REGNO (operands[5]) == REGNO (operands[1])) + || (REGNO (operands[4]) == REGNO (operands[1]) + && REGNO (operands[5]) == REGNO (operands[0])))) + { + operands[6] = operands[2]; + operands[7] = operands[1]; + } + else if (REGNO (operands[0]) != REGNO (operands[2]) + && ((REGNO (operands[4]) == REGNO (operands[0]) + && REGNO (operands[5]) == REGNO (operands[2])) + || (REGNO (operands[4]) == REGNO (operands[2]) + && REGNO (operands[5]) == REGNO (operands[0])))) + { + operands[6] = operands[1]; + operands[7] = operands[2]; + } + else + FAIL; +}) + (define_insn "*andnot3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (vec_merge:VI48_AVX512VL