From patchwork Mon Jan 9 15:01:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 62852 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 627773857835 for ; Mon, 9 Jan 2023 15:01:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 8AB4E3858408 for ; Mon, 9 Jan 2023 15:01:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8AB4E3858408 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=Bj5oZ5gUgBh6RLsKVS67p3pOrZK7/wmHtM3yWT7mMJY=; b=ZSNRCLw6XWvqolecU2xw+NhddY Pll9iPnwLfLJn5DABsxY29GqvuMmEkr7UEZPy7jw6N7gXMWvT6CTeBPX5+EVmK5IPJwKlYoB0DKMI Q+ev+zRhhhxLET2LJ2uenCifWtLOAx4qS9K3tnJDtUVyWBUPJrmd9Z3Z9qGZOG3XxH6RgaDn1GNUH bL/WxpwRxHh1GsewJ4DmulrPQ7rhrZnmYye1s2Pjor8BnoY3svS/kWfRIqc2OUSmTUUxiEG/LZmcS FVjLsAQAWC3unjDoF5OFSIQ4KsH1oKWf74VyaKadmtSCuxo3Y7QJAuMGQJ1037owNqfS/PNNJGbaA ElzzlMAg==; Received: from [185.62.158.67] (port=52270 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pEteD-0002Nd-Od; Mon, 09 Jan 2023 10:01:13 -0500 From: "Roger Sayle" To: "'GCC Patches'" Cc: "'Uros Bizjak'" Subject: [x86 PATCH] PR rtl-optimization/107991: peephole2 to tweak register allocation. Date: Mon, 9 Jan 2023 15:01:10 -0000 Message-ID: <011401d9243b$3782ce10$a6886a30$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdkkOqhER/g5PgF4Qs+fsYbSl+ez7Q== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch addresses PR rtl-optimization/107991, which is a P2 regression where GCC currently requires more "mov" instructions than GCC 7. The x86's two address ISA creates some interesting challenges for reload. For example, the tricky "x = y - x" usually needs to be implemented on x86 as tmp = x x = y x -= tmp where a scratch register and two mov's are required to work around the lack of a subf (subtract from) or rsub (reverse subtract) insn. Not uncommonly, if y is dead after this subtraction, register allocation can be improved by clobbering y. y -= x x = y For the testcase in PR 107991, things are slightly more complicated, where y is not itself dead, but is assigned from (i.e. equivalent to) a value that is dead. Hence we have something like: y = z x = y - x so, GCC's reload currently generates the expected shuffle (as y is live): y = z tmp = x x = y x -= tmp but we can use a peephole2 that understands that y and z are equivalent, and that z is dead, to produce the shorter sequence: y = z z -= x x = z In practice, for the new testcase from PR 107991, which before produced: foo: movl %edx, %ecx movl %esi, %edx movl %esi, %eax subl %ecx, %edx testb %dil, %dil cmovne %edx, %eax ret with this patch/peephole2 we now produce the much improved: foo: movl %esi, %eax subl %edx, %esi testb %dil, %dil cmovne %esi, %eax ret This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2023-01-09 Roger Sayle gcc/ChangeLog PR rtl-optimization/107991 * config/i386/i386.md (peephole2): New peephole2 to avoid register shuffling before a subtraction, after a register-to-register move. gcc/testsuite/ChangeLog PR rtl-optimization/107991 * gcc.target/i386/pr107991.c: New test case. Thanks in advance, Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 76f55ec..3090cea 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -7603,6 +7603,31 @@ "sub{l}\t{%2, %1|%1, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) + +;; PR 107991: Use peephole2 to avoid suffling before subtraction. +;; ax = si; cx = dx; dx = ax; dx -= cx where both si and cx +;; are dead becomes ax = si; si -= dx; dx = si. +(define_peephole2 + [(set (match_operand:SWI 0 "general_reg_operand") + (match_operand:SWI 1 "general_reg_operand")) + (set (match_operand:SWI 2 "general_reg_operand") + (match_operand:SWI 3 "general_reg_operand")) + (set (match_dup 3) (match_dup 0)) + (parallel + [(set (match_dup 3) (minus:SWI (match_dup 3) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "REGNO (operands[0]) != REGNO (operands[1]) + && REGNO (operands[0]) != REGNO (operands[2]) + && REGNO (operands[0]) != REGNO (operands[3]) + && REGNO (operands[1]) != REGNO (operands[2]) + && REGNO (operands[1]) != REGNO (operands[3]) + && REGNO (operands[2]) != REGNO (operands[3]) + && peep2_reg_dead_p (1, operands[1]) + && peep2_reg_dead_p (4, operands[2])" + [(set (match_dup 0) (match_dup 1)) + (parallel [(set (match_dup 1) (minus:SWI (match_dup 1) (match_dup 3))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 3) (match_dup 1))]) ;; Add with carry and subtract with borrow diff --git a/gcc/testsuite/gcc.target/i386/pr107991.c b/gcc/testsuite/gcc.target/i386/pr107991.c new file mode 100644 index 0000000..9d0d9b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107991.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +int foo(_Bool b, int i, int j) { + return b ? i - j : i; +} + +int bar(_Bool b, int i, int j) { + return i + (b ? -j : 0); +} + +int baz(_Bool b, int i, int j) { + return i - (b ? j : 0); +} + +/* { dg-final { scan-assembler-times "movl" 3 } } */