From patchwork Thu May 26 18:41:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 54429 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 63B99383569D for ; Thu, 26 May 2022 18:41:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id E989A3836E51 for ; Thu, 26 May 2022 18:41:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E989A3836E51 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=QABpPPO5kWUfuROgPc4bCqnIm0JncI1GCHnrQhHotik=; b=shxLp+pymHEBjDqTBokJDcAOws oNWCE7tLrG8pVlWtzwdSe5QwLItscIB0RC7482kX+BDvvUUfW4l392E2XYti6TiV7VkXmmgJXIVnM CF4QcSJ0KvfbsZ4hd7RQukztl1cUu2sU/yGdRRKQ+N+G9JU9+NqpD//u1H8sFE7Mkgmit13YQeeje N2uPqAotm7MOkXPTm/SyPqDQPzRV6MqYNHiLJUe4Uq8XPdeHlYS//hGkCCSdV8c4Hj6XfE53yCI/a EBhZaPZVE0s0+FS6J7Y9knOoO9cy3BBq4Ldsa55+A71B7Vh79qzdsbAvBSm7/IkltLZvZr+FQjSUX nGobLHBA==; Received: from host109-154-46-241.range109-154.btcentralplus.com ([109.154.46.241]:59818 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nuIQM-0002dY-7p; Thu, 26 May 2022 14:41:30 -0400 From: "Roger Sayle" To: "'GCC Patches'" Subject: [x86 PATCH] Pre-reload splitter to transform and;cmp into not;test. Date: Thu, 26 May 2022 19:41:29 +0100 Message-ID: <006301d87130$3747a240$a5d6e6c0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdhxL3YzSVrWqiBLTSyOkJ7wI8pRwA== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" A common idiom for testing if a specific set of bits is set in a value is to use "(X & Y) == Y", which on x86 results in an AND followed by a CMP. A slightly improved implementation is to instead use (~X & Y)==0, that uses a NOT and a TEST (or ANDN where available); still two "fast" instructions, but typically shorter especially if Y is an immediate constant. Because the above transformation would require more gimple statements in SSA, and may only be a win on targets with flags registers, it isn't performed by the middle-end, instead leaving this choice to the backend. As an example, here's the change in code generation for pr91400-1.c [which now requires a tweak to its dg-final clauses]. Before: movl __cpu_model+12(%rip), %eax andl $68, %eax // 3 bytes cmpl $68, %eax // 3 bytes sete %al ret After: movl __cpu_model+12(%rip), %eax notl %eax // 2 bytes testb $68, %al // 2 bytes sete %al ret This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2022-05-26 Roger Sayle gcc/ChangeLog * config/i386/i386.md (*test_not): New define_insn_and_split to split a combined "and;cmp" sequence into "not;test". gcc/testsuite/ChangeLog * gcc.target/i386/pr91400-1.c: Update for improved code generation. * gcc.target/i386/pr91400-2.c: Likewise. * gcc.target/i386/testnot-1.c: New test case. * gcc.target/i386/testnot-2.c: Likewise. Thanks in advance, Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index b9b8f78..602dfa7 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9716,6 +9716,27 @@ operands[2] = gen_rtx_AND (mode, val, immed_wide_int_const (mask, mode)); }) +;; Split and;cmp (as optimized by combine) into not;test +;; Except when TARGET_BMI provides andn (*andn__ccno). +(define_insn_and_split "*test_not" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (and:SWI + (not:SWI (match_operand:SWI 0 "register_operand")) + (match_operand:SWI 1 "")) + (const_int 0)))] + "ix86_pre_reload_split () + && (!TARGET_BMI || !REG_P (operands[1]))" + "#" + "&& 1" + [(set (match_dup 2) (not:SWI (match_dup 0))) + (set (reg:CCZ FLAGS_REG) + (compare:CCZ (and:SWI (match_dup 2) (match_dup 1)) + (const_int 0)))] +{ + operands[2] = gen_reg_rtx (mode); +}) + ;; Convert HImode/SImode test instructions with immediate to QImode ones. ;; i386 does not allow to encode test with 8bit sign extended immediate, so ;; this is relatively important trick. diff --git a/gcc/testsuite/gcc.target/i386/pr91400-1.c b/gcc/testsuite/gcc.target/i386/pr91400-1.c index 6124058..751dc6c 100644 --- a/gcc/testsuite/gcc.target/i386/pr91400-1.c +++ b/gcc/testsuite/gcc.target/i386/pr91400-1.c @@ -1,8 +1,8 @@ /* PR target/91400 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-times "andl" 1 } } */ -/* { dg-final { scan-assembler-times "cmpl" 1 } } */ +/* { dg-final { scan-assembler-times "notl" 1 } } */ +/* { dg-final { scan-assembler-times "testb" 1 } } */ /* { dg-final { scan-assembler-times "sete" 1 } } */ /* { dg-final { scan-assembler-not "cmove" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr91400-2.c b/gcc/testsuite/gcc.target/i386/pr91400-2.c index 1af5a2f..914acd7 100644 --- a/gcc/testsuite/gcc.target/i386/pr91400-2.c +++ b/gcc/testsuite/gcc.target/i386/pr91400-2.c @@ -1,8 +1,8 @@ /* PR target/91400 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-times "andl" 1 } } */ -/* { dg-final { scan-assembler-times "cmpl" 1 } } */ +/* { dg-final { scan-assembler-times "notl" 1 } } */ +/* { dg-final { scan-assembler-times "testb" 1 } } */ /* { dg-final { scan-assembler-times "sete" 1 } } */ /* { dg-final { scan-assembler-not "cmove" } } */ diff --git a/gcc/testsuite/gcc.target/i386/testnot-1.c b/gcc/testsuite/gcc.target/i386/testnot-1.c new file mode 100644 index 0000000..9ebcb5c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/testnot-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x) +{ + return (x & 1234) == 1234; +} + +int foos(short x) +{ + return (x & 1234) == 1234; +} + +int fooc(char x) +{ + return (x & 123) == 123; +} + +int fool(long long x) +{ + return (x & 1234) == 1234; +} + +/* { dg-final { scan-assembler-not "cmp" } } */ diff --git a/gcc/testsuite/gcc.target/i386/testnot-2.c b/gcc/testsuite/gcc.target/i386/testnot-2.c new file mode 100644 index 0000000..52fdaf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/testnot-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x & y) == y; +} + +int foos(short x, short y) +{ + return (x & y) == y; +} + +int fooc(char x, char y) +{ + return (x & y) == y; +} + +int fool(long long x, long long y) +{ + return (x & y) == y; +} + +/* { dg-final { scan-assembler-not "cmp" } } */