From patchwork Tue May 17 15:52:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 54101 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2E2903857823 for ; Tue, 17 May 2022 15:52:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 9DDD93858D3C for ; Tue, 17 May 2022 15:52:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9DDD93858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=V10TSnc81vulhmUleWaGvdBTwQ61C3sUIE/xb7TcpAk=; b=miHyeD+xXvjYUOJDpjPMzwpvlM bIOmyVxS9Xb8o/Q5ilLA7IlfY8HKEiA03c8hA07aTidpG1D6MBGT2qeX8HNOwbvMuGUeiyS0K+7rp L9IQXSOD7HcG5G0zHXr6vfEINB6hbpTIls5ZlBL6GEynWOUvbHG2PCoUQ5TUecCc0GArfrbGdBtJV vpJYfoVCjV64BfM+KJjL30vO2QSdE68Fd/6ia25RZvrIRV6yuKao4X5RuLgVKYssN7pTKwqo1eWfv bcMQMFql6wLivVXG4bGEG+/866Bbp59TrzIGotoqfR85J/RUsf5+zfIdTEQ1xJFWI+LgfYbiUwlxC 7Y5hDmvQ==; Received: from host109-154-46-241.range109-154.btcentralplus.com ([109.154.46.241]:51545 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nqzUn-00079F-Vt; Tue, 17 May 2022 11:52:26 -0400 From: "Roger Sayle" To: Subject: [x86 PATCH take 2] Avoid andn and generate shorter not;and with -Oz. Date: Tue, 17 May 2022 16:52:23 +0100 Message-ID: <004601d86a06$1aa55320$4feff960$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdhqBHZIxXVOidlHT1aB4JVA1r8mkw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This is a revised version of my i386 backend patch to avoid andn with -Oz, when an explicit not;and (or not;test) would be (one byte) shorter. https://gcc.gnu.org/pipermail/gcc-patches/2022-April/593168.html This revision incorporates Michael Matz's feedback/suggestions with explicit checks for LEGACY_INT_REG_P and REX_INT_REG_P. This patch has been tested against gcc13 trunk on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2022-05-17 Roger Sayle gcc/ChangeLog * config/i386/i386.md (define_split): Split *andsi_1 and *andn_si_ccno after reload with -Oz. gcc/testsuite/ChangeLog * gcc.target/i386/bmi-and-3.c: New test case. Thanks in advance, Roger --- > -----Original Message----- > From: Michael Matz > Sent: 13 April 2022 14:11 > To: Roger Sayle > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [x86 PATCH] Avoid andn and generate shorter not;and with -Oz. > > Hello, > > On Wed, 13 Apr 2022, Roger Sayle wrote: > > > The x86 instruction encoding for SImode andn is longer than the > > equivalent notl/andl sequence when the source for the not operand is > > the same register as the destination. > > _And_ when no REX prefixes are necessary for the notl,andn, which they are if > the respective registers are %r8 or beyond. As you seem to be fine with saving > just a byte you ought to test that as well to not waste one again :-) > > > Ciao, > Michael. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f9c06ff..33473c6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10401,6 +10401,40 @@ [(set_attr "type" "bitmanip") (set_attr "btver2_decode" "direct, double") (set_attr "mode" "")]) + +;; Split *andnsi_1 after reload with -Oz when not;and is shorter. +(define_split + [(set (match_operand:SI 0 "register_operand") + (and:SI (not:SI (match_operand:SI 1 "register_operand")) + (match_operand:SI 2 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "reload_completed + && optimize_insn_for_size_p () && optimize_size > 1 + && REGNO (operands[0]) == REGNO (operands[1]) + && LEGACY_INT_REG_P (operands[0]) + && !REX_INT_REG_P (operands[2]) + && !reg_overlap_mentioned_p (operands[0], operands[2])" + [(set (match_dup 0) (not:SI (match_dup 1))) + (parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])]) + +;; Split *andn_si_ccno with -Oz when not;test is shorter. +(define_split + [(set (match_operand 0 "flags_reg_operand") + (match_operator 1 "compare_operator" + [(and:SI (not:SI (match_operand:SI 2 "general_reg_operand")) + (match_operand:SI 3 "nonimmediate_operand")) + (const_int 0)])) + (clobber (match_dup 2))] + "reload_completed + && optimize_insn_for_size_p () && optimize_size > 1 + && LEGACY_INT_REG_P (operands[2]) + && !REX_INT_REG_P (operands[3]) + && !reg_overlap_mentioned_p (operands[2], operands[3])" + [(set (match_dup 2) (not:SI (match_dup 2))) + (set (match_dup 0) (match_op_dup 1 + [(and:SI (match_dup 3) (match_dup 2)) + (const_int 0)]))]) ;; Logical inclusive and exclusive OR instructions diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-3.c b/gcc/testsuite/gcc.target/i386/bmi-andn-3.c new file mode 100644 index 0000000..16993a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/bmi-andn-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-Oz -mbmi" } */ +int m; + +int foo(int x, int y) +{ + return (x & ~y) != 0; +} + +int bar(int x) +{ + return (~x & m) != 0; +} +/* { dg-final { scan-assembler-not "andn\[ \\t\]+" } } */ +