From patchwork Tue Jan 11 13:26:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 49838 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 849D238A942A for ; Tue, 11 Jan 2022 13:30:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 53E2338A9417 for ; Tue, 11 Jan 2022 13:26:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 53E2338A9417 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=tgPZI4jgfPgC/QWyg8lrjwKrgZXkRqa0rAUzSnEiFww=; b=lJrRG23KVzlQmyRJVDPqnh7vmK 0qGqiFFHy2xozO1nL3SKe8u0gCy1kq6yt3MmTby4jLV5NBzM4hlEB2oBtJCtcVeIAKJ4stjkiA1Ay ceWbwPABQozMgdXATpwO+3qEqBmB/Se/RyqgdYwM1aT75Mh6R9sjQczaELhck44oob3WL/pub5UW3 EqO1G5BiQ57+P/c0LnhpC8cQgexa6BB3mLY8hl3gVGnFTAUFw0LXkMfdExIInbAzdbykHK12wL0GT Nv/ohsYKys9JyZH7vH3R229OcVTVdawxbHV8lWCLF3as8c2Db3VXTerzSPS7w0Zu7SikKb30cU4SU CigC9ZCA==; Received: from host86-160-23-130.range86-160.btcentralplus.com ([86.160.23.130]:53295 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n7HAn-0001UU-Fs; Tue, 11 Jan 2022 08:26:49 -0500 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] x86_64: Improvements to arithmetic right shifts of V1TImode values. Date: Tue, 11 Jan 2022 13:26:48 -0000 Message-ID: <001a01d806ee$e39c15f0$aad441d0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdgG7e98p/TKWGujROakAPzYBIC8/Q== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch to the i386 backend's ix86_expand_v1ti_ashiftrt provides improved (shorter) implementations of V1TI mode arithmetic right shifts for constant amounts between 111 and 126 bits. The significance of this range is that this functionality is useful for (eventually) providing sign extension from HImode and QImode to V1TImode. For example, x>>112 (to sign extend a 16-bit value), was previously generated as a four operation sequence: movdqa %xmm0, %xmm1 // word 7 6 5 4 3 2 1 0 psrad $31, %xmm0 // V8HI = [S,S,?,?,?,?,?,?] psrad $16, %xmm1 // V8HI = [S,X,?,?,?,?,?,?] punpckhqdq %xmm0, %xmm1 // V8HI = [S,S,?,?,S,X,?,?] pshufd $253, %xmm1, %xmm0 // V8HI = [S,S,S,S,S,S,S,X] with this patch, we now generates a three operation sequence: psrad $16, %xmm0 // V8HI = [S,X,?,?,?,?,?,?] pshufhw $254, %xmm0, %xmm0 // V8HI = [S,S,S,X,?,?,?,?] pshufd $254, %xmm0, %xmm0 // V8HI = [S,S,S,S,S,S,S,X] The correctness of generated code is confirmed by the existing run-time test gcc.target/i386/sse2-v1ti-ashiftrt-1.c in the testsuite. This idiom is safe to use for shifts by 127, but that case gets handled by a two operation sequence earlier in this function. This patch has been tested on x86_64-pc-linux-gnu with a make bootstrap and make -k check with no new failures. OK for mainline? 2022-01-11 Roger Sayle gcc/ChangeLog * config/i386/i386-expand.c (ix86_expand_v1ti_ashiftrt): Provide new three operation implementations for shifts by 111..126 bits. Thanks in advance, Roger diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 95bba25..3138b5f 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -6470,12 +6470,12 @@ ix86_expand_v1ti_ashiftrt (rtx operands[]) if (bits == 96) { /* Three operations. */ - rtx tmp3 = gen_reg_rtx (V2DImode); rtx tmp1 = gen_reg_rtx (V4SImode); rtx tmp2 = gen_reg_rtx (V4SImode); emit_move_insn (tmp1, gen_lowpart (V4SImode, op1)); emit_insn (gen_ashrv4si3 (tmp2, tmp1, GEN_INT (31))); + rtx tmp3 = gen_reg_rtx (V2DImode); rtx tmp4 = gen_reg_rtx (V2DImode); rtx tmp5 = gen_reg_rtx (V2DImode); emit_move_insn (tmp3, gen_lowpart (V2DImode, tmp1)); @@ -6493,6 +6493,30 @@ ix86_expand_v1ti_ashiftrt (rtx operands[]) return; } + if (bits >= 111) + { + /* Three operations. */ + rtx tmp1 = gen_reg_rtx (V4SImode); + rtx tmp2 = gen_reg_rtx (V4SImode); + emit_move_insn (tmp1, gen_lowpart (V4SImode, op1)); + emit_insn (gen_ashrv4si3 (tmp2, tmp1, GEN_INT (bits - 96))); + + rtx tmp3 = gen_reg_rtx (V8HImode); + rtx tmp4 = gen_reg_rtx (V8HImode); + emit_move_insn (tmp3, gen_lowpart (V8HImode, tmp2)); + emit_insn (gen_sse2_pshufhw (tmp4, tmp3, GEN_INT (0xfe))); + + rtx tmp5 = gen_reg_rtx (V4SImode); + rtx tmp6 = gen_reg_rtx (V4SImode); + emit_move_insn (tmp5, gen_lowpart (V4SImode, tmp4)); + emit_insn (gen_sse2_pshufd (tmp6, tmp5, GEN_INT (0xfe))); + + rtx tmp7 = gen_reg_rtx (V1TImode); + emit_move_insn (tmp7, gen_lowpart (V1TImode, tmp6)); + emit_move_insn (operands[0], tmp7); + return; + } + if (TARGET_AVX2 || TARGET_SSE4_1) { /* Three operations. */