From patchwork Mon May 23 07:16:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 54274 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9CB35383A33E for ; Mon, 23 May 2022 07:17:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 5C949383E698 for ; Mon, 23 May 2022 07:16:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5C949383E698 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=09WtDszSCxD2AAxN4jBPZS/w3LQNUmhidnGB09tF7HU=; b=VW5T3XfyJKhQPUwIKD2lNFEgwb zgxNmR50fXKQEw/lfMzoTj3VHcMtDLYVhSuoD5xDELgeig1DQTkML3zsNt6L89CMVFGr2HbirgVzy QbrW0InGI0ecixHZuI+VTtKzynJpuPpDyrwsV7oiHsZ2TtbciCoByghgqVUHFeXJVKKdQGEWtK9gk w/raV5dqOVSBuEw2QKNhMXUyXjArwJch9PTgbGqwjxHnzrUbg9qtMB5RG0B/6ye9vMbx6cHhzeFDC 6BS6qK3enTij9qHNevt4ecvHpNNLA65fDcRvU8eXUoJrZYahxHVARsj51SSjMfoVsaDUqC8cTNsCG pvIyjhVw==; Received: from host109-154-46-241.range109-154.btcentralplus.com ([109.154.46.241]:51342 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nt2JC-0001l3-KJ; Mon, 23 May 2022 03:16:54 -0400 From: "Roger Sayle" To: Subject: [x86 PATCH] PR tree-optimization/105668: Provide vcond_mask_v1tiv1ti pattern. Date: Mon, 23 May 2022 08:16:50 +0100 Message-ID: <001601d86e75$13b5cc20$3b216460$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdhudF75dgS/0MqjSQ+u2+iDbWSv0Q== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch is an alternate/supplementary fix to PR tree-optimization/105668 that provides a vcond_mask_v1titi optab/define_expand to the i386 backend. An undocumented feature/bug of GCC's vectorization is that any target that provides a vec_cmpeq has to also provide a matching vcond_mask. This backend patch preserves the status quo, rather than fixes the underlying problem. One aspect of this clean-up is that ix86_expand_sse_movcc provides fallback implementations using pand/pandn/por that effectively make V2DImode and V1TImode vcond_mask available on any TARGET_SSE2, not just TARGET_SSE4_2. This allows a simplification as V2DI mode can be handled by using a VI_128 mode iterator instead of a VI124_128 mode iterator, and instead this define_expand is effectively renamed to provide a V1TImode vcond_mask expander (as V1TI isn't in VI_128). This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. The new test case is identical to the middle-end patch, so if both patches are approved, this'll be committed only once. Ok for mainline? 2022-05-23 Roger Sayle gcc/ChangeLog PR tree-optimization/105668 * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Support V1TImode, just like V2DImode. * config/i386/sse.md (vcond_mask_Msseintvecmodelower>): Use VI_128 mode iterator instead of VI124_128 to include V2DI. (vcond_mask_v2div2di): Delete. (vcond_mask_v1tiv1ti): New define_expand. gcc/testsuite/ChangeLog PR tree-optimization/105668 * gcc.target/i386/pr105668.c: New test case. Roger diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 1460bcc..e3bd661 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -4026,6 +4026,7 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) case E_V8HFmode: case E_V4SImode: case E_V2DImode: + case E_V1TImode: if (TARGET_SSE4_1) { gen = gen_sse4_1_pblendvb; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 191371b..f261ff6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4579,10 +4579,10 @@ }) (define_expand "vcond_mask_" - [(set (match_operand:VI124_128 0 "register_operand") - (vec_merge:VI124_128 - (match_operand:VI124_128 1 "vector_operand") - (match_operand:VI124_128 2 "nonimm_or_0_operand") + [(set (match_operand:VI_128 0 "register_operand") + (vec_merge:VI_128 + (match_operand:VI_128 1 "vector_operand") + (match_operand:VI_128 2 "nonimm_or_0_operand") (match_operand: 3 "register_operand")))] "TARGET_SSE2" { @@ -4591,13 +4591,13 @@ DONE; }) -(define_expand "vcond_mask_v2div2di" - [(set (match_operand:V2DI 0 "register_operand") - (vec_merge:V2DI - (match_operand:V2DI 1 "vector_operand") - (match_operand:V2DI 2 "nonimm_or_0_operand") - (match_operand:V2DI 3 "register_operand")))] - "TARGET_SSE4_2" +(define_expand "vcond_mask_v1tiv1ti" + [(set (match_operand:V1TI 0 "register_operand") + (vec_merge:V1TI + (match_operand:V1TI 1 "vector_operand") + (match_operand:V1TI 2 "nonimm_or_0_operand") + (match_operand:V1TI 3 "register_operand")))] + "TARGET_SSE2" { ix86_expand_sse_movcc (operands[0], operands[3], operands[1], operands[2]); diff --git a/gcc/testsuite/gcc.target/i386/pr105668.c b/gcc/testsuite/gcc.target/i386/pr105668.c new file mode 100644 index 0000000..359c2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105668.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O -ftracer -fno-tree-fre" } */ + +typedef __int128 __attribute__((__vector_size__ (16))) V; + +int i; + +V +foo (_Complex float f) +{ + (void) __builtin_atanhf (i); + V v = i != (V) { }; + i ^= f && 8; + v %= 5; + return v; +}