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Sun, 05 Mar 2023 19:17:04 -0800 (PST) Received: from [192.168.86.117] ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id a20-20020aed2794000000b003a81eef14efsm6799808qtd.45.2023.03.05.19.17.03 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 05 Mar 2023 19:17:04 -0800 (PST) Message-ID: <00013323-7689-85c3-f10a-45f90e746868@rivosinc.com> Date: Sun, 5 Mar 2023 22:17:03 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 From: Michael Collison Subject: [PATCH v2 07/07] RISC-V: autovec: Add autovectorization patterns for add & sub To: gcc-patches Content-Language: en-US X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds tests for autovectorization of integer add and subtract. gcc/testsuite/ChangeLog: 2023-03-02  Michael Collison                     Vineet Gupta                 * gcc.target/riscv/rvv/autovec: New directory                 for autovectorization tests.                 * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New                 test to verify code generation of vector add on rv32.                 * gcc.target/riscv/rvv/autovec/loop-add.c: New                 test to verify code generation of vector add on rv64.                 * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New                 test to verify code generation of vector subtract on rv32.                 * gcc.target/riscv/rvv/autovec/loop-sub.c: New                 test to verify code generation of vector subtract on rv64. ---  .../riscv/rvv/autovec/loop-add-rv32.c         | 24 +++++++++++++++++++  .../gcc.target/riscv/rvv/autovec/loop-add.c   | 24 +++++++++++++++++++  .../riscv/rvv/autovec/loop-sub-rv32.c         | 24 +++++++++++++++++++  .../gcc.target/riscv/rvv/autovec/loop-sub.c   | 24 +++++++++++++++++++  4 files changed, 96 insertions(+)  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c new file mode 100644 index 00000000000..bdc3b6892e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE)                 \ +  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \ +  {                            \ +    for (int i = 0; i < n; i++)                \ +      dst[i] = a[i] + b[i];                \ +  } + +/* *int8_t not autovec currently. */ +#define TEST_ALL()    \ + TEST_TYPE(int16_t)    \ + TEST_TYPE(uint16_t)    \ + TEST_TYPE(int32_t)    \ + TEST_TYPE(uint32_t)    \ + TEST_TYPE(int64_t)    \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c new file mode 100644 index 00000000000..d7f992c7d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE)                 \ +  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \ +  {                            \ +    for (int i = 0; i < n; i++)                \ +      dst[i] = a[i] + b[i];                \ +  } + +/* *int8_t not autovec currently. */ +#define TEST_ALL()    \ + TEST_TYPE(int16_t)    \ + TEST_TYPE(uint16_t)    \ + TEST_TYPE(int32_t)    \ + TEST_TYPE(uint32_t)    \ + TEST_TYPE(int64_t)    \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c new file mode 100644 index 00000000000..7d0a40ec539 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE)                 \ +  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \ +  {                            \ +    for (int i = 0; i < n; i++)                \ +      dst[i] = a[i] - b[i];                \ +  } + +/* *int8_t not autovec currently. */ +#define TEST_ALL()    \ + TEST_TYPE(int16_t)    \ + TEST_TYPE(uint16_t)    \ + TEST_TYPE(int32_t)    \ + TEST_TYPE(uint32_t)    \ + TEST_TYPE(int64_t)    \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c new file mode 100644 index 00000000000..c8900884f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE)                 \ +  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \ +  {                            \ +    for (int i = 0; i < n; i++)                \ +      dst[i] = a[i] - b[i];                \ +  } + +/* *int8_t not autovec currently. */ +#define TEST_ALL()    \ + TEST_TYPE(int16_t)    \ + TEST_TYPE(uint16_t)    \ + TEST_TYPE(int32_t)    \ + TEST_TYPE(uint32_t)    \ + TEST_TYPE(int64_t)    \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */