Show patches with: Submitter = Tamar Christina       |    State = Action Required       |    Archived = No       |   71 patches
Patch Series rb/tb S/W/F Date Submitter Delegate State
AArch64 div-by-255, ensure that arguments are registers. [PR107988] AArch64 div-by-255, ensure that arguments are registers. [PR107988] - - --- 2022-12-08 Tamar Christina New
AArch64 sve2: Fix expansion of division [PR107830] AArch64 sve2: Fix expansion of division [PR107830] - - --- 2022-11-23 Tamar Christina New
middle-end: ensure that VEC_PERM operands get lowered to the same SSA_NAME. [PR107717] middle-end: ensure that VEC_PERM operands get lowered to the same SSA_NAME. [PR107717] - - --- 2022-11-17 Tamar Christina New
middle-end: replace GET_MODE_WIDER_MODE with GET_MODE_NEXT_MODE middle-end: replace GET_MODE_WIDER_MODE with GET_MODE_NEXT_MODE - - --- 2022-11-15 Tamar Christina New
AArch64 Fix vector re-interpretation between partial SIMD modes AArch64 Fix vector re-interpretation between partial SIMD modes - - --- 2022-11-11 Tamar Christina New
[i386] : Update ix86_can_change_mode_class target hook to accept QImode conversions [i386] : Update ix86_can_change_mode_class target hook to accept QImode conversions - - --- 2022-11-11 Tamar Christina New
[2/2] AArch64 Add implementation for vector cbranch. [1/2] middle-end: Support early break/return auto-vectorization. - - --- 2022-11-02 Tamar Christina New
[1/2] middle-end: Support early break/return auto-vectorization. [1/2] middle-end: Support early break/return auto-vectorization. - - --- 2022-11-02 Tamar Christina New
[8/8] AArch64: Have reload not choose to do add on the scalar side if both values exist on the SIMD… [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[7/8] AArch64: Consolidate zero and sign extension patterns and add missing ones. [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[6/8] AArch64: Add peephole and scheduling logic for pairwise operations that appear late in RTL. [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[5/8] AArch64 aarch64: Make existing V2HF be usable. [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[4/8] AArch64 aarch64: Implement widening reduction patterns [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[3/8] middle-end: Support extractions of subvectors from arbitrary element position inside a vector [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[2/8] middle-end: Recognize scalar widening reductions [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
[1/8] middle-end: Recognize scalar reductions from bitfields and array_refs [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina New
AArch64 Extend umov and sbfx patterns. AArch64 Extend umov and sbfx patterns. - - --- 2022-10-31 Tamar Christina New
[2/2] AArch64 Support new tbranch optab. [1/2] middle-end: Add new tbranch optab to add support for bit-test-and-branch operations - - --- 2022-10-31 Tamar Christina New
[1/2] middle-end: Add new tbranch optab to add support for bit-test-and-branch operations [1/2] middle-end: Add new tbranch optab to add support for bit-test-and-branch operations - - --- 2022-10-31 Tamar Christina New
[2/2] AArch64 Perform more late folding of reg moves and shifts which arrive after expand [1/2] middle-end Fold BIT_FIELD_REF and Shifts into BIT_FIELD_REFs alone - - --- 2022-09-23 Tamar Christina New
[1/2] middle-end Fold BIT_FIELD_REF and Shifts into BIT_FIELD_REFs alone [1/2] middle-end Fold BIT_FIELD_REF and Shifts into BIT_FIELD_REFs alone - - --- 2022-09-23 Tamar Christina New
[4/4] AArch64 sve2: rewrite pack + NARROWB + NARROWB to NARROWB + NARROWT [1/2] middle-end Support optimized division by pow2 bitmask - - --- 2022-09-23 Tamar Christina New
[3/4] AArch64 Add SVE2 implementation for pow2 bitmask division [1/2] middle-end Support optimized division by pow2 bitmask - - --- 2022-09-23 Tamar Christina New
[2/4] AArch64 Add implementation for pow2 bitmask division. Untitled series #12466 - - --- 2022-09-23 Tamar Christina New
[2/2] AArch64 Extend tbz pattern to allow SI to SI extensions. Untitled series #12465 - - --- 2022-09-23 Tamar Christina New
[1/2] middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type … [1/2] middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type … - - --- 2022-09-23 Tamar Christina New
middle-end fix floating out of constants in conditionals middle-end fix floating out of constants in conditionals - - --- 2022-09-23 Tamar Christina New
middle-end Recognize more conditional comparisons idioms. middle-end Recognize more conditional comparisons idioms. - - --- 2022-09-23 Tamar Christina New
[2/2] AArch64 Add support for neg on v1df [1/2] middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type … - - --- 2022-09-23 Tamar Christina New
middle-end: Fix phi-ssa assertion triggers. [PR106519] middle-end: Fix phi-ssa assertion triggers. [PR106519] - - --- 2022-08-04 Tamar Christina New
middle-end: don't lower past veclower [PR106063] middle-end: don't lower past veclower [PR106063] - - --- 2022-07-05 Tamar Christina New
middle-end simplify complex if expressions where comparisons are inverse of one another. middle-end simplify complex if expressions where comparisons are inverse of one another. - - --- 2022-06-16 Tamar Christina New
[2/2] middle-end: Support recognition of three-way max/min. [1/2] middle-end: Simplify subtract where both arguments are being bitwise inverted. - - --- 2022-06-16 Tamar Christina New
[1/2] middle-end: Simplify subtract where both arguments are being bitwise inverted. [1/2] middle-end: Simplify subtract where both arguments are being bitwise inverted. - - --- 2022-06-16 Tamar Christina New
middle-end Add optimized float addsub without needing VEC_PERM_EXPR. middle-end Add optimized float addsub without needing VEC_PERM_EXPR. - - --- 2022-06-16 Tamar Christina New
[2/2] Add SVE fallback case using sdot for usdot [1/2] AArch64 Add fallback case using sdot for usdot - - --- 2022-06-16 Tamar Christina New
[1/2] AArch64 Add fallback case using sdot for usdot [1/2] AArch64 Add fallback case using sdot for usdot - - --- 2022-06-16 Tamar Christina New
middle-end Use subregs to expand COMPLEX_EXPR to set the lowpart. middle-end Use subregs to expand COMPLEX_EXPR to set the lowpart. - - --- 2022-06-09 Tamar Christina New
[2/2] AArch64 aarch64: Add implementation for pow2 bitmask division. [1/2] middle-end Support optimized division by pow2 bitmask - - --- 2022-06-09 Tamar Christina New
[1/2] middle-end Support optimized division by pow2 bitmask [1/2] middle-end Support optimized division by pow2 bitmask - - --- 2022-06-09 Tamar Christina New
AArch64 relax predicate on load structure load instructions AArch64 relax predicate on load structure load instructions - - --- 2022-06-08 Tamar Christina New
[3/3] AArch64 Update the testsuite to remove xfails. [1/3] middle-end: Add the ability to let the target decide the method of argument promotions. - - --- 2022-05-13 Tamar Christina New
[2/3] AArch64 Promote function arguments using a paradoxical subreg when beneficial. [1/3] middle-end: Add the ability to let the target decide the method of argument promotions. - - --- 2022-05-13 Tamar Christina New
[1/3] middle-end: Add the ability to let the target decide the method of argument promotions. [1/3] middle-end: Add the ability to let the target decide the method of argument promotions. - - --- 2022-05-13 Tamar Christina New
middle-end testsuite: Backport testsuite changes from GCC 12 to GCC 11 middle-end testsuite: Backport testsuite changes from GCC 12 to GCC 11 - - --- 2022-04-28 Tamar Christina New
AArch64 Fix left fold sum reduction RTL patterns [PR104049] AArch64 Fix left fold sum reduction RTL patterns [PR104049] - - --- 2022-04-05 Tamar Christina New
[2/2] middle-end Backport complex vect testsuite to GCC 11 [1/2] middle-end Handle difference between complex negations in SLP tree better (GCC 11 backport) - - --- 2022-02-28 Tamar Christina New
[1/2] middle-end Handle difference between complex negations in SLP tree better (GCC 11 backport) [1/2] middle-end Handle difference between complex negations in SLP tree better (GCC 11 backport) - - --- 2022-02-28 Tamar Christina New
middle-end vect: Simplify and extend the complex numbers validation routines. (GCC-11 Backport) middle-end vect: Simplify and extend the complex numbers validation routines. (GCC-11 Backport) - - --- 2022-02-24 Tamar Christina New
[AArch32] : correct dot-product RTL patterns. [AArch32] : correct dot-product RTL patterns. - - --- 2021-12-21 Tamar Christina New
[3/3,AArch32] use canonical ordering for complex mul, fma and fms [1/3] middle-end vect: Simplify and extend the complex numbers validation routines. - - --- 2021-12-17 Tamar Christina New
[2/3] AArch64 use canonical ordering for complex mul, fma and fms [1/3] middle-end vect: Simplify and extend the complex numbers validation routines. - - --- 2021-12-17 Tamar Christina New
[1/3] middle-end vect: Simplify and extend the complex numbers validation routines. [1/3] middle-end vect: Simplify and extend the complex numbers validation routines. - - --- 2021-12-17 Tamar Christina New
AArch64 Fix the AAPCs for new partial and full SIMD structure types [PR103094] AArch64 Fix the AAPCs for new partial and full SIMD structure types [PR103094] - - --- 2021-12-14 Tamar Christina New
middle-end: move bitmask match.pd pattern and update tests middle-end: move bitmask match.pd pattern and update tests - - --- 2021-11-29 Tamar Christina New
middle-end cse: Make sure duplicate elements are not entered into the equivalence set [PR103404] middle-end cse: Make sure duplicate elements are not entered into the equivalence set [PR103404] - - --- 2021-11-29 Tamar Christina New
middle-end: Handle FMA_CONJ correctly after SLP layout update. middle-end: Handle FMA_CONJ correctly after SLP layout update. - - --- 2021-11-19 Tamar Christina New
AArch64 Optimize right shift rounding narrowing AArch64 Optimize right shift rounding narrowing - - --- 2021-11-12 Tamar Christina New
Arm Update missing entries of cost tables Arm Update missing entries of cost tables - - --- 2021-11-10 Tamar Christina New
middle-end Add an RPO pass after successful vectorization middle-end Add an RPO pass after successful vectorization - - --- 2021-11-02 Tamar Christina New
[1/2] middle-end Update the complex numbers auto-vec detection to the new format of the SLP tree. [1/2] middle-end Update the complex numbers auto-vec detection to the new format of the SLP tree. - - --- 2021-10-29 Tamar Christina New
middle-end: fix de-optimizations with bitclear patterns on signed values middle-end: fix de-optimizations with bitclear patterns on signed values - - --- 2021-10-15 Tamar Christina New
AArch64 Lower intrinsics shift to GIMPLE when possible. AArch64 Lower intrinsics shift to GIMPLE when possible. - - --- 2021-10-15 Tamar Christina New
middle-end convert negate + right shift into compare greater. middle-end convert negate + right shift into compare greater. - - --- 2021-10-05 Tamar Christina New
[7/7] AArch64 Combine cmeq 0 + not into cmtst AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New
[6/7] AArch64 Add neg + cmle into cmgt AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New
[5/7] middle-end Convert bitclear <imm> + cmp<cc> #0 into cm<cc2> <imm2> AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New
[4/7] AArch64 Add pattern xtn+xtn2 to uzp2 AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New
[3/7] AArch64 Add pattern for sshr to cmlt AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New
[2/7] AArch64 Add combine patterns for narrowing shift of half top bits (shuffle) AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New
[1/7] AArch64 Add combine patterns for right shift and narrow AArch64 Optimize truncation, shifts and bitmask comparisons - - --- 2021-09-29 Tamar Christina New