Show patches with: Submitter = Roger Sayle       |    State = Action Required       |    Archived = No       |   43 patches
Patch Series rb/tb S/W/F Date Submitter Delegate State
PR middle-end/104140: bootstrap ICE on riscv. PR middle-end/104140: bootstrap ICE on riscv. - - --- 2022-01-21 Roger Sayle New
nvptx: Fix and use BI mode logic instructions (e.g. and.pred). nvptx: Fix and use BI mode logic instructions (e.g. and.pred). - - --- 2022-01-16 Roger Sayle New
nvptx: Add support for 64-bit mul.hi (and other) instructions. nvptx: Add support for 64-bit mul.hi (and other) instructions. - - --- 2022-01-14 Roger Sayle New
x86_64: Improvements to arithmetic right shifts of V1TImode values. x86_64: Improvements to arithmetic right shifts of V1TImode values. - - --- 2022-01-11 Roger Sayle New
nvptx: Expand QI mode operations using SI mode instructions. nvptx: Expand QI mode operations using SI mode instructions. - - --- 2022-01-10 Roger Sayle New
nvptx: Improved support for HFMode including neghf2 and abshf2. nvptx: Improved support for HFMode including neghf2 and abshf2. - - --- 2022-01-08 Roger Sayle New
[take,#3] Recognize MULT_HIGHPART_EXPR in tree-ssa-math-opts pass. [take,#3] Recognize MULT_HIGHPART_EXPR in tree-ssa-math-opts pass. - - --- 2022-01-06 Roger Sayle New
[take,#3] PR target/103773: Fix wrong-code with -Oz from pop to memory. [take,#3] PR target/103773: Fix wrong-code with -Oz from pop to memory. - - --- 2021-12-23 Roger Sayle New
x86: Shrink writing 0/-1 to memory using and/or with -Oz. x86: Shrink writing 0/-1 to memory using and/or with -Oz. - - --- 2021-12-21 Roger Sayle New
PR target/103773: Fix wrong-code with -Oz from pop to memory. PR target/103773: Fix wrong-code with -Oz from pop to memory. - - --- 2021-12-21 Roger Sayle New
x86: PR target/103611: Splitter for DST:DI = (HI:SI<<32)|LO:SI. x86: PR target/103611: Splitter for DST:DI = (HI:SI<<32)|LO:SI. - - --- 2021-12-13 Roger Sayle New
PR target/103611: Avoid generating orb $0, %ah on x86. PR target/103611: Avoid generating orb $0, %ah on x86. - - --- 2021-12-13 Roger Sayle New
PR target/32803: Add -Oz option for improved clang compatibility. PR target/32803: Add -Oz option for improved clang compatibility. - - --- 2021-12-10 Roger Sayle New
mips: Improved RTL representation of wsbh/dsbh/dshd mips: Improved RTL representation of wsbh/dsbh/dshd - - --- 2021-12-10 Roger Sayle New
Improved handling of REG_UNUSED notes on PARALLEL in try_combine. Improved handling of REG_UNUSED notes on PARALLEL in try_combine. - - --- 2021-12-10 Roger Sayle New
x86_64: Improve code expanded for highpart multiplications. x86_64: Improve code expanded for highpart multiplications. - - --- 2021-12-10 Roger Sayle New
[take,#2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. [take,#2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. - - --- 2021-12-03 Roger Sayle New
Final value replacement improvements for until-wrap loops. Final value replacement improvements for until-wrap loops. - - --- 2021-11-29 Roger Sayle New
x86_64: PR target/100711: Splitters for pandn x86_64: PR target/100711: Splitters for pandn - - --- 2021-11-28 Roger Sayle New
[take,3] ivopts: Improve code generated for very simple loops. [take,3] ivopts: Improve code generated for very simple loops. - - --- 2021-11-25 Roger Sayle New
Tweak tree-ssa-math-opts.c to solve PR target/102117 Tweak tree-ssa-math-opts.c to solve PR target/102117 - - --- 2021-11-20 Roger Sayle New
[take,2] ivopts: Improve code generated for very simple loops. [take,2] ivopts: Improve code generated for very simple loops. - - --- 2021-11-18 Roger Sayle New
ivopts: Improve code generated for very simple loops. ivopts: Improve code generated for very simple loops. - - --- 2021-11-15 Roger Sayle New
x86_64: Improved implementation of TImode rotations. x86_64: Improved implementation of TImode rotations. - - --- 2021-11-01 Roger Sayle New
[Take,#2] x86_64: Expand ashrv1ti (and PR target/102986) [Take,#2] x86_64: Expand ashrv1ti (and PR target/102986) - - --- 2021-10-31 Roger Sayle New
x86_64: Expand ashrv1ti (and PR target/102986) x86_64: Expand ashrv1ti (and PR target/102986) - - --- 2021-10-30 Roger Sayle New
Constant fold/simplify SS_ASHIFT and US_ASHIFT in simplify-rtx.c Constant fold/simplify SS_ASHIFT and US_ASHIFT in simplify-rtx.c - - --- 2021-10-25 Roger Sayle New
x86_64: Add insn patterns for V1TI mode logic operations. x86_64: Add insn patterns for V1TI mode logic operations. - - --- 2021-10-22 Roger Sayle New
PR target/102785: Correct addsub/subadd patterns on bfin. PR target/102785: Correct addsub/subadd patterns on bfin. - - --- 2021-10-18 Roger Sayle New
bfin: Popcount-related improvements to machine description. bfin: Popcount-related improvements to machine description. - - --- 2021-10-17 Roger Sayle New
Constant fold SS_NEG and SS_ABS in simplify-rtx.c Constant fold SS_NEG and SS_ABS in simplify-rtx.c - - --- 2021-10-17 Roger Sayle New
x86_64: Some SUBREG related optimization tweaks to i386 backend. x86_64: Some SUBREG related optimization tweaks to i386 backend. - - --- 2021-10-11 Roger Sayle New
Transition nvptx backend to STORE_FLAG_VALUE = 1 Transition nvptx backend to STORE_FLAG_VALUE = 1 - - --- 2021-10-05 Roger Sayle New
[#2] Introduce smul_highpart and umul_highpart RTX for high-part multiplications [#2] Introduce smul_highpart and umul_highpart RTX for high-part multiplications - - --- 2021-09-29 Roger Sayle New
[RFC] Experimental __attribute__((saturating)) on integer types. [RFC] Experimental __attribute__((saturating)) on integer types. - - --- 2021-09-26 Roger Sayle New
Introduce sh_mul and uh_mul RTX codes for high-part multiplications Introduce sh_mul and uh_mul RTX codes for high-part multiplications - - --- 2021-09-25 Roger Sayle New
Make flag_trapping_math a non-binary Boolean. Make flag_trapping_math a non-binary Boolean. - - --- 2021-09-25 Roger Sayle New
[RFC/PATCH] C++ constexpr vs. floating point exceptions. [RFC/PATCH] C++ constexpr vs. floating point exceptions. - - --- 2021-09-21 Roger Sayle Changes Requested
PR middle-end/88173: More constant folding of NaN comparisons. PR middle-end/88173: More constant folding of NaN comparisons. - - --- 2021-09-18 Roger Sayle New
nvptx: Adds uses of -misa=sm_75 and -misa=sm_80 nvptx: Adds uses of -misa=sm_75 and -misa=sm_80 - - --- 2021-09-17 Roger Sayle New
nvptx: Add (experimental) support for HFmode with -misa=sm_53 nvptx: Add (experimental) support for HFmode with -misa=sm_53 - - --- 2021-09-16 Roger Sayle New
[#2] PR c/102245: Disable sign-changing optimization for shifts by zero. [#2] PR c/102245: Disable sign-changing optimization for shifts by zero. - - --- 2021-09-14 Roger Sayle New
PR c/102245: Don't warn that ((_Bool)x<<0) isn't a truthvalue. PR c/102245: Don't warn that ((_Bool)x<<0) isn't a truthvalue. - - --- 2021-09-13 Roger Sayle New