Show patches with: Archived = No       |   22722 patches
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Patch Series rb/tb S/W/F Date Submitter Delegate State
Warray-bounds: Warn only for generic address spaces Warray-bounds: Warn only for generic address spaces - - --- 2021-10-12 Siddhesh Poyarekar Dropped
Arm Update missing entries of cost tables Arm Update missing entries of cost tables - - --- 2021-11-10 Tamar Christina Dropped
libstdc++: Allow std::condition_variable waits to be cancelled [PR103382] libstdc++: Allow std::condition_variable waits to be cancelled [PR103382] - - --- 2021-12-07 Jonathan Wakely jwakely Dropped
middle-end/77608: object size estimate with variable offsets middle-end/77608: object size estimate with variable offsets - - --- 2022-01-05 Siddhesh Poyarekar Dropped
[GCC13] Don't force side effects for hardware vector element broadcast [GCC13] Don't force side effects for hardware vector element broadcast - - --- 2022-01-27 Maciej W. Rozycki Dropped
libstdc++: Gate constexpr string and vector on constexpr destructor support libstdc++: Gate constexpr string and vector on constexpr destructor support - - --- 2022-04-26 Jonathan Wakely Dropped
[1/3] middle-end: Add the ability to let the target decide the method of argument promotions. [1/3] middle-end: Add the ability to let the target decide the method of argument promotions. - - --- 2022-05-13 Tamar Christina Dropped
[2/3] AArch64 Promote function arguments using a paradoxical subreg when beneficial. [1/3] middle-end: Add the ability to let the target decide the method of argument promotions. - - --- 2022-05-13 Tamar Christina Dropped
[2/3,ARM] STAR-MC1 CPU Support - arm: Add individual star-mc1 cost tables and cost functions [1/3,ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core - - --- 2022-05-26 Chung-Ju Wu Dropped
AArch64 relax predicate on load structure load instructions AArch64 relax predicate on load structure load instructions - - --- 2022-06-08 Tamar Christina Dropped
[1/2] AArch64 Add fallback case using sdot for usdot [1/2] AArch64 Add fallback case using sdot for usdot - - --- 2022-06-16 Tamar Christina Dropped
[2/2] Add SVE fallback case using sdot for usdot [1/2] AArch64 Add fallback case using sdot for usdot - - --- 2022-06-16 Tamar Christina Dropped
libstdc++: 60241.cc: tolerate slightly shorter aggregate sleep libstdc++: 60241.cc: tolerate slightly shorter aggregate sleep - - --- 2022-06-22 Alexandre Oliva Dropped
libstdc++: async: tolerate slightly shorter sleep libstdc++: async: tolerate slightly shorter sleep - - --- 2022-06-22 Alexandre Oliva jwakely Dropped
libstdc++: retry removal of dir entries if dir removal fails libstdc++: retry removal of dir entries if dir removal fails - - --- 2022-06-22 Alexandre Oliva Dropped
[9/12,V2] arm: Make libgcc bti compatible Untitled series #11064 - - --- 2022-07-21 Andrea Corallo Dropped
[2/2] AArch64 Add support for neg on v1df [1/2] middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type … - - --- 2022-09-23 Tamar Christina Dropped
[1/2] middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type … [1/2] middle-end: RFC: On expansion of conditional branches, give hint if argument is a truth type … - - --- 2022-09-23 Tamar Christina Dropped
[4/4] AArch64 sve2: rewrite pack + NARROWB + NARROWB to NARROWB + NARROWT [1/2] middle-end Support optimized division by pow2 bitmask - - --- 2022-09-23 Tamar Christina Dropped
[2/2] AArch64 Perform more late folding of reg moves and shifts which arrive after expand [1/2] middle-end Fold BIT_FIELD_REF and Shifts into BIT_FIELD_REFs alone - - --- 2022-09-23 Tamar Christina Dropped
[1/8] middle-end: Recognize scalar reductions from bitfields and array_refs [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina Dropped
[2/8] middle-end: Recognize scalar widening reductions [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina Dropped
[3/8] middle-end: Support extractions of subvectors from arbitrary element position inside a vector [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina Dropped
[4/8] AArch64 aarch64: Implement widening reduction patterns [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina Dropped
[6/8] AArch64: Add peephole and scheduling logic for pairwise operations that appear late in RTL. [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina Dropped
[8/8] AArch64: Have reload not choose to do add on the scalar side if both values exist on the SIMD… [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - --- 2022-10-31 Tamar Christina Dropped
AArch64 relax constraints on FP16 insn PR108172 AArch64 relax constraints on FP16 insn PR108172 - - --- 2022-12-20 Tamar Christina Dropped
RISC-V: Avoid redundant flow in backward fusion RISC-V: Avoid redundant flow in backward fusion - - --- 2023-01-09 juzhe.zhong@rivai.ai Dropped
RISC-V: Call DCE to remove redundant instructions created by the PASS RISC-V: Call DCE to remove redundant instructions created by the PASS - - --- 2023-01-09 juzhe.zhong@rivai.ai Dropped
RISC-V: Remove DCE in VSETVL PASS RISC-V: Remove DCE in VSETVL PASS - - --- 2023-01-18 juzhe.zhong@rivai.ai Dropped
RISC-V: Bugfix for mode tieable of the rvv bool types RISC-V: Bugfix for mode tieable of the rvv bool types - - --- 2023-02-11 Li, Pan2 via Gcc-patches Dropped
libstdc++: Limit allocations in _Rb_tree 2/2 libstdc++: Limit allocations in _Rb_tree 2/2 - - --- 2023-02-22 François Dumont Dropped
[v2] RISC-V: Avoid calloc() poisoning on musl [v2] RISC-V: Avoid calloc() poisoning on musl - - --- 2023-03-11 Sam James Dropped
ISC-V: Fine tune vmadc/vmsbc RA constraint ISC-V: Fine tune vmadc/vmsbc RA constraint - - --- 2023-03-16 juzhe.zhong@rivai.ai Dropped
[V3] RISC-V: Fix a redefinition bug for the fd-4.c [V3] RISC-V: Fix a redefinition bug for the fd-4.c - - --- 2023-03-22 shiyulong@iscas.ac.cn Dropped
RISC-V: Fine tune RVV narrow instruction (source EEW > dest DEST) RA constraint RISC-V: Fine tune RVV narrow instruction (source EEW > dest DEST) RA constraint - - --- 2023-03-24 juzhe.zhong@rivai.ai Dropped
[GCC14,QUEUE] RISC-V: Fine tune RVV narrow instruction (source EEW > dest DEST) RA constraint [GCC14,QUEUE] RISC-V: Fine tune RVV narrow instruction (source EEW > dest DEST) RA constraint - - --- 2023-03-24 juzhe.zhong@rivai.ai Dropped
RISC-V: Add Z*inx incompatible check in gcc. RISC-V: Add Z*inx incompatible check in gcc. - - --- 2023-03-26 Jiawei Dropped
[2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern RISC-V:Enable basic auto-vectorization for RVV - - --- 2023-04-06 juzhe.zhong@rivai.ai JeffreyALaw Dropped
RISC-V: Add RVV auto-vectorization testcase RISC-V: Add RVV auto-vectorization testcase - - --- 2023-04-06 juzhe.zhong@rivai.ai Dropped
RISC-V: Add RVV auto-vectorization compile option RISC-V: Add RVV auto-vectorization compile option - - --- 2023-04-07 juzhe.zhong@rivai.ai Dropped
RISC-V: Enable basic RVV auto-vectorization support RISC-V: Enable basic RVV auto-vectorization support - - --- 2023-04-07 juzhe.zhong@rivai.ai Dropped
RISC-V: Add testcases for RVV auto-vectorization RISC-V: Add testcases for RVV auto-vectorization - - --- 2023-04-07 juzhe.zhong@rivai.ai Dropped
RISC-V: Fix EEW = 64 predicate RISC-V: Fix EEW = 64 predicate - - --- 2023-04-10 juzhe.zhong@rivai.ai Dropped
RISC-V: Allow LMUL = 2 auto-vectorization for zve32* RISC-V: Allow LMUL = 2 auto-vectorization for zve32* - - --- 2023-04-10 juzhe.zhong@rivai.ai Dropped
RISC-V: Fix PR109479 RISC-V: Fix PR109479 - - --- 2023-04-12 juzhe.zhong@rivai.ai Dropped
RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization - - --- 2023-04-19 Li, Pan2 via Gcc-patches Dropped
[1/3] RISC-V: Add auto-vectorization compile option for RVV [1/3] RISC-V: Add auto-vectorization compile option for RVV - - --- 2023-04-19 juzhe.zhong@rivai.ai Dropped
[2/3] RISC-V: Enable basic auto-vectorization for RVV RISC-V: Basic enable RVV auto-vectorizaiton - - --- 2023-04-19 juzhe.zhong@rivai.ai Dropped
[3/3] RISC-V: Add sanity testcases for RVV auto-vectorization RISC-V: Basic enable RVV auto-vectorizaiton - - --- 2023-04-19 juzhe.zhong@rivai.ai JeffreyALaw Dropped
[1/3] RISC-V: Add auto-vectorization compile option for RVV RISC-V: Basic enable RVV auto-vectorizaiton - - --- 2023-04-19 juzhe.zhong@rivai.ai JeffreyALaw Dropped
[3/3] RISC-V: Add sanity testcases for RVV auto-vectorization RISC-V: Basic enable RVV auto-vectorizaiton - - --- 2023-04-19 juzhe.zhong@rivai.ai Dropped
[2/3,V2] RISC-V: Enable basic auto-vectorization for RVV RISC-V: Basic enable RVV auto-vectorizaiton - - --- 2023-04-19 juzhe.zhong@rivai.ai JeffreyALaw Dropped
[3/3,V2] RISC-V: Add sanity testcases for RVV auto-vectorization RISC-V: Basic enable RVV auto-vectorizaiton - - --- 2023-04-19 juzhe.zhong@rivai.ai JeffreyALaw Dropped
[committed,v2] RISC-V: Handle multi-lib path correclty for linux [DRAFT] [committed,v2] RISC-V: Handle multi-lib path correclty for linux [DRAFT] - - --- 2023-04-21 Kito Cheng Dropped
RISC-V: ICE for vlmul_ext_v intrinsic API RISC-V: ICE for vlmul_ext_v intrinsic API - - --- 2023-04-26 Li, Pan2 via Gcc-patches Dropped
Docs: Add vector register constarint for asm operands Docs: Add vector register constarint for asm operands - - --- 2023-04-27 Kito Cheng Dropped
RISC-V: Handle multi-lib path correclty for linux RISC-V: Handle multi-lib path correclty for linux - - --- 2023-05-04 Kito Cheng Dropped
RISC-V: Fix PR109615 RISC-V: Fix PR109615 - - --- 2023-05-05 juzhe.zhong@rivai.ai Dropped
[V5] RISC-V: Enable basic RVV auto-vectorization support. [V5] RISC-V: Enable basic RVV auto-vectorization support. - - --- 2023-05-05 juzhe.zhong@rivai.ai Dropped
ISC-V: Enable basic RVV auto-vectorization support. ISC-V: Enable basic RVV auto-vectorization support. - - --- 2023-05-06 juzhe.zhong@rivai.ai Dropped
RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT - - --- 2023-05-09 juzhe.zhong@rivai.ai Dropped
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -… RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -… - - --- 2023-05-10 Li Xu Dropped
[V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init [V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init - - --- 2023-05-13 juzhe.zhong@rivai.ai kitoc Dropped
RISC-V: Add missing torture-init and torture-finish for rvv.exp RISC-V: Add missing torture-init and torture-finish for rvv.exp - - --- 2023-05-22 Kito Cheng Dropped
RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation. RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation. - - --- 2023-05-23 Jin Ma kitoc Dropped
RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM - - --- 2023-05-25 juzhe.zhong@rivai.ai Dropped
RISC-V: Basic VLS code gen for RISC-V RISC-V: Basic VLS code gen for RISC-V - - --- 2023-05-30 Kito Cheng Dropped
[2/3] RISC-V: Add missing torture-init and torture-finish for rvv.exp Unbork testsuite for multlib setups - - --- 2023-05-31 Vineet Gupta Dropped
[2/4,RISC-V] support cm.popretz in zcmp support zcmp extention - - --- 2023-06-07 Fei Gao kitoc Dropped
[4/4,RISC-V] support cm.mva01s cm.mvsa01 in zcmp support zcmp extention - - 2-- 2023-06-07 Fei Gao kitoc Dropped
[v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. [v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. - - 2-- 2023-06-08 Li, Pan2 via Gcc-patches Dropped
[v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. [v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. - - 1-2 2023-06-09 Li, Pan2 via Gcc-patches Dropped
[v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. [v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. - - 4-- 2023-06-15 Robin Dapp Dropped
RISC-V: Add VLS modes for GNU vectors RISC-V: Add VLS modes for GNU vectors - - 4-- 2023-06-18 juzhe.zhong@rivai.ai JeffreyALaw Dropped
RISC-V: Add an experimental vector calling convention RISC-V: Add an experimental vector calling convention - - 4-- 2023-06-25 Lehua Ding kitoc Dropped
[1/3] testsuite: Add check for vectors of 128 bits being supported testsuite: Exclude vector tests for unsupported targets - - 3-- 2023-07-06 Maciej W. Rozycki Dropped
RISC-V: Enable COND_LEN_FMA auto-vectorization RISC-V: Enable COND_LEN_FMA auto-vectorization - - 4-- 2023-07-13 juzhe.zhong@rivai.ai Dropped
RISC-V: Enable basic VLS modes support RISC-V: Enable basic VLS modes support - - 4-- 2023-07-25 juzhe.zhong@rivai.ai Dropped
RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn - - 4-- 2023-07-26 Jivan Hakobyan Dropped
[V2] RISC-V: Enable basic VLS modes support [V2] RISC-V: Enable basic VLS modes support - - 13- 2023-07-27 juzhe.zhong@rivai.ai Dropped
[V3] RISC-V: Enable basic VLS modes support [V3] RISC-V: Enable basic VLS modes support - - 13- 2023-07-27 juzhe.zhong@rivai.ai Dropped
[RFC,1/2] RISC-V: Make __builtin_riscv_pause 'Zihintpause' only RISC-V: Make __builtin_riscv_pause 'Zihintpause' only - - 4-- 2023-08-10 Tsukasa OI JeffreyALaw Dropped
[RFC,2/2] RISC-V: Fix documentation of __builtin_riscv_pause RISC-V: Make __builtin_riscv_pause 'Zihintpause' only - - 4-- 2023-08-10 Tsukasa OI JeffreyALaw Dropped
RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037] RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037] - - -4- 2023-08-21 juzhe.zhong@rivai.ai Dropped
[RFC] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support [RFC] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support - - 4-- 2023-08-30 Tsukasa OI Dropped
[6/8] vect: Add vector_mode paramater to simd_clone_usable [1/8] parloops: Copy target and optimizations when creating a function clone - - --4 2023-08-30 Andre Vieira (lists) Dropped
[PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM [1/8] parloops: Copy target and optimizations when creating a function clone - - 4-- 2023-08-30 Andre Vieira (lists) Dropped
[V4,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - --4 2023-08-31 Lehua Ding Dropped
[V4,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - --4 2023-08-31 Lehua Ding Dropped
[V4,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - 1-3 2023-08-31 Lehua Ding Dropped
libstdc++: Use GLIBCXX_CHECK_LINKER_FEATURES for cross-builds (PR111238) libstdc++: Use GLIBCXX_CHECK_LINKER_FEATURES for cross-builds (PR111238) - - --4 2023-08-31 Christophe Lyon Dropped
RISC-V: Replace rtx REG for zero REGS operations RISC-V: Replace rtx REG for zero REGS operations - - 2-- 2023-09-07 juzhe.zhong@rivai.ai Dropped
[v2,4/4] RISC-V: Implement target attribute RISC-V target attribute - - 4-- 2023-10-10 Kito Cheng JeffreyALaw Dropped
RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935] - - 1-5 2023-10-24 Li Xu Dropped
[PING,1/3] arm: vld1q_types_x2 ACLE intrinsics [PING,1/3] arm: vld1q_types_x2 ACLE intrinsics - - --- 2023-10-24 Ezra Sitorus rearnsha Dropped
RISC-V: VECT: Remember to assert any_known_not_updated_vssa RISC-V: VECT: Remember to assert any_known_not_updated_vssa - - 6-- 2023-11-06 Maxim Blinov JeffreyALaw Dropped
[v2] RISC-V: Fixbug for that XTheadMemPair causes interrupt to fail. [v2] RISC-V: Fixbug for that XTheadMemPair causes interrupt to fail. - - 63- 2023-11-10 Jin Ma Dropped
[RFC] RISC-V: Remove f{r,s}flags builtins [RFC] RISC-V: Remove f{r,s}flags builtins - - 11-1 2023-11-29 Christoph Müllner Dropped
testsuite: add missing dg-require ifunc in pr105554.c testsuite: add missing dg-require ifunc in pr105554.c - - 3-- 2023-12-07 Marc Poulhiès Dropped
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