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ktkachov
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JeffreyALaw
JeffreyALaw
kitoc
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Apply
Patch
Series
rb/tb
S/W/F
Date
Submitter
Delegate
State
[v1,2/2] RISC-V: Add test cases for __builtin_add_overflow branchless unsigned SAT_ADD
[v1,1/2] Match: Support __builtin_add_overflow for branchless unsigned SAT_ADD
- -
1
-
3
2024-05-19
Li, Pan2
New
RISC-V: Remove dead perm series code and document.
RISC-V: Remove dead perm series code and document.
- -
12
-
-
2024-05-17
Robin Dapp
JeffreyALaw
Accepted
RISC-V: Add vector popcount, clz, ctz.
RISC-V: Add vector popcount, clz, ctz.
- -
-
1
3
2024-05-17
Robin Dapp
JuzheZhong
Accepted
RISC-V: Add vandn combine helper.
RISC-V: Add vandn combine helper.
- -
1
-
3
2024-05-17
Robin Dapp
JuzheZhong
Accepted
RISC-V: Use widening shift for scatter/gather if applicable.
RISC-V: Use widening shift for scatter/gather if applicable.
- -
-
1
3
2024-05-17
Robin Dapp
JuzheZhong
Accepted
RISC-V: Add vwsll combine helpers.
RISC-V: Add vwsll combine helpers.
- -
-
1
3
2024-05-17
Robin Dapp
JuzheZhong
Accepted
RISC-V: Split vwadd.wx and vwsub.wx and add helpers.
RISC-V: Split vwadd.wx and vwsub.wx and add helpers.
- -
-
1
3
2024-05-17
Robin Dapp
JuzheZhong
Accepted
RISC-V: Fix testcases renamed test flag options
RISC-V: Fix testcases renamed test flag options
- -
1
-
3
2024-05-16
Edwin Lu
New
RISC-V: propgue/epilogue expansion code minor changes [NFC]
RISC-V: propgue/epilogue expansion code minor changes [NFC]
- -
7
-
5
2024-05-15
Vineet Gupta
JeffreyALaw
Failed CI
RISC-V: Do not allow v0 as dest when merging [PR115068].
RISC-V: Do not allow v0 as dest when merging [PR115068].
- -
10
1
-
2024-05-13
Robin Dapp
JuzheZhong
Accepted
[v2,2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]
RISC-V improve stack/array access by constant mat tweak
- -
11
-
1
2024-05-13
Vineet Gupta
JeffreyALaw
Failed CI
[4/4] RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight
RISC-V: Enhance unaligned/overlapping codegen
- -
7
1
2
2024-05-08
Christoph Müllner
JeffreyALaw
Accepted
[3/4] RISC-V: tune: Add setting for overlapping mem ops to tuning struct
RISC-V: Enhance unaligned/overlapping codegen
- -
7
1
-
2024-05-08
Christoph Müllner
JeffreyALaw
Accepted
[2/4] RISC-V: Allow unaligned accesses in cpymemsi expansion
RISC-V: Enhance unaligned/overlapping codegen
- -
8
-
-
2024-05-08
Christoph Müllner
Changes Requested
[1/4] RISC-V: Add test cases for cpymem expansion
RISC-V: Enhance unaligned/overlapping codegen
- -
8
-
-
2024-05-08
Christoph Müllner
Accepted
[risc-v] libstdc++: Preserve signbit of nan when converting float to double [PR113578]
[risc-v] libstdc++: Preserve signbit of nan when converting float to double [PR113578]
1 -
4
1
6
2024-05-07
Jonathan Wakely
Changes Requested
[5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
RISC-V: Support vf and vx for autovec comparison of
- -
12
-
-
2024-03-01
Demin Han
rdapp
Under Review
[4/5] RISC-V: Remove integer vector eqne pattern
RISC-V: Support vf and vx for autovec comparison of
- -
12
-
-
2024-03-01
Demin Han
rdapp
Under Review
[3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
RISC-V: Support vf and vx for autovec comparison of
- -
11
-
-
2024-03-01
Demin Han
rdapp
Under Review
[1/5] RISC-V: Remove float vector eqne pattern
RISC-V: Support vf and vx for autovec comparison of
- -
10
-
-
2024-03-01
Demin Han
rdapp
Under Review
RISC-V: Adjust vec unit-stride load/store costs.
RISC-V: Adjust vec unit-stride load/store costs.
- -
9
1
2
2024-02-13
Robin Dapp
JeffreyALaw
Under Review
[v3,1/1] RISC-V: Add support for XCVmem extension in CV32E40P
RISC-V: Support CORE-V XCVMEM extension
- -
8
1
2
2024-01-25
Mary Bennett
New
[v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
[v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
- -
11
-
1
2024-01-02
Li, Pan2
JeffreyALaw
New
RISC-V: Support -m[no-]unaligned-access
RISC-V: Support -m[no-]unaligned-access
- -
-
1
3
2023-12-22
Wang Pengcheng
palmer
Under Review
RISC-V: Add --with-cmodel configure-time argument
RISC-V: Add --with-cmodel configure-time argument
- -
4
1
6
2023-12-20
Palmer Dabbelt
New
[v2,3/3] RISC-V: cmpmem for RISCV with V extension
RISC-V: vectorised memory operations
- -
9
-
1
2023-12-19
Sergei Lewis
JeffreyALaw
Under Review
[v2,2/3] RISC-V: setmem for RISCV with V extension
RISC-V: vectorised memory operations
- -
7
1
-
2023-12-19
Sergei Lewis
JeffreyALaw
Under Review
[v2,1/3] RISC-V: movmem for RISCV with V extension
RISC-V: vectorised memory operations
- -
6
1
1
2023-12-19
Sergei Lewis
JeffreyALaw
Under Review
[5/5,ifcvt] optimize extension for x=c ? (y op z) : y by RISC-V Zicond like insns
[1/5,V3,ifcvt] optimize x=c ? (y op z) : y by RISC-V Zicond like insns
- -
9
1
1
2023-12-05
Fei Gao
JeffreyALaw
New
[4/5,ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like insns
[1/5,V3,ifcvt] optimize x=c ? (y op z) : y by RISC-V Zicond like insns
- -
11
-
-
2023-12-05
Fei Gao
JeffreyALaw
New
[7/7] RISC-V: Add intrinsic functions for crypto vector Zvksh extension
Untitled series #27838
- -
-
1
1
2023-12-04
Feng Wang
kitoc
New
[6/7] RISC-V: Add intrinsic functions for crypto vector Zvksed extension.
Untitled series #27838
- -
-
1
1
2023-12-04
Feng Wang
kitoc
New
[5/7] RISC-V: Add intrinsic functions for crypto vector Zvknh[ab] extension
Untitled series #27838
- -
-
1
1
2023-12-04
Feng Wang
kitoc
New
[4/7] RISC-V: Add intrinsic functions for crypto vector Zvkned extension
Untitled series #27838
- -
-
1
1
2023-12-04
Feng Wang
kitoc
New
[3/7] RISC-V: Add intrinsic functions for crypto vector Zvkg extension
Untitled series #27838
- -
-
1
1
2023-12-04
Feng Wang
kitoc
New
[2/7] RISC-V: Add intrinsic functions for crypto vector Zvbc extension
Untitled series #27838
- -
-
1
1
2023-12-04
Feng Wang
kitoc
New
RFA: RISC-V: Add support for XCVhwlp extension in CV32E40P
RFA: RISC-V: Add support for XCVhwlp extension in CV32E40P
- -
8
1
-
2023-11-18
Joern Rennecke
New
RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice
RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice
- -
8
1
-
2023-11-17
钟居哲
rdapp
Under Review
[Commit,QUEUE,V3] RISC-V: Support strided load/store
[Commit,QUEUE,V3] RISC-V: Support strided load/store
- -
9
-
-
2023-11-14
钟居哲
New
[4/4] RISC-V: Fix ICE by expansion and register coercion
RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in)
- -
6
-
-
2023-10-23
Tsukasa OI
JeffreyALaw
New
[3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets
RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in)
- -
6
-
-
2023-10-23
Tsukasa OI
JeffreyALaw
New
[2/2] RISC-V: Implement locality for __builtin_prefetch
[1/2] RISC-V: Recognized zihintntl extensions
- -
4
-
-
2023-07-13
Monk Chiang
New
[v1] RISC-V: Refine the insn pattern of fsrm
[v1] RISC-V: Refine the insn pattern of fsrm
- -
-
4
-
2023-07-04
Li, Pan2 via Gcc-patches
New
RISC-V: Synthesize power-of-two constants.
RISC-V: Synthesize power-of-two constants.
- -
-
-
-
2023-05-30
Robin Dapp
New