Message ID | 33371799-7353-cd99-3f78-9abe31ad24ec@e124511.cambridge.arm.com |
---|---|
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8298A385840D for <patchwork@sourceware.org>; Tue, 9 Apr 2024 13:25:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2053.outbound.protection.outlook.com [40.107.21.53]) by sourceware.org (Postfix) with ESMTPS id DDCAC385840D for <gcc-patches@gcc.gnu.org>; Tue, 9 Apr 2024 13:24:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DDCAC385840D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DDCAC385840D Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.21.53 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1712669071; cv=pass; b=Jfvanw4WkJjYIrP/LNkP+VCGnkgoW+FUPff5APgxGKJgfMK5Up7Wq+a9ZHaPort1WFW5ohNmobTkmuB4iJc57IJul3H9j7qU10nht543keSVI6UHEQLsY2jR3YfxYBZsfofVG1NIHMTLzcPKCdEu6QDsf7ZqnCz401dEAqcJ4U8= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1712669071; c=relaxed/simple; bh=uSLGnmP91TgEMHU5wacIS9vcr8mewTcMWFmGHxENck0=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=sdqn6l00EJ2JWyO1uLMFBtpdbb8g2Wzy+SlHD0hLibIetlZqiF5mnlA8/kotNUp6TUeQ/9KB5E01zusGaFVejFp6mAQKJNaX/hCJFiC+lDhSz0yrz+TaI9r97uwxJBH+wKGlmMouDVQCudHmmoHSyCGzwMM1OPbYS8GH9/mX8Fw= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=ELDfSFJIlm1qytW64AltW2+AKV0MSlz2oKGOz7hHhK4wn9RqiuQamO7jFZCGxxQZ1fS9aQdTuNxxdziCVT5vc5xFyLp44xF3KyF6AiSXG6ggzxkDy+kPpSu9qmSAfi96cYl59DIeEPMDv6DNmWPYy5aT8AbwxUP30rOAkH5ZB5k4eM23fG0jGuQaWsux0J/SUpZkF+9VU81xQkwNptuAzPxujD4oNCznpyQ82s7HAiE0x5VBZBdMnTKSim5h/3wljFMGmUQ1OiU1v9ink/hBzV00HWCMui8kwsh+Hgk3X/p2K7ziDScWWP7GS4q8IPeQQtBsELtgUxeBHBobrc9ctg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tYIa4Vek4VSKXEMJN5260vFkV89UAj6Toro4cPnJ5N0=; b=Y34o9vpONVqE7DKT8bujVx7l7weYyLfIhVJIIaLoURcyG9JRfQ+xFv0fD63nW2ispnP8q/PiYGfSdDvC7UMR1UA9vJU+8h2BeRbWvjHzblMbEQ1oRLPHJ+r3dPlFbBStOYIo5BIrfecqUcCzYV4S00fpYXAb+5I263Sv6/OjcnCQiLpXVKii/WLPhOc9S2c+u0xjLyOcVipA8kGjZJq0QRdDrBsxTJE1hVsS5+JzHy5vb4yuzjYztlqElZ+7XBvGKQjn8ndaplTWNAbtJgDkpo8HTRTSxNFpvZ0Xjn2bJ1a/Nq8xBhGTcgbz88aY/BNSSAEl+/m9NQPgkGcwPPXt9A== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tYIa4Vek4VSKXEMJN5260vFkV89UAj6Toro4cPnJ5N0=; b=ojmBvDD/oq8Q54sgZy7l+SV3Ke1Q81/8kpPWuMEfQ+bde6pKP4z+N34rl8v96AwT6G4D1kavxdlpWuJAJmZHi4ty5OFQ25N9yrDF+8bpzPMhPNgHE0NS8HtnDbgs9Sa47W7YisQKm9EN5VGPIwgHDabcdB7RV+LHPytpWb8qA9A= Received: from AM0PR01CA0076.eurprd01.prod.exchangelabs.com (2603:10a6:208:10e::17) by DU0PR08MB8206.eurprd08.prod.outlook.com (2603:10a6:10:3b3::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.46; Tue, 9 Apr 2024 13:24:26 +0000 Received: from AM3PEPF0000A790.eurprd04.prod.outlook.com (2603:10a6:208:10e:cafe::58) by AM0PR01CA0076.outlook.office365.com (2603:10a6:208:10e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.28 via Frontend Transport; Tue, 9 Apr 2024 13:24:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM3PEPF0000A790.mail.protection.outlook.com (10.167.16.119) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.7452.22 via Frontend Transport; Tue, 9 Apr 2024 13:24:25 +0000 Received: ("Tessian outbound 9d16f63426bd:v300"); Tue, 09 Apr 2024 13:24:25 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 60e454dea010645e X-CR-MTA-TID: 64aa7808 Received: from 9a417215f2d4.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 36A89C7B-6A01-45FA-AF0D-5E50C7764907.1; Tue, 09 Apr 2024 13:24:19 +0000 Received: from EUR01-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 9a417215f2d4.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 09 Apr 2024 13:24:19 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OkbpdcqzpXxiJYFnqY2I7U5B2hlNz/UbHHiniEfggfLFF8HV+WPPDwoq++Z4VGJFZT/8sxDnmvqbRQToOeZZ0W4OX06JCGSzHc2svM0FL1b3aLFi/vRm6KuHpmC1gSPlpmak3yIiXq/NQBba+Qbcy1Qbz6JWcJ4CInYGRGhqsyUFi6fwW/LJhHHsO/tyhASMqtzDcdph6OihIHau0RPWBKDKDhP7r9fly4YM0mtlsLorLI28rQluKNqv9eET56h9pU/v3KxZzW2NCRd7ojjw6oJna4Q0vlXp+5BuxEApB7ENvzXk3i8p+iXuvyyxmGoAf1ftXEeZOFRPwVEbfScQpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tYIa4Vek4VSKXEMJN5260vFkV89UAj6Toro4cPnJ5N0=; b=gT8BGXaiNweup4DW4Ihc2/5a3wv0sjLtYLdm9jxsPD2fxNsxBJUR3s9sxUjCXmsXUqpwpV5AYux1YtaY4mQ8bp7JRcqr8xKUX2HOlD5kDx3J509Dz/+dlcxE2e3nEIy7kTprOgdx+tkwbI4tEtJW+y4ZwcbGFaKveN317/U5Z23PG2ItbVsN1h7U8LSgj6tqWyQ+ixKDv5J7VTHEioFQd7eBR35w4Ysx+t7C+KC0gWO5u0jjn8zzZnDpyrUVr3s2wYAsueUUSXjSKvzFi8GlHwNCdBQHOWZhXp6BwBGjCY7BQpQIzllaoqzRAFxVgCd1wN/0MgQP/fhet/2oRF8nqA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tYIa4Vek4VSKXEMJN5260vFkV89UAj6Toro4cPnJ5N0=; b=ojmBvDD/oq8Q54sgZy7l+SV3Ke1Q81/8kpPWuMEfQ+bde6pKP4z+N34rl8v96AwT6G4D1kavxdlpWuJAJmZHi4ty5OFQ25N9yrDF+8bpzPMhPNgHE0NS8HtnDbgs9Sa47W7YisQKm9EN5VGPIwgHDabcdB7RV+LHPytpWb8qA9A= Received: from AS8PR08MB6678.eurprd08.prod.outlook.com (2603:10a6:20b:398::8) by AS2PR08MB8502.eurprd08.prod.outlook.com (2603:10a6:20b:55d::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.46; Tue, 9 Apr 2024 13:24:17 +0000 Received: from AS8PR08MB6678.eurprd08.prod.outlook.com ([fe80::791b:686b:e7b9:be90]) by AS8PR08MB6678.eurprd08.prod.outlook.com ([fe80::791b:686b:e7b9:be90%5]) with mapi id 15.20.7409.042; Tue, 9 Apr 2024 13:24:17 +0000 Date: Tue, 9 Apr 2024 14:24:13 +0100 From: Andrew Carlotti <andrew.carlotti@arm.com> To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford <richard.sandiford@arm.com>, Richard Earnshaw <richard.earnshaw@arm.com> Subject: [PATCH 0/5] aarch64: FMV feature list fixes Message-ID: <33371799-7353-cd99-3f78-9abe31ad24ec@e124511.cambridge.arm.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-ClientProxiedBy: LO4P123CA0032.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:151::19) To AS8PR08MB6678.eurprd08.prod.outlook.com (2603:10a6:20b:398::8) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: AS8PR08MB6678:EE_|AS2PR08MB8502:EE_|AM3PEPF0000A790:EE_|DU0PR08MB8206:EE_ x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: EAfCHs9dSQxV15+dax1FPEOkOpjsciteK1VS3TPSKPp8i99294plRppCd1UlrySnZ4flj8+ZDre7Z4LZInd94wE+WjblXZMtTwwX2sFTtN+sl/7HCqmWKnORKBoednHPLBJI+PbzU8HhLqlSSb0Jt15Z3hkJ0EOgBgycJc/b46Xu6g0kWvY1rRad7gNxcgP0EKT3V/NtVRultxyZXeSS3gM64E4R+dBetsQgfHIi0EGmAid5HKEDiZCTQ6w6kBTddHmlO/IALIVwPSySlIHU2WP5DEPQUWFahX7xgCCVq9UMm7sBb7nC/0CseB48VYx+NWEJ69hbWSCqMGqCFF/zNAi78+yIjbTvg3sAnXKMMGLfCaxVHhnG0QT3a2E5y4dl5ED930xaqa7GdyHE6P7RMu2hM2OsMjTkRrTGhyHPrdSnVIxvJrkoismWA5t+UT/ObI3K50EYEM+YnBkJqPNzRq3Ee9F0fWTc0lCZjzx9eTeaTb2P+uuS5uNu1uX7AJDuc/1ePcj5fH+KPsES5zQOOfpmXWLX7tvcDHBIBZ+rdQhH5vGlJJMsuzJXYTeugppzdoIUZZeRmzFpSLpLSv1QVJ2rbiPcdWhUsaUeR18cenMZHOz+J3DB+eOj5QcJwzHF0egtsS40FH8RWH7d/tMgsOH3mvSN4o2eojifAjM/o+8= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AS8PR08MB6678.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(376005)(1800799015)(366007); DIR:OUT; SFP:1102; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8502 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM3PEPF0000A790.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 561fc048-c885-469b-7a7b-08dc58986097 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5k0L9fcsXGHc0WH1CjSFnfkTXAnDf2Xk/2tkauecWOmsoIz7aRgpL/Ec12SKskZTjveIJEAsxn+5H0KdUAVQykewFunZ4y4o9iI9IGBc1qEjXcAZrFXmXbkQaAm15DLfGmB/hukl0S9d8/mCPqON0DRlnAD+TBOuHBo1O+egyKInFmaQleuLAOjd6/VcCLz3pDvy/Uf36/UTTkXSFi6nz5pYTAvjf9CD7KpCerxuhNEEZxhtVKiuNMb7ibVJAen27nwVYkEE6h7KSevjVOzdhTc1J0ioT99GAUnTq254P8om51jjdUsF7eRVPumTT62rZp1yy2U2u1x5p8ltJIVlm++wZybCGvDIBc6puRGwSRi2QeL3w6xt2tCAGzgRGAyxmzdTX44tzAQG+MMMi2JJG/tCSUeen3SMhuPcok3gN98IyheSoBj6AYaTDq/Wzlh0laFcKeMTHXIYH9llArmPhx3O2x2pL9e3XzlHwdjDNXAGIadexkr9S7OzGJ2jmchq6OTketcfLb+1O+Rr4uJJrco8HR/aK2Or7f4lvy580TdWHyXRb98iynuUB4X7W76riqvV8ZtUSDngC5+HutZD7lOy6XixT5/WEfTDbf4o1e8T8ZftTZzrmZNIlqnaLKMhQuBrf3H4RHqhO7VctuJn9JR8U2ZeHo4RNy+taIT6vDTlvWvoqQ6US4aaTlUXFHKNSiWJOjq0yg0mdKjzqg/U4ko2O1RI2rzuqShHTAtS8JuzqkYClTFxhXnxgNygstIT X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2024 13:24:25.8112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 561fc048-c885-469b-7a7b-08dc58986097 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A790.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8206 X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, KAM_DMARC_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org |
Series | aarch64: FMV feature list fixes | |
Message
Andrew Carlotti
April 9, 2024, 1:24 p.m. UTC
The first three patches are trivial changes to the feature list to reflect recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning features that don't work at the moment, and should be entirely uncontroversial. Patch 5 handles the remaining cases, where there's an inconsistency in how features are named in the current FMV specification compared to the existing command line options. It might be better to instead preserve the "memtag2", "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either version. Bootstrapped and regression tested on aarch64. Ok for master?
Comments
Andrew Carlotti <andrew.carlotti@arm.com> writes: > The first three patches are trivial changes to the feature list to reflect > recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning > features that don't work at the moment, and should be entirely uncontroversial. > > Patch 5 handles the remaining cases, where there's an inconsistency in how > features are named in the current FMV specification compared to the existing > command line options. It might be better to instead preserve the "memtag2", > "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either > version. Yeah, I suppose patch 5 leaves things in a somewhat awkward state, since e.g.: -AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "") +AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") -AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG)) +AARCH64_FMV_FEATURE("memtag", MEMTAG2, (MEMTAG)) seems to drop "memtag2" and FEAT_MEMTAG, but keep "memtag" and FEAT_MEMTAG2. Is that right? Apart from that and the comment on patch 2, the series looks good to me. While rechecking aarch64-option-extensions.def against the ACLE list: it seems that the .def doesn't treat mops as an FMV feature. Is that deliberate? Thanks, Richard
On Tue, Apr 09, 2024 at 04:43:16PM +0100, Richard Sandiford wrote: > Andrew Carlotti <andrew.carlotti@arm.com> writes: > > The first three patches are trivial changes to the feature list to reflect > > recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning > > features that don't work at the moment, and should be entirely uncontroversial. > > > > Patch 5 handles the remaining cases, where there's an inconsistency in how > > features are named in the current FMV specification compared to the existing > > command line options. It might be better to instead preserve the "memtag2", > > "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either > > version. > > Yeah, I suppose patch 5 leaves things in a somewhat awkward state, > since e.g.: > > -AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "") > +AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") > > -AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG)) > +AARCH64_FMV_FEATURE("memtag", MEMTAG2, (MEMTAG)) > > seems to drop "memtag2" and FEAT_MEMTAG, but keep "memtag" and > FEAT_MEMTAG2. Is that right? That's deliberate. The FEAT_MEMTAG bit in __aarch64_cpu_features is defined to match the definition of FEAT_MTE in the architecture, and likewise for FEAT_MEMTAG2/FEAT_MTE2. However, in Binutils the "+memtag" extension enables both FEAT_MTE and FEAT_MTE2 instructions (although none of the FEAT_MTE2 instructions can be generated from GCC without inline assembly). The FMV specification in the ACLE currently uses names "memtag" and "memtag2" that match the architecture names, but arguably don't match the command line extension names. I'm advocating for that to change to match the extension names in command line options. The LS64 example is definitely an inconsistency, since GCC uses "+ls64" to enable intrinsics for all of the FEAT_LS64/FEAT_LS64_V/FEAT_LS64_ACCDATA intrinsics. There were similar issues with "sha1", "pmull" and "sve2-pmull128", but in these cases their presence architecturally is implied by the presence of the features checked for "sha2", "aes" and "sve2-aes" so it's fine to just delete the ones without command line flags. > Apart from that and the comment on patch 2, the series looks good to me. > > While rechecking aarch64-option-extensions.def against the ACLE list: > it seems that the .def doesn't treat mops as an FMV feature. Is that > deliberate? "mops" was added to the ACLE list later, and libgcc doesn't yet support detecting it. I didn't think it was sensible to add new FMV feature support at this stage. > Thanks, > Richard
Andrew Carlotti <andrew.carlotti@arm.com> writes: > On Tue, Apr 09, 2024 at 04:43:16PM +0100, Richard Sandiford wrote: >> Andrew Carlotti <andrew.carlotti@arm.com> writes: >> > The first three patches are trivial changes to the feature list to reflect >> > recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning >> > features that don't work at the moment, and should be entirely uncontroversial. >> > >> > Patch 5 handles the remaining cases, where there's an inconsistency in how >> > features are named in the current FMV specification compared to the existing >> > command line options. It might be better to instead preserve the "memtag2", >> > "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either >> > version. >> >> Yeah, I suppose patch 5 leaves things in a somewhat awkward state, >> since e.g.: >> >> -AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "") >> +AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") >> >> -AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG)) >> +AARCH64_FMV_FEATURE("memtag", MEMTAG2, (MEMTAG)) >> >> seems to drop "memtag2" and FEAT_MEMTAG, but keep "memtag" and >> FEAT_MEMTAG2. Is that right? > > That's deliberate. The FEAT_MEMTAG bit in __aarch64_cpu_features is defined to > match the definition of FEAT_MTE in the architecture, and likewise for > FEAT_MEMTAG2/FEAT_MTE2. However, in Binutils the "+memtag" extension enables > both FEAT_MTE and FEAT_MTE2 instructions (although none of the FEAT_MTE2 > instructions can be generated from GCC without inline assembly). The FMV > specification in the ACLE currently uses names "memtag" and "memtag2" that > match the architecture names, but arguably don't match the command line > extension names. I'm advocating for that to change to match the extension > names in command line options. Hmm, ok. I agree it makes sense for the user-visible FMV namnes to match the command line. But shouldn't __aarch64_cpu_features either (a) use exactly the same names as the architecture or (b) use exactly the same names as the command-line (mangled where necessary)? It seems that we're instead using a third convention that doesn't exactly match the other two. That is, I can see the rationale for "memtag" => FEAT_MTE2 and "memtag" => FEAT_MEMTAG. It just seems odd to have "memtag" => FEAT_MEMTAG2 (where MEMTAG2 is an alias of MTE2). How much leeway do we have to change the __aarch64_cpu_features names? Is it supposed to be a public API (as opposed to ABI)? > The LS64 example is definitely an inconsistency, since GCC uses "+ls64" to > enable intrinsics for all of the FEAT_LS64/FEAT_LS64_V/FEAT_LS64_ACCDATA > intrinsics. Ok, thanks. If we go for option (a) above then I agree that the ls64 change is correct. If we go for option (b) then I suppose it should stay as LS64. > There were similar issues with "sha1", "pmull" and "sve2-pmull128", but in > these cases their presence architecturally is implied by the presence of the > features checked for "sha2", "aes" and "sve2-aes" so it's fine to just delete > the ones without command line flags. > >> Apart from that and the comment on patch 2, the series looks good to me. >> >> While rechecking aarch64-option-extensions.def against the ACLE list: >> it seems that the .def doesn't treat mops as an FMV feature. Is that >> deliberate? > > "mops" was added to the ACLE list later, and libgcc doesn't yet support > detecting it. I didn't think it was sensible to add new FMV feature support at > this stage. Ah, ok, makes sense. Richard
On Wed, Apr 10, 2024 at 05:42:05PM +0100, Richard Sandiford wrote: > Andrew Carlotti <andrew.carlotti@arm.com> writes: > > On Tue, Apr 09, 2024 at 04:43:16PM +0100, Richard Sandiford wrote: > >> Andrew Carlotti <andrew.carlotti@arm.com> writes: > >> > The first three patches are trivial changes to the feature list to reflect > >> > recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning > >> > features that don't work at the moment, and should be entirely uncontroversial. > >> > > >> > Patch 5 handles the remaining cases, where there's an inconsistency in how > >> > features are named in the current FMV specification compared to the existing > >> > command line options. It might be better to instead preserve the "memtag2", > >> > "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either > >> > version. > >> > >> Yeah, I suppose patch 5 leaves things in a somewhat awkward state, > >> since e.g.: > >> > >> -AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "") > >> +AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") > >> > >> -AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG)) > >> +AARCH64_FMV_FEATURE("memtag", MEMTAG2, (MEMTAG)) > >> > >> seems to drop "memtag2" and FEAT_MEMTAG, but keep "memtag" and > >> FEAT_MEMTAG2. Is that right? > > > > That's deliberate. The FEAT_MEMTAG bit in __aarch64_cpu_features is defined to > > match the definition of FEAT_MTE in the architecture, and likewise for > > FEAT_MEMTAG2/FEAT_MTE2. However, in Binutils the "+memtag" extension enables > > both FEAT_MTE and FEAT_MTE2 instructions (although none of the FEAT_MTE2 > > instructions can be generated from GCC without inline assembly). The FMV > > specification in the ACLE currently uses names "memtag" and "memtag2" that > > match the architecture names, but arguably don't match the command line > > extension names. I'm advocating for that to change to match the extension > > names in command line options. > > Hmm, ok. I agree it makes sense for the user-visible FMV namnes to match > the command line. But shouldn't __aarch64_cpu_features either (a) use exactly > the same names as the architecture or (b) use exactly the same names as the > command-line (mangled where necessary)? It seems that we're instead > using a third convention that doesn't exactly match the other two. I agree that the name isn't one I would choose now, but I don't think it matters much that it's inconsistent. > That is, I can see the rationale for "memtag" => FEAT_MTE2 and > "memtag" => FEAT_MEMTAG. It just seems odd to have "memtag" => FEAT_MEMTAG2 > (where MEMTAG2 is an alias of MTE2). > > How much leeway do we have to change the __aarch64_cpu_features names? > Is it supposed to be a public API (as opposed to ABI)? I think we're designing it to be capable of being a public API, but we haven't yet made it one. That's partly why I've kept the enum value names the same as in LLVM so far. > > The LS64 example is definitely an inconsistency, since GCC uses "+ls64" to > > enable intrinsics for all of the FEAT_LS64/FEAT_LS64_V/FEAT_LS64_ACCDATA > > intrinsics. > > Ok, thanks. If we go for option (a) above then I agree that the ls64 > change is correct. If we go for option (b) then I suppose it should > stay as LS64. > > > There were similar issues with "sha1", "pmull" and "sve2-pmull128", but in > > these cases their presence architecturally is implied by the presence of the > > features checked for "sha2", "aes" and "sve2-aes" so it's fine to just delete > > the ones without command line flags. > > > >> Apart from that and the comment on patch 2, the series looks good to me. > >> > >> While rechecking aarch64-option-extensions.def against the ACLE list: > >> it seems that the .def doesn't treat mops as an FMV feature. Is that > >> deliberate? > > > > "mops" was added to the ACLE list later, and libgcc doesn't yet support > > detecting it. I didn't think it was sensible to add new FMV feature support at > > this stage. > > Ah, ok, makes sense. > > Richard
Andrew Carlotti <andrew.carlotti@arm.com> writes: > On Wed, Apr 10, 2024 at 05:42:05PM +0100, Richard Sandiford wrote: >> Andrew Carlotti <andrew.carlotti@arm.com> writes: >> > On Tue, Apr 09, 2024 at 04:43:16PM +0100, Richard Sandiford wrote: >> >> Andrew Carlotti <andrew.carlotti@arm.com> writes: >> >> > The first three patches are trivial changes to the feature list to reflect >> >> > recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning >> >> > features that don't work at the moment, and should be entirely uncontroversial. >> >> > >> >> > Patch 5 handles the remaining cases, where there's an inconsistency in how >> >> > features are named in the current FMV specification compared to the existing >> >> > command line options. It might be better to instead preserve the "memtag2", >> >> > "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either >> >> > version. >> >> >> >> Yeah, I suppose patch 5 leaves things in a somewhat awkward state, >> >> since e.g.: >> >> >> >> -AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "") >> >> +AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") >> >> >> >> -AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG)) >> >> +AARCH64_FMV_FEATURE("memtag", MEMTAG2, (MEMTAG)) >> >> >> >> seems to drop "memtag2" and FEAT_MEMTAG, but keep "memtag" and >> >> FEAT_MEMTAG2. Is that right? >> > >> > That's deliberate. The FEAT_MEMTAG bit in __aarch64_cpu_features is defined to >> > match the definition of FEAT_MTE in the architecture, and likewise for >> > FEAT_MEMTAG2/FEAT_MTE2. However, in Binutils the "+memtag" extension enables >> > both FEAT_MTE and FEAT_MTE2 instructions (although none of the FEAT_MTE2 >> > instructions can be generated from GCC without inline assembly). The FMV >> > specification in the ACLE currently uses names "memtag" and "memtag2" that >> > match the architecture names, but arguably don't match the command line >> > extension names. I'm advocating for that to change to match the extension >> > names in command line options. >> >> Hmm, ok. I agree it makes sense for the user-visible FMV namnes to match >> the command line. But shouldn't __aarch64_cpu_features either (a) use exactly >> the same names as the architecture or (b) use exactly the same names as the >> command-line (mangled where necessary)? It seems that we're instead >> using a third convention that doesn't exactly match the other two. > > I agree that the name isn't one I would choose now, but I don't think it matters much that it's inconsistent. I kind-of think it does though. Given... >> That is, I can see the rationale for "memtag" => FEAT_MTE2 and >> "memtag" => FEAT_MEMTAG. It just seems odd to have "memtag" => FEAT_MEMTAG2 >> (where MEMTAG2 is an alias of MTE2). >> >> How much leeway do we have to change the __aarch64_cpu_features names? >> Is it supposed to be a public API (as opposed to ABI)? > > I think we're designing it to be capable of being a public API, but we haven't > yet made it one. That's partly why I've kept the enum value names the same as > in LLVM so far. ...this, I don't want to sleep-walk into a situation where we have one naming convention for the architecture, one for the attributes, and a third one for the API. If we're not in a position to commit to a consistent naming scheme for the API by GCC 14 then it might be better to remove the FMV features in 5/5 for GCC 14 and revisit in GCC 15. A patch to do that is pre-approved if you agree (but please say if you don't). Thanks, Richard
On Wed, Apr 10, 2024 at 07:51:44PM +0100, Richard Sandiford wrote: > Andrew Carlotti <andrew.carlotti@arm.com> writes: > > On Wed, Apr 10, 2024 at 05:42:05PM +0100, Richard Sandiford wrote: > >> Andrew Carlotti <andrew.carlotti@arm.com> writes: > >> > On Tue, Apr 09, 2024 at 04:43:16PM +0100, Richard Sandiford wrote: > >> >> Andrew Carlotti <andrew.carlotti@arm.com> writes: > >> >> > The first three patches are trivial changes to the feature list to reflect > >> >> > recent changes in the ACLE. Patch 4 removes most of the FMV multiversioning > >> >> > features that don't work at the moment, and should be entirely uncontroversial. > >> >> > > >> >> > Patch 5 handles the remaining cases, where there's an inconsistency in how > >> >> > features are named in the current FMV specification compared to the existing > >> >> > command line options. It might be better to instead preserve the "memtag2", > >> >> > "ssbs2" and "ls64_accdata" names for now; I'd be happy to commit either > >> >> > version. > >> >> > >> >> Yeah, I suppose patch 5 leaves things in a somewhat awkward state, > >> >> since e.g.: > >> >> > >> >> -AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "") > >> >> +AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") > >> >> > >> >> -AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG)) > >> >> +AARCH64_FMV_FEATURE("memtag", MEMTAG2, (MEMTAG)) > >> >> > >> >> seems to drop "memtag2" and FEAT_MEMTAG, but keep "memtag" and > >> >> FEAT_MEMTAG2. Is that right? > >> > > >> > That's deliberate. The FEAT_MEMTAG bit in __aarch64_cpu_features is defined to > >> > match the definition of FEAT_MTE in the architecture, and likewise for > >> > FEAT_MEMTAG2/FEAT_MTE2. However, in Binutils the "+memtag" extension enables > >> > both FEAT_MTE and FEAT_MTE2 instructions (although none of the FEAT_MTE2 > >> > instructions can be generated from GCC without inline assembly). The FMV > >> > specification in the ACLE currently uses names "memtag" and "memtag2" that > >> > match the architecture names, but arguably don't match the command line > >> > extension names. I'm advocating for that to change to match the extension > >> > names in command line options. > >> > >> Hmm, ok. I agree it makes sense for the user-visible FMV namnes to match > >> the command line. But shouldn't __aarch64_cpu_features either (a) use exactly > >> the same names as the architecture or (b) use exactly the same names as the > >> command-line (mangled where necessary)? It seems that we're instead > >> using a third convention that doesn't exactly match the other two. > > > > I agree that the name isn't one I would choose now, but I don't think it matters much that it's inconsistent. > > I kind-of think it does though. Given... > > >> That is, I can see the rationale for "memtag" => FEAT_MTE2 and > >> "memtag" => FEAT_MEMTAG. It just seems odd to have "memtag" => FEAT_MEMTAG2 > >> (where MEMTAG2 is an alias of MTE2). > >> > >> How much leeway do we have to change the __aarch64_cpu_features names? > >> Is it supposed to be a public API (as opposed to ABI)? > > > > I think we're designing it to be capable of being a public API, but we haven't > > yet made it one. That's partly why I've kept the enum value names the same as > > in LLVM so far. > > ...this, I don't want to sleep-walk into a situation where we have > one naming convention for the architecture, one for the attributes, > and a third one for the API. If we're not in a position to commit > to a consistent naming scheme for the API by GCC 14 then it might be > better to remove the FMV features in 5/5 for GCC 14 and revisit in GCC 15. > > A patch to do that is pre-approved if you agree (but please say > if you don't). I'm happy to remove those features for GCC 14 (pending agreement on the attribute names in particular), but I don't think that does anything to solve the enum names issue. I'll remove the names from my FMV documentation patch as well. > Thanks, > Richard