[0/6] aarch64: Port NEON intrinsics to pragma-based framework using IFNs

Message ID	20260902083828.45767-1-dhruvc@nvidia.com
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 504904BA5435 Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: <dhruvc@nvidia.com> To: <gcc-patches@gcc.gnu.org> CC: <karl.meakin@arm.com>, <ktkachov@nvidia.com> Subject: [PATCH 0/6] aarch64: Port NEON intrinsics to pragma-based framework using IFNs Date: Wed, 2 Sep 2026 14:08:22 +0530 Message-ID: <20260902083828.45767-1-dhruvc@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org
Series	aarch64: Port NEON intrinsics to pragma-based framework using IFNs \| [0/6] aarch64: Port NEON intrinsics to pragma-based framework using IFNs [1/6] aarch64: Port NEON saturating add/sub intrinsics to pragma-based framework [2/6] aarch64: Port NEON reduction intrinsics to pragma-based framework [3/6] aarch64: Port NEON halving-add intrinsics to pragma-based framework [4/6] aarch64: Port NEON square-root intrinsics to pragma-based framework [5/6] aarch64: Port NEON rounding intrinsics to the pragma-based framework [6/6] aarch64: Port NEON min/max intrinsics to the pragma-based framework

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Subject: [PATCH 0/6] aarch64: Port NEON intrinsics to pragma-based framework
 using IFNs
Date: Wed, 2 Sep 2026 14:08:22 +0530
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Series

aarch64: Port NEON intrinsics to pragma-based framework using IFNs |

Message

Dhruv Chawla Sept. 2, 2026, 8:38 a.m. UTC

  From: Dhruv Chawla <dhruvc@nvidia.com>

This patch series ports a set of NEON intrinsics that can be directly mapped
to GIMPLE IFNs without any special handling. This includes the
following:
* vqadd (plus scalar versions)
* vqsub (plus scalar versions)
* vmax{,v,nm,nmv}
* vmin{,v,nm,nmv}
* vaddv
* vsqrt
* vhadd
* vrhadd
* vrnd{,a,i,m,n,ns,p,x}

Some of these intrinsics are not ported for one of the following reasons:
- The instruction pattern that the IFN lowers to does not iterate over
  the mode required to match the intrinsic (eg. an intrinsic requiring a
  V1DF pattern but the existing pattern using VHSDF).
- The intrinsic requires special handling (eg. floating point NaN
  semantics).

Details for individual cases are provided in the patches.

Signed-off-by: Dhruv Chawla <dhruvc@nvidia.com>

Dhruv Chawla (6):
  aarch64: Port NEON saturating add/sub intrinsics to pragma-based
    framework
  aarch64: Port NEON reduction intrinsics to pragma-based framework
  aarch64: Port NEON halving-add intrinsics to pragma-based framework
  aarch64: Port NEON square-root intrinsics to pragma-based framework
  aarch64: Port NEON rounding intrinsics to the pragma-based framework
  aarch64: Port NEON min/max intrinsics to the pragma-based framework

 gcc/config/aarch64/aarch64-acle-builtins.h    |   14 +
 .../aarch64/aarch64-neon-builtins-base.cc     |   63 +
 .../aarch64/aarch64-neon-builtins-base.def    |  115 ++
 gcc/config/aarch64/arm_neon.h                 | 1790 ++---------------
 gcc/testsuite/gcc.target/aarch64/neon/vaddv.c |  138 ++
 gcc/testsuite/gcc.target/aarch64/neon/vhadd.c |   88 +
 gcc/testsuite/gcc.target/aarch64/neon/vmax.c  |  130 ++
 .../gcc.target/aarch64/neon/vmaxnm.c          |   46 +
 .../gcc.target/aarch64/neon/vmaxnmv.c         |   39 +
 gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c |  135 ++
 gcc/testsuite/gcc.target/aarch64/neon/vmin.c  |  130 ++
 .../gcc.target/aarch64/neon/vminnm.c          |   46 +
 .../gcc.target/aarch64/neon/vminnmv.c         |   39 +
 gcc/testsuite/gcc.target/aarch64/neon/vminv.c |  135 ++
 gcc/testsuite/gcc.target/aarch64/neon/vqadd.c |  192 ++
 gcc/testsuite/gcc.target/aarch64/neon/vqsub.c |  192 ++
 .../gcc.target/aarch64/neon/vrhadd.c          |   88 +
 gcc/testsuite/gcc.target/aarch64/neon/vrnd.c  |   45 +
 gcc/testsuite/gcc.target/aarch64/neon/vrnda.c |   45 +
 gcc/testsuite/gcc.target/aarch64/neon/vrndi.c |   45 +
 gcc/testsuite/gcc.target/aarch64/neon/vrndm.c |   45 +
 gcc/testsuite/gcc.target/aarch64/neon/vrndn.c |   52 +
 gcc/testsuite/gcc.target/aarch64/neon/vrndp.c |   45 +
 gcc/testsuite/gcc.target/aarch64/neon/vrndx.c |   45 +
 gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c |   46 +
 .../aarch64/simd/faminmax-no-codegen.c        |   40 +-
 .../gcc.target/aarch64/sme/arm_neon_1.c       |    4 +-
 .../gcc.target/aarch64/sme/arm_neon_2.c       |    4 +-
 .../gcc.target/aarch64/sme/arm_neon_3.c       |    4 +-
 .../gcc.target/aarch64/sme/inlining_10.c      |    6 +-
 .../gcc.target/aarch64/sme/inlining_11.c      |    6 +-
 31 files changed, 2183 insertions(+), 1629 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vaddv.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vhadd.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmax.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxnm.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxnmv.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmin.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminnm.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminnmv.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminv.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vqadd.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vqsub.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrhadd.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrnd.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrnda.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndi.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndm.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndn.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndp.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndx.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c

Comments

Karl Meakin Sept. 7, 2026, 2:13 p.m. UTC | #1

On 02/09/2026 09:38, dhruvc@nvidia.com wrote:
> From: Dhruv Chawla <dhruvc@nvidia.com>
>
> This patch series ports a set of NEON intrinsics that can be directly mapped
> to GIMPLE IFNs without any special handling. This includes the
> following:
> * vqadd (plus scalar versions)
> * vqsub (plus scalar versions)
> * vmax{,v,nm,nmv}
> * vmin{,v,nm,nmv}
> * vaddv
> * vsqrt
> * vhadd
> * vrhadd
> * vrnd{,a,i,m,n,ns,p,x}
>
> Some of these intrinsics are not ported for one of the following reasons:
> - The instruction pattern that the IFN lowers to does not iterate over
>    the mode required to match the intrinsic (eg. an intrinsic requiring a
>    V1DF pattern but the existing pattern using VHSDF).
Why not edit the instruction patterns to cover the missing modes?
> - The intrinsic requires special handling (eg. floating point NaN
>    semantics).
>
> Details for individual cases are provided in the patches.
>
> Signed-off-by: Dhruv Chawla <dhruvc@nvidia.com>
>
> Dhruv Chawla (6):
>    aarch64: Port NEON saturating add/sub intrinsics to pragma-based
>      framework
>    aarch64: Port NEON reduction intrinsics to pragma-based framework
>    aarch64: Port NEON halving-add intrinsics to pragma-based framework
>    aarch64: Port NEON square-root intrinsics to pragma-based framework
>    aarch64: Port NEON rounding intrinsics to the pragma-based framework
>    aarch64: Port NEON min/max intrinsics to the pragma-based framework
>
>   gcc/config/aarch64/aarch64-acle-builtins.h    |   14 +
>   .../aarch64/aarch64-neon-builtins-base.cc     |   63 +
>   .../aarch64/aarch64-neon-builtins-base.def    |  115 ++
>   gcc/config/aarch64/arm_neon.h                 | 1790 ++---------------
>   gcc/testsuite/gcc.target/aarch64/neon/vaddv.c |  138 ++
>   gcc/testsuite/gcc.target/aarch64/neon/vhadd.c |   88 +
>   gcc/testsuite/gcc.target/aarch64/neon/vmax.c  |  130 ++
>   .../gcc.target/aarch64/neon/vmaxnm.c          |   46 +
>   .../gcc.target/aarch64/neon/vmaxnmv.c         |   39 +
>   gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c |  135 ++
>   gcc/testsuite/gcc.target/aarch64/neon/vmin.c  |  130 ++
>   .../gcc.target/aarch64/neon/vminnm.c          |   46 +
>   .../gcc.target/aarch64/neon/vminnmv.c         |   39 +
>   gcc/testsuite/gcc.target/aarch64/neon/vminv.c |  135 ++
>   gcc/testsuite/gcc.target/aarch64/neon/vqadd.c |  192 ++
>   gcc/testsuite/gcc.target/aarch64/neon/vqsub.c |  192 ++
>   .../gcc.target/aarch64/neon/vrhadd.c          |   88 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrnd.c  |   45 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrnda.c |   45 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrndi.c |   45 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrndm.c |   45 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrndn.c |   52 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrndp.c |   45 +
>   gcc/testsuite/gcc.target/aarch64/neon/vrndx.c |   45 +
>   gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c |   46 +
>   .../aarch64/simd/faminmax-no-codegen.c        |   40 +-
>   .../gcc.target/aarch64/sme/arm_neon_1.c       |    4 +-
>   .../gcc.target/aarch64/sme/arm_neon_2.c       |    4 +-
>   .../gcc.target/aarch64/sme/arm_neon_3.c       |    4 +-
>   .../gcc.target/aarch64/sme/inlining_10.c      |    6 +-
>   .../gcc.target/aarch64/sme/inlining_11.c      |    6 +-
>   31 files changed, 2183 insertions(+), 1629 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vaddv.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vhadd.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmax.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxnm.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxnmv.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmaxv.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vmin.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminnm.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminnmv.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vminv.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vqadd.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vqsub.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrhadd.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrnd.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrnda.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndi.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndm.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndn.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndp.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vrndx.c
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/neon/vsqrt.c
>