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[v1,0/3] RISC-V: Allow RVV register overlap for vwmaccus.vx

Message ID 20260901233549.3563543-1-pan2.li@intel.com
Headers
Series RISC-V: Allow RVV register overlap for vwmaccus.vx |

Message

Li, Pan2 Sept. 1, 2026, 11:34 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Like v[sz]ext.vf8, we continue the support for vwmaccus.vx

The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.

Pan Li (3):
  RISC-V: Allow RVV register overlap for vwmaccus.vx
  RISC-V: Add test cases for vwmaccus.vx reg overlap
  RISC-V: Add more test cases for vwmaccus.vx

 gcc/config/riscv/vector.md                    | 18 +++---
 .../group_overlap/vwmaccus_vx-i16-m1.c        | 58 +++++++++++++++++
 .../group_overlap/vwmaccus_vx-i16-m2.c        | 50 +++++++++++++++
 .../group_overlap/vwmaccus_vx-i16-m4.c        | 46 ++++++++++++++
 .../group_overlap/vwmaccus_vx-i16-mf2.c       | 21 +++++++
 .../group_overlap/vwmaccus_vx-i16-mf4.c       | 21 +++++++
 .../group_overlap/vwmaccus_vx-i32-m1.c        | 58 +++++++++++++++++
 .../group_overlap/vwmaccus_vx-i32-m2.c        | 50 +++++++++++++++
 .../group_overlap/vwmaccus_vx-i32-m4.c        | 46 ++++++++++++++
 .../group_overlap/vwmaccus_vx-i32-mf2.c       | 21 +++++++
 .../autovec/group_overlap/vwmaccus_vx-i8-m1.c | 58 +++++++++++++++++
 .../autovec/group_overlap/vwmaccus_vx-i8-m2.c | 50 +++++++++++++++
 .../autovec/group_overlap/vwmaccus_vx-i8-m4.c | 46 ++++++++++++++
 .../group_overlap/vwmaccus_vx-i8-mf2.c        | 21 +++++++
 .../group_overlap/vwmaccus_vx-i8-mf4.c        | 21 +++++++
 .../group_overlap/vwmaccus_vx-i8-mf8.c        | 21 +++++++
 .../gcc.target/riscv/rvv/base/pr112431-37.c   |  6 +-
 .../gcc.target/riscv/rvv/base/pr112431-57.c   | 62 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/pr112431-58.c   | 62 +++++++++++++++++++
 19 files changed, 724 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccus_vx-i8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c

Comments

Jeff Law Sept. 2, 2026, 1:29 a.m. UTC | #1 
On 9/1/26 5:34 PM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> Like v[sz]ext.vf8, we continue the support for vwmaccus.vx
>
> The below test suites are passed for this patch:
> 1. The rv64gcv fully regression tests.
>
> Pan Li (3):
>    RISC-V: Allow RVV register overlap for vwmaccus.vx
>    RISC-V: Add test cases for vwmaccus.vx reg overlap
>    RISC-V: Add more test cases for vwmaccus.vx
>
>   gcc/config/riscv/vector.md                    | 18 +++---
>   .../group_overlap/vwmaccus_vx-i16-m1.c        | 58 +++++++++++++++++
>   .../group_overlap/vwmaccus_vx-i16-m2.c        | 50 +++++++++++++++
>   .../group_overlap/vwmaccus_vx-i16-m4.c        | 46 ++++++++++++++
>   .../group_overlap/vwmaccus_vx-i16-mf2.c       | 21 +++++++
>   .../group_overlap/vwmaccus_vx-i16-mf4.c       | 21 +++++++
>   .../group_overlap/vwmaccus_vx-i32-m1.c        | 58 +++++++++++++++++
>   .../group_overlap/vwmaccus_vx-i32-m2.c        | 50 +++++++++++++++
>   .../group_overlap/vwmaccus_vx-i32-m4.c        | 46 ++++++++++++++
>   .../group_overlap/vwmaccus_vx-i32-mf2.c       | 21 +++++++
>   .../autovec/group_overlap/vwmaccus_vx-i8-m1.c | 58 +++++++++++++++++
>   .../autovec/group_overlap/vwmaccus_vx-i8-m2.c | 50 +++++++++++++++
>   .../autovec/group_overlap/vwmaccus_vx-i8-m4.c | 46 ++++++++++++++
>   .../group_overlap/vwmaccus_vx-i8-mf2.c        | 21 +++++++
>   .../group_overlap/vwmaccus_vx-i8-mf4.c        | 21 +++++++
>   .../group_overlap/vwmaccus_vx-i8-mf8.c        | 21 +++++++
>   .../gcc.target/riscv/rvv/base/pr112431-37.c   |  6 +-
>   .../gcc.target/riscv/rvv/base/pr112431-57.c   | 62 +++++++++++++++++++
>   .../gcc.target/riscv/rvv/base/pr112431-58.c   | 62 +++++++++++++++++++
This series is OK.  Thanks!

jeff