mbox series

[v1,0/3] Support RVV register overlap for vwmulsu.vv

Message ID 20260805080146.2333958-1-pan2.li@intel.com
Headers
Series Support RVV register overlap for vwmulsu.vv |

Message

Li, Pan2 Aug. 5, 2026, 8 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Like v[sz]ext.vf8, we continue the support for vwmulsu.vv.

The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.

Pan Li (3):
  RISC-V: Allow RVV register overlap for vwmulsu.vv
  RISC-V: Add test cases for vwmulsu.vv reg overlap
  RISC-V: Add more test cases for vwmulsu.vv

 gcc/config/riscv/vector.md                    |  18 +-
 .../rvv/autovec/group_overlap/group_overlap.h | 158 ++++++++++++++++++
 .../autovec/group_overlap/vwmulsu_vv-i16-m1.c |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i16-m2.c |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i16-m4.c |  19 +++
 .../group_overlap/vwmulsu_vv-i16-mf2.c        |  21 +++
 .../group_overlap/vwmulsu_vv-i16-mf4.c        |  21 +++
 .../autovec/group_overlap/vwmulsu_vv-i32-m1.c |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i32-m2.c |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i32-m4.c |  19 +++
 .../group_overlap/vwmulsu_vv-i32-mf2.c        |  21 +++
 .../autovec/group_overlap/vwmulsu_vv-i8-m1.c  |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i8-m2.c  |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i8-m4.c  |  19 +++
 .../autovec/group_overlap/vwmulsu_vv-i8-mf2.c |  21 +++
 .../autovec/group_overlap/vwmulsu_vv-i8-mf4.c |  21 +++
 .../autovec/group_overlap/vwmulsu_vv-i8-mf8.c |  21 +++
 .../gcc.target/riscv/rvv/base/pr112431-48.c   |  66 ++++++++
 18 files changed, 530 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c