mbox series

[v1,0/5] Support RVV register overlap for v[sz]ext.vf4

Message ID 20260708142206.215039-1-pan2.li@intel.com
Headers
Series Support RVV register overlap for v[sz]ext.vf4 |

Message

Li, Pan2 July 8, 2026, 2:20 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Like v[sz]ext.vf2, we continue the support for v[sz]ext.vf4.

Pan Li (5):
  RISC-V: Allow RVV register overlap for v[sz]ext.vf4
  RISC-V: Add test cases for vsext.vf4 reg overlap
  RISC-V: Add test cases for vzext.vf4 reg overlap
  RISC-V: Adjust the scan asm for v[sz]ext.vf2 for v1 and v12
  RISC-V: Adjust test case due to vf[sz]ext.vf4 overlap

 gcc/config/riscv/riscv-protos.h               |  1 +
 gcc/config/riscv/riscv-v.cc                   | 26 ++++++++++++++++++-
 gcc/config/riscv/vector.md                    | 16 ++++++------
 .../autovec/group_overlap/vsext_vf2-i16-m1.c  |  4 +--
 .../autovec/group_overlap/vsext_vf2-i16-m2.c  |  2 +-
 .../autovec/group_overlap/vsext_vf2-i16-m4.c  |  2 +-
 .../autovec/group_overlap/vsext_vf2-i16-mf2.c |  4 +--
 .../autovec/group_overlap/vsext_vf2-i16-mf4.c |  4 +--
 .../autovec/group_overlap/vsext_vf2-i32-m1.c  |  4 +--
 .../autovec/group_overlap/vsext_vf2-i32-m2.c  |  2 +-
 .../autovec/group_overlap/vsext_vf2-i32-mf2.c |  4 +--
 .../autovec/group_overlap/vsext_vf2-i8-m1.c   |  4 +--
 .../autovec/group_overlap/vsext_vf2-i8-m2.c   |  2 +-
 .../autovec/group_overlap/vsext_vf2-i8-mf2.c  |  4 +--
 .../autovec/group_overlap/vsext_vf2-i8-mf4.c  |  4 +--
 .../autovec/group_overlap/vsext_vf2-i8-mf8.c  |  4 +--
 .../autovec/group_overlap/vsext_vf4-i16-m1.c  | 17 ++++++++++++
 .../autovec/group_overlap/vsext_vf4-i16-m2.c  | 17 ++++++++++++
 .../autovec/group_overlap/vsext_vf4-i16-mf2.c | 23 ++++++++++++++++
 .../autovec/group_overlap/vsext_vf4-i16-mf4.c | 23 ++++++++++++++++
 .../autovec/group_overlap/vsext_vf4-i8-m1.c   | 17 ++++++++++++
 .../autovec/group_overlap/vsext_vf4-i8-m2.c   | 17 ++++++++++++
 .../autovec/group_overlap/vsext_vf4-i8-mf2.c  | 23 ++++++++++++++++
 .../autovec/group_overlap/vsext_vf4-i8-mf4.c  | 23 ++++++++++++++++
 .../autovec/group_overlap/vsext_vf4-i8-mf8.c  | 23 ++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-m1.c  | 17 ++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-m2.c  | 17 ++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-mf2.c | 23 ++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-mf4.c | 23 ++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-m1.c   | 17 ++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-m2.c   | 17 ++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-mf2.c  | 23 ++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-mf4.c  | 23 ++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-mf8.c  | 23 ++++++++++++++++
 .../gcc.target/riscv/rvv/base/pr112431-16.c   |  2 +-
 .../gcc.target/riscv/rvv/base/pr112431-17.c   |  2 +-
 36 files changed, 424 insertions(+), 33 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c