From patchwork Fri Sep 12 14:14:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 58941 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 730E73857B8F for ; Fri, 12 Sep 2025 23:36:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 730E73857B8F Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=G8i5jEmR X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 197993858D21 for ; Fri, 12 Sep 2025 23:34:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 197993858D21 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 197993858D21 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1757720074; cv=none; b=kKsRjTY7R98lvWh6jEKHFw8rkMTB/5PtDiWpN8H5WaR9ZgUzWsbD4sMgce5eEbpwUk8U/74UVWZBJtDb5RLOB8s6qWpHCEoVOvaWOY5L/4hba/OfyD6Co18VfaGeqmHokWN9KJruykuniRH+VRIxFrx/ZJbuCdUX2o4vmIO11UU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1757720074; c=relaxed/simple; bh=V5n9MCZjm1XD/Iwh2jIAtAGUgr53YfOZM+ZoAthkWYE=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=a8nT6B1OfO+04v2/MndorOmIuCCwATYJRH/zaA6dWhJQXA2Y+pdZkssyP5aXvYsPWVl0Uyn5WVd03EmersQ+C31qgBLLQ65B07sYe2/w4psnO24fsRJLJusgUEo3K/b9QbNybd6qYN783s+dH2r6aM7MPbsO8/5OukkQlmO8QeI= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 197993858D21 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757720074; x=1789256074; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=V5n9MCZjm1XD/Iwh2jIAtAGUgr53YfOZM+ZoAthkWYE=; b=G8i5jEmRt2keBDfr8HnkyKnJKGE7TmMraksUG9XRTIJPaatafqvnkSxy w4k/5KgLf+rSkYYQQOCLtmTGnKokMWkqs/xB88x9rLwWW7/rbkwLY9eX8 ArS2qLfo1VDokHXrbeDXdwUtPupJajl1FUHXswWbcvLB0UWGtT7UOKa7h 4ZkOlWAX7CoE/ts05qlS8s/1996VdyqS0q6yZZSApfHPUgh88dwt2YJ09 r158UoZVyMpwEH10zIblHD+wF5Eet1J14hFIA8hgIhzmvJQjeM3ofqyp/ HgTQ02B13tsSqjErif8av5GYu1IQjHxgVNxvvcSAIcJtEYzYLoMqKUGE9 Q==; X-CSE-ConnectionGUID: I7TST05KTyKITa7yYHYsNQ== X-CSE-MsgGUID: o7rSH4iWTV6qqb8oG3b/gA== X-IronPort-AV: E=McAfee;i="6800,10657,11551"; a="85500921" X-IronPort-AV: E=Sophos;i="6.18,260,1751266800"; d="scan'208";a="85500921" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2025 16:34:33 -0700 X-CSE-ConnectionGUID: xSv/IQl5Qa6eY0n4YNa9fw== X-CSE-MsgGUID: sKLjHL//RSWJQNyQujbuJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,260,1751266800"; d="scan'208";a="173285383" Received: from panli.sh.intel.com ([10.239.159.63]) by orviesa006.jf.intel.com with ESMTP; 12 Sep 2025 16:34:30 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 0/4] RISC-V: Combine vec_duplicate + v{widen}u.vv to v{widen}u.vx on GR2VR cost Date: Fri, 12 Sep 2025 22:14:29 +0800 Message-ID: <20250912233514.3586587-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to introduce the combine of vec_dup + v{widen}u.vv into v{widen}u.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VRlike 1, 2, 15 in test. The below insn from uint32_t to uint64_t are included. * vwaddu.vx * vwsubu.vx * vwmulu.vx From: | ... | vmv.v.x | L1: | v{widen}u.vv | J L1 | ... To: | ... | L1: | v{widen}u.vx | J L1 | ... The below test suites are passed for this patch series. * The rv64gcv fully regression test. Pan Li (4): RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on GR2VR cost RISC-V: Add test for vec_duplicate + vwaddu.vv signed combine with GR2VR cost 0, 1 and 15 RISC-V: Add test for vec_duplicate + vwsubu.vv signed combine with GR2VR cost 0, 1 and 15 RISC-V: Add test for vec_duplicate + vwmulu.vv signed combine with GR2VR cost 0, 1 and 15 gcc/config/riscv/autovec-opt.md | 44 +++++ gcc/config/riscv/iterators.md | 3 + gcc/config/riscv/vector-iterators.md | 16 ++ .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 6 + .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 6 + .../rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c | 18 ++ .../rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c | 18 ++ .../rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c | 18 ++ .../riscv/rvv/autovec/vx_vf/vx_widen.h | 36 ++++ .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 159 ++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h | 27 +++ 18 files changed, 393 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h