| Message ID | 20241101032345.3501979-1-haochen.jiang@intel.com |
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Return-Path: <gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 68964385841C for <patchwork@sourceware.org>; Fri, 1 Nov 2024 03:24:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by sourceware.org (Postfix) with ESMTPS id B56BC3858D26 for <gcc-patches@gcc.gnu.org>; Fri, 1 Nov 2024 03:23:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B56BC3858D26 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B56BC3858D26 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730431433; cv=none; b=FSsewZbN4y8kABMWqY15fmA0v+e3VgkX3o5B3kYaIgEwZlkBp1CExVAJoeURdsKivpCsVXYEr/QH1VVZ5OmdLIFOvFZhIrk7GMOQLdHpZ5B5vadle01MyxtOvk2mOAJZDFIIiFNcf1OzdLrJ982b8gYavx2EXqQWHGVvITlDDqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730431433; c=relaxed/simple; bh=6wB8YJD2N+Fz4cRwrlMYDjPBrJhtPeYh8kqiYUi5olo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=K1WKsbwT5EN0yvDenIHO+4EGkE2QQINIMoPU7kcD6HIaqoRkAnJVZPWT74MAHVIWkJq6vetgL6Gm8aID7ON2bIRvCT0vbmLqxROb3fMDb99ZUCA+VA1Xp+LEV3w7YYQRTy1a9YAPg1iikCQCyRbSVtv7OxclgXPwuhWoU7s8iNA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730431431; x=1761967431; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6wB8YJD2N+Fz4cRwrlMYDjPBrJhtPeYh8kqiYUi5olo=; b=P8TKqTq3K3oDbXGi6S7H8yw3/RWNyL1tjf+BwI+NvO3eYQZQLRhkx5en Mt8AVB0oWhoa98EQ1MlwCPavHq9PfwsTzCbmUI1n0DEw2aza9YIhD8aEM Q/bwkB27U1OF+yZJfGNpbEGiSfe7mVie+2EpMEifWWZlFTwJp9Yfji+Hg De8S5z01ddFwiLRlsndPh6RDdBGoykF3IpaozVOFjpjwzMBxfQBHYnyWl Od1myM64MAPtGsBLSMnX0g88xX8xdM1IZ03D9vsWiBiSngi0kImYvRBVa QO4STnpuPrAtAanyrnDfoSZZ6/rrUJm368W+6K+9N4GowMpCO20gCyACU Q==; X-CSE-ConnectionGUID: Jx9U8sHARkWr/AnqeULRyA== X-CSE-MsgGUID: 5tmfHBrIQJagjHRj+GpoTg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="30383331" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="30383331" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 20:23:49 -0700 X-CSE-ConnectionGUID: qsKyTC+RSk61PoJLxGwDRQ== X-CSE-MsgGUID: 8jdYNnW4TW2Xpc+VaK+BRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,248,1725346800"; d="scan'208";a="83272601" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by orviesa007.jf.intel.com with ESMTP; 31 Oct 2024 20:23:49 -0700 From: Haochen Jiang <haochen.jiang@intel.com> To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 0/2] Add arch support for Intel CPUs Date: Fri, 1 Nov 2024 11:23:43 +0800 Message-Id: <20241101032345.3501979-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org |
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Add arch support for Intel CPUs
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Message
Jiang, Haochen
Nov. 1, 2024, 3:23 a.m. UTC
Hi all, I have just landed new ISA patches on trunk. The next step will be the arch support for ISE055 mentioned CPUs. There are two changes in ISE055 on CPUs: - A new model number is added for Arrow Lake. - Diamond Rapids Support is added. The following two patches will reflect those changes. Bootstraped and tested on x86_64-pc-linux-gnu. Ok for trunk and ARL patch backport to GCC14? Ref: https://cdrdv2.intel.com/v1/dl/getContent/671368 Thx, Haochen
Comments
On Fri, Nov 1, 2024 at 11:24 AM Haochen Jiang <haochen.jiang@intel.com> wrote: > > Hi all, > > I have just landed new ISA patches on trunk. The next step will > be the arch support for ISE055 mentioned CPUs. > > There are two changes in ISE055 on CPUs: > > - A new model number is added for Arrow Lake. > - Diamond Rapids Support is added. > > The following two patches will reflect those changes. > > Bootstraped and tested on x86_64-pc-linux-gnu. Ok for trunk and > ARL patch backport to GCC14? Ok. > > Ref: https://cdrdv2.intel.com/v1/dl/getContent/671368 > > Thx, > Haochen > >