[v2,0/5] aarch64: Add Armv9.4-a 128-bit system-register read/write support

Message ID 20231128155609.198744-1-victor.donascimento@arm.com
Headers
Series aarch64: Add Armv9.4-a 128-bit system-register read/write support |

Message

Victor Do Nascimento Nov. 28, 2023, 3:55 p.m. UTC
  Changes from v1 -
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635531.html

  * [PATCH 4/5] - For `error_at' message, put feature name in quotes.
  * [PATCH 4/5] - For `aarch64_retrieve_sysreg' function, add
  description of new parameter to comments.
  * [PATCH 5/5] - Reduce the minimum arch requirements of the system
  register unit tests, selectively using `#pragma GCC target' when
  testing 128-bit sysreg r/w functions.

---

Given the introduction of optional 128-bit page table descriptor and
translation hardening extension support with the Arm9.4-a
architecture, this patch series introduces the necessary changes to
the aarch64-specific builtin code to enable the reading and writing of
128-bit system registers.  In so doing, the following ACLE builtins and
feature macro are made available to the compiler:

  * __uint128_t __arm_rsr128(const char *special_register);
  * void __arm_wsr128(const char *special_register, __uint128_t value);
  * __ARM_FEATURE_SYSREG128.

Finally, in order to update the GCC system-register database bringing
it in line with Binutils, and in so doing add the relevant 128-bit
system registers to GCC, this patch also introduces the Guarded
Control Stack (GCS) `+gcs' architecture modifier flag, allowing the
inclusion of the novel GCS system registers which are now supported
and also present in the `aarch64-sys-regs.def' system register
database.

Victor Do Nascimento (5):
  aarch64: Add march flags for +the and +d128 arch extensions
  aarch64: Add support for GCS system registers with the +gcs modifier
  aarch64: Sync `aarch64-sys-regs.def' with Binutils.
  aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins
  aarch64: Add rsr128 and wsr128 ACLE tests

 gcc/config/aarch64/aarch64-arches.def         |  2 +
 gcc/config/aarch64/aarch64-builtins.cc        | 50 ++++++++++++++++---
 gcc/config/aarch64/aarch64-c.cc               |  1 +
 .../aarch64/aarch64-option-extensions.def     |  6 +++
 gcc/config/aarch64/aarch64-protos.h           |  2 +-
 gcc/config/aarch64/aarch64-sys-regs.def       | 30 +++++++----
 gcc/config/aarch64/aarch64.cc                 |  9 +++-
 gcc/config/aarch64/aarch64.h                  | 21 ++++++++
 gcc/config/aarch64/aarch64.md                 | 18 +++++++
 gcc/config/aarch64/arm_acle.h                 | 11 ++++
 gcc/doc/invoke.texi                           |  8 +++
 gcc/testsuite/gcc.target/aarch64/acle/rwsr.c  | 32 ++++++++++++
 12 files changed, 170 insertions(+), 20 deletions(-)
  

Comments

Richard Sandiford Nov. 28, 2023, 10:46 p.m. UTC | #1
Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Changes from v1 -
> https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635531.html
>
>   * [PATCH 4/5] - For `error_at' message, put feature name in quotes.
>   * [PATCH 4/5] - For `aarch64_retrieve_sysreg' function, add
>   description of new parameter to comments.
>   * [PATCH 5/5] - Reduce the minimum arch requirements of the system
>   register unit tests, selectively using `#pragma GCC target' when
>   testing 128-bit sysreg r/w functions.

OK for the series, thanks, with the changelog tweak that Kyrill
asked for.  1-3 had already been approved and I agree that the new
versions of 4 and 5 address the review comments.

Richard

> ---
>
> Given the introduction of optional 128-bit page table descriptor and
> translation hardening extension support with the Arm9.4-a
> architecture, this patch series introduces the necessary changes to
> the aarch64-specific builtin code to enable the reading and writing of
> 128-bit system registers.  In so doing, the following ACLE builtins and
> feature macro are made available to the compiler:
>
>   * __uint128_t __arm_rsr128(const char *special_register);
>   * void __arm_wsr128(const char *special_register, __uint128_t value);
>   * __ARM_FEATURE_SYSREG128.
>
> Finally, in order to update the GCC system-register database bringing
> it in line with Binutils, and in so doing add the relevant 128-bit
> system registers to GCC, this patch also introduces the Guarded
> Control Stack (GCS) `+gcs' architecture modifier flag, allowing the
> inclusion of the novel GCS system registers which are now supported
> and also present in the `aarch64-sys-regs.def' system register
> database.
>
> Victor Do Nascimento (5):
>   aarch64: Add march flags for +the and +d128 arch extensions
>   aarch64: Add support for GCS system registers with the +gcs modifier
>   aarch64: Sync `aarch64-sys-regs.def' with Binutils.
>   aarch64: Implement 128-bit extension to ACLE sysreg r/w builtins
>   aarch64: Add rsr128 and wsr128 ACLE tests
>
>  gcc/config/aarch64/aarch64-arches.def         |  2 +
>  gcc/config/aarch64/aarch64-builtins.cc        | 50 ++++++++++++++++---
>  gcc/config/aarch64/aarch64-c.cc               |  1 +
>  .../aarch64/aarch64-option-extensions.def     |  6 +++
>  gcc/config/aarch64/aarch64-protos.h           |  2 +-
>  gcc/config/aarch64/aarch64-sys-regs.def       | 30 +++++++----
>  gcc/config/aarch64/aarch64.cc                 |  9 +++-
>  gcc/config/aarch64/aarch64.h                  | 21 ++++++++
>  gcc/config/aarch64/aarch64.md                 | 18 +++++++
>  gcc/config/aarch64/arm_acle.h                 | 11 ++++
>  gcc/doc/invoke.texi                           |  8 +++
>  gcc/testsuite/gcc.target/aarch64/acle/rwsr.c  | 32 ++++++++++++
>  12 files changed, 170 insertions(+), 20 deletions(-)