mbox series

[v2,0/4] Add Loongson SX/ASX instruction support to

Message ID 20230907070101.22062-1-chenxiaolong@loongson.cn
Headers
Series Add Loongson SX/ASX instruction support to |

Message

chenxiaolong Sept. 7, 2023, 7 a.m. UTC 
  In order to better test the function of the vector instruction, the 128 and 256 
bit test cases are further split according to the function of the instruction.

Xiaolong Chen (4):
  LoongArch: Add tests of -mstrict-align option.
  LoongArch: Add testsuite framework for Loongson SX/ASX.
  LoongArch: Add tests for Loongson SX builtin functions.
  LoongArch:Add Loongson SX/ASX instruction support to LoongArch

 .../gcc.target/loongarch/strict-align.c       |   13 +
 .../loongarch/vector/loongarch-vector.exp     |   42 +
 .../loongarch/vector/lsx/lsx-builtin.c        | 1461 +++++++++++++++++
 .../loongarch/vector/lsx/lsx-vfcvt-1.c        |  397 +++++
 .../loongarch/vector/lsx/lsx-vfcvt-2.c        |  277 ++++
 .../loongarch/vector/lsx/lsx-vffint-1.c       |  160 ++
 .../loongarch/vector/lsx/lsx-vffint-2.c       |  263 +++
 .../loongarch/vector/lsx/lsx-vffint-3.c       |  101 ++
 .../loongarch/vector/lsx/lsx-vfrint_d.c       |  229 +++
 .../loongarch/vector/lsx/lsx-vfrint_s.c       |  349 ++++
 .../loongarch/vector/lsx/lsx-vftint-1.c       |  348 ++++
 .../loongarch/vector/lsx/lsx-vftint-2.c       |  694 ++++++++
 .../loongarch/vector/lsx/lsx-vftint-3.c       | 1027 ++++++++++++
 .../loongarch/vector/lsx/lsx-vftint-4.c       |  344 ++++
 .../loongarch/vector/simd_correctness_check.h |   39 +
 15 files changed, 5744 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h