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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:53 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 00/10] RISC-V: Support the Zicond (conditional-operations) extension Date: Fri, 10 Feb 2023 23:41:40 +0100 Message-Id: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The (proposed, but about to be frozen) Zicond extension adds 2 unconditional R-type instructions that can be used to build branchless sequences that have conditional-arithmetic/bitwise/select semantics and integrate will with the RISC-V architecture. See the Zicond specification for details: https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230207/riscv-zicond_1.0-draft-20230207.pdf The Zicond extension defines a conditional-zero(-or-value) instruction, which is similar to the following C construct: rd = rc ? rs : 0 This functionality can be tied back into if-convertsion and also matches some typical programming idioms. This series includes backend support for Zicond both to handle conditional-zero constructions and if-conversion. We also change the previously submitted XVentanaCondops support to use the Zicond infrastructure. Tested against SPEC CPU 2017. Philipp Tomsich (10): docs: Document a canonical RTL for a conditional-zero insns RISC-V: Recognize Zicond (conditional operations) extension RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion RISC-V: Support immediates in Zicond RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez RISC-V: Recognize sign-extract + and cases for czero.eqz/nez RISC-V: Recognize bexti in negated if-conversion ifcvt: add if-conversion to conditional-zero instructions RISC-V: Recognize xventanacondops extension RISC-V: Support XVentanaCondOps extension gcc/common/config/riscv/riscv-common.cc | 5 + gcc/config/riscv/predicates.md | 12 + gcc/config/riscv/riscv-opts.h | 5 + gcc/config/riscv/riscv.cc | 15 ++ gcc/config/riscv/riscv.md | 28 +++ gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/xventanacondops.md | 29 +++ gcc/config/riscv/zicond.md | 156 +++++++++++++ gcc/doc/md.texi | 17 ++ gcc/ifcvt.cc | 216 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../riscv/xventanacondops-ifconv-imm.c | 19 ++ .../gcc.target/riscv/xventanacondops-le-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-le-02.c | 11 + .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-lt-03.c | 16 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 10 + .../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++ .../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ .../gcc.target/riscv/zicond-and-01.c | 16 ++ .../gcc.target/riscv/zicond-and-02.c | 15 ++ gcc/testsuite/gcc.target/riscv/zicond-eq-01.c | 11 + gcc/testsuite/gcc.target/riscv/zicond-eq-02.c | 14 ++ .../gcc.target/riscv/zicond-ifconv-imm.c | 19 ++ gcc/testsuite/gcc.target/riscv/zicond-le-01.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-le-02.c | 11 + gcc/testsuite/gcc.target/riscv/zicond-lt-01.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-lt-03.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-ne-01.c | 10 + gcc/testsuite/gcc.target/riscv/zicond-ne-03.c | 13 ++ gcc/testsuite/gcc.target/riscv/zicond-ne-04.c | 13 ++ .../gcc.target/riscv/zicond-xor-01.c | 14 ++ 36 files changed, 854 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/config/riscv/zicond.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-xor-01.c