From patchwork Fri Jan 20 16:39:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 55423 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E244C3889E34 for ; Fri, 20 Jan 2023 16:47:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E244C3889E34 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1674233247; bh=VObCFJaOoM8R/jd7w9eGgHRitGfhICDJ1GckReUAx80=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=l1Ug2w5D3YgEkzY1OdTP+0SDXd+BP37iJCd6/kje6Kktg+cJnTgSEe+tWWdJGyzuH Ql9Uaqe8aGOS7tMuS1hcNdCjicKPhomFS41oGDYGn3QCsFge1z8FkoAVCnHC//0Z9d nCAsN1QFFS9I/d88i9cRZQrk2J2C6aZlIzCmv2D0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on2045.outbound.protection.outlook.com [40.107.14.45]) by sourceware.org (Postfix) with ESMTPS id 5F3E4385439B for ; Fri, 20 Jan 2023 16:41:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5F3E4385439B Received: from AM6PR10CA0037.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:209:80::14) by AS2PR08MB8831.eurprd08.prod.outlook.com (2603:10a6:20b:5f4::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.12; Fri, 20 Jan 2023 16:41:22 +0000 Received: from AM7EUR03FT041.eop-EUR03.prod.protection.outlook.com (2603:10a6:209:80:cafe::f) by AM6PR10CA0037.outlook.office365.com (2603:10a6:209:80::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Fri, 20 Jan 2023 16:41:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT041.mail.protection.outlook.com (100.127.140.233) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Fri, 20 Jan 2023 16:41:22 +0000 Received: ("Tessian outbound 3ad958cd7492:v132"); Fri, 20 Jan 2023 16:41:22 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 9a587ce4a6caf1b2 X-CR-MTA-TID: 64aa7808 Received: from fd89d87c3053.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id D3D52319-029D-483B-B8D8-DEB6538A255E.1; Fri, 20 Jan 2023 16:40:25 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id fd89d87c3053.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 20 Jan 2023 16:40:25 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UihKxI8P8RUTfx3t10sa0PUGVpThY8HD879uQxBk0vdrTnFC8HbuqFBspcpZOUPq+tJbWi895cAjrUzZ74f/wpKeFawRaPmBkC9Gy/sE4gPpFuKFtse3UEYXMgFVHtc7R6jRlMi21NroPj7iH0rM+F+EhdGiomZQWqfrZRXX2uCGZ1VzhvQkTXQy0OcM0ix35VF6rpYg+bQR8mmmvh7Wfey2SvUvTXRsh8SrZNzU6VO8PE9pYEVE1zuFhlxsVmOQzUL2yxoSlqZdZXMsajj4Wrpf8kzTzyeIsjXO5gjYLlA41gyKwhcfCnc45dQ66I5ccy8uF8jvNXE9rJs1SrkIjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VObCFJaOoM8R/jd7w9eGgHRitGfhICDJ1GckReUAx80=; b=aCOFypZJEBkWuB4TO0sJKZCUbOMXnOgH/Wawhfmt2SC7n77uWPFvDchedbNNukCaGJX4kZfnloyg0RzkA2Rrtv/tZh2gYj/qFWowzmmfQCj4v3Tkyxy8gM/HBN9yag4MsvCXJH1SWiywbJuu01gAAmshnnvFn2bQyUCBaGnoUF4JPRKfU61oDKWkQgijgUi+K3cHvMpg3CLtpy9OhaE1ADig25Se7XcqOaxgBi1scjiG+aPCx7Rkj3Xph5NTGGNAGunjNW6eSQT/b1Ue7F73ma1zUBjw44Y3HERo2PLW+pvP48ysJ0Tq9ipEsAHh44HFSFpPwRxNVHxnKDAIT+iumg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AS9PR06CA0080.eurprd06.prod.outlook.com (2603:10a6:20b:464::16) by PR3PR08MB5705.eurprd08.prod.outlook.com (2603:10a6:102:93::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27; Fri, 20 Jan 2023 16:40:23 +0000 Received: from AM7EUR03FT059.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:464::4) by AS9PR06CA0080.outlook.office365.com (2603:10a6:20b:464::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Fri, 20 Jan 2023 16:40:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT059.mail.protection.outlook.com (100.127.140.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6023.16 via Frontend Transport; Fri, 20 Jan 2023 16:40:23 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Fri, 20 Jan 2023 16:40:20 +0000 Received: from e124257.nice.arm.com (10.34.105.24) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Fri, 20 Jan 2023 16:40:20 +0000 To: CC: , , Andrea Corallo Subject: [PATCH 00/23] arm: rework MVE testsuite and rework backend where necessary (3rd chunck) Date: Fri, 20 Jan 2023 17:39:25 +0100 Message-ID: <20230120163948.752531-1-andrea.corallo@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT059:EE_|PR3PR08MB5705:EE_|AM7EUR03FT041:EE_|AS2PR08MB8831:EE_ X-MS-Office365-Filtering-Correlation-Id: acaa3627-d8fd-46c7-2e81-08dafb0529f9 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 4iUH9no7Phc96ovIgEcveTMK5mHZUPR8W/T/W8l1Hu0h1Cf1OH2lI4mD7HSyfDQqC8HWko8U7NolLGSLMkCIOJ+kaC7hDjuVY1bs2oQigh24+i986GGesFFgXuKgcmsTs1f/5ispLxjtLdZxizzAj86RsIhwKq+5coDtHXHuLuGsGRaipbjAAZEinMHbQNXL6H2zduExxGKH7UwB64+5LUA82Y1ZK9uQkqKKC3BAiasHFcOn2e9o1WcjWoN7WqD+X1HND344V8dzV7Atuecr27Gw4RSdtUBqjIl+zvWHGzyDvAqEDtFE9ki+DHNcvWadJBDLlbrcvePhsIO10teOJ/edipKDLGqJDmmlot0mf+qotnTAseq+Xvz0IKK34kgGaQz1jwkNKDRzPUS4ICq1DwrTfKKNub9/QAXLg4z9DzBqyveo5BKmU9dMc4o+6hLVRznok+xpRAPFllg4Es2K4duHMcWX25ckeO9nbKQQi5jzwsgkBcGizroRX+uK46IIiTg8RuJMZLbAHZUKTGPap3inhwgsuHnz6ZvWDHkcl8gUYtdVYL0uTrrTS1jWfxnXJEJOuC3ZnmykUvkf/OjtLBRhjrbTMW2HRxzTkXZPXqc66QA1l+qDjKswTg495SwMlD5srhEZEg0qIgOt2lX5vtMvwPXYjnojqX1guSxel2PfitDM0e1iegXXsJhGaDeEY33XBfB0IkBRzqTpn/cOHMezsxLL5920ceHaTYkhlUM= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(316002)(36860700001)(83380400001)(7696005)(478600001)(2616005)(44832011)(30864003)(5660300002)(36756003)(2906002)(82740400003)(1076003)(186003)(426003)(40480700001)(336012)(47076005)(41300700001)(54906003)(26005)(8936002)(70586007)(70206006)(86362001)(6916009)(40460700003)(4326008)(8676002)(356005)(81166007)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR08MB5705 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT041.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: d9a903c3-7cb8-4aee-b79d-08dafb0506ca X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iNDJsH+IFPvrA4BU7fi/HMUsyDm/luiQM9Dqae1n0BaQ8CHipnavCILD5alJeVfKhhwHtL7gHYJ7jhhvUkWmXDR+stQFeQQZCv5HeGT/o2pTl8sOT+wO3CMoefeZrtqtv/mfrkFik525t/xz6zqwc9ejeantLVtKD6BnQJjmQelrNzdavUruCUhxSIbaa0jeDCZdRSwaGhAXPoCJBd0T1XvHr4dx0NDxXvBvpyPerEUt6N00b7GcjZDXrWEax/dKhrLlKjgnJJSTq8T9peAya46PWWoIgaiBnEUGpYu50bOTU5NianeN832UVjhgvUzD1gPCiMaPsG1a5C90mmUrDNWXP8l5HCr5EvS+91FgSiNdAI2pkzKXxjhc+rfpogOeIBPWk6Z8J6StHvqDGtibGqRyoS8NHX4dJqJ+3aHM5bLAiVGszrUcQ4kOQG5+Horg0QYcwZ8Cuae6UD8oOheELsXBlQ2xzldHszCDSpGb49yJRtG3uQcwuJyruVAiHY0W2uHsFI71OgtprtuQh9cPXyq6lrIkqZ/WHPo2gG20suBnFfS8yb/EsNG3NTEFa0eHM9t8pKOprFdRF4Ae0pi/rdJPpmi9nJkAJyQgKKv0Aeo99tGTFYyEj2UmTthJVTadLJ+z0ZMhvV2sGKc8zjIKPIdGzs35eOmlZ7kIKDC0blU1HgCWGecfupgLNr1myQR8t3/w7zCSAOe58mcKWJsWeQ== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(46966006)(36840700001)(40470700004)(70586007)(36860700001)(40460700003)(47076005)(336012)(426003)(8936002)(316002)(54906003)(36756003)(1076003)(83380400001)(40480700001)(41300700001)(2906002)(44832011)(8676002)(5660300002)(70206006)(30864003)(4326008)(2616005)(6916009)(82740400003)(26005)(81166007)(86362001)(186003)(7696005)(478600001)(82310400005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2023 16:41:22.3482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acaa3627-d8fd-46c7-2e81-08dafb0529f9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT041.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8831 X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, this 3rd series, similarly to the previous ones, rework the arm MVE testsuite for better coverage. Contextually some trivial fixes to the backend are performed. 23/23 also adds some extern "C" I forgot to add with the previous series in order to fix those tests for C++. Best Regards Andrea Andrea Corallo (23): arm: improve tests and fix vclsq* arm: improve tests and fix vclzq* arm: improve tests and fix vnegq* arm: improve tests for vmulhq* arm: improve tests for vmullbq* arm: improve tests for vmulltq* arm: improve tests for vcaddq* arm: improve tests for vcmlaq* arm: improve tests for vcmulq* arm: improve tests and fix vqabsq* arm: improve tests for vqdmladhq* arm: improve tests for vqdmladhxq* arm: improve tests for vqrdmladhq* arm: improve tests for vqrdmladhxq* arm: improve tests for vqrdmlashq* arm: improve tests for vqdmlsdhq* arm: improve tests for vqdmlsdhxq* arm: improve tests for vqrdmlsdhq* arm: improve tests for vqrdmlsdhxq* arm: improve tests for vqrdmulhq* arm: improve tests and fix vqnegq* arm: improve tests for vld2q* arm: fix missing extern "C" in MVE tests gcc/config/arm/mve.md | 12 +++---- .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclsq_m_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclsq_m_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclsq_m_s8.c | 33 ++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vclsq_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclsq_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclsq_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_m_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_m_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_m_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_m_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_m_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_m_u8.c | 33 ++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 24 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 28 ++++++++++++--- .../arm/mve/intrinsics/vclzq_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_x_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_x_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vclzq_x_u8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcmlaq_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vcmulq_x_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vcmulq_x_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vhaddq_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_n_u16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_n_u32.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_n_u8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_s16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_s32.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_u16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_u32.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_n_u16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_n_u32.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_n_u8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_s16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_s32.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_s8.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_u16.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_u32.c | 8 +++++ .../arm/mve/intrinsics/vhaddq_x_u8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_n_u16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_n_u32.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_n_u8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_s16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_s32.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_u16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_u32.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_n_u16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_n_u32.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_n_u8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_s16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_s32.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_s8.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_u16.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_u32.c | 8 +++++ .../arm/mve/intrinsics/vhsubq_x_u8.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 33 +++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 33 +++++++++++++++--- .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 8 +++++ .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 8 +++++ .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 8 +++++ .../arm/mve/intrinsics/vmladavaxq_s16.c | 8 +++++ .../arm/mve/intrinsics/vmladavaxq_s32.c | 8 +++++ .../arm/mve/intrinsics/vmladavaxq_s8.c | 8 +++++ .../arm/mve/intrinsics/vmulhq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulhq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulhq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulhq_m_u16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulhq_m_u32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulhq_m_u8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulhq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulhq_s32.c | 24 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulhq_u16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulhq_u32.c | 24 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulhq_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulhq_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulhq_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulhq_x_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulhq_x_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulhq_x_u8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_int_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_int_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_int_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_int_u16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_int_u32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_int_u8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmullbq_poly_p16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_poly_p8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_int_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_int_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_int_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_int_u16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_int_u32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_int_u8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vmulltq_poly_p16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_poly_p8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 33 ++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 30 +++++++++++++++- .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 30 +++++++++++++++- .../arm/mve/intrinsics/vnegq_m_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_m_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_m_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_m_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_m_s8.c | 33 ++++++++++++++++-- .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vnegq_x_f16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_x_f32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_x_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_x_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vnegq_x_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqabsq_m_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqabsq_m_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqabsq_m_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqabsq_s16.c | 28 ++++++++++++--- .../arm/mve/intrinsics/vqabsq_s32.c | 28 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqaddq_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_n_u16.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_n_u32.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_n_u8.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_s16.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_s32.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_u16.c | 8 +++++ .../arm/mve/intrinsics/vqaddq_u32.c | 8 +++++ .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 8 +++++ .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmladhq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmladhq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmladhq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmladhq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmladhxq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmladhxq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmladhxq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmlahq_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vqdmlahq_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vqdmlahq_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vqdmlashq_m_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vqdmlashq_m_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vqdmlashq_m_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vqdmlashq_n_s16.c | 8 +++++ .../arm/mve/intrinsics/vqdmlashq_n_s32.c | 8 +++++ .../arm/mve/intrinsics/vqdmlashq_n_s8.c | 8 +++++ .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmlsdhq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmlsdhq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmlsdhq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqdmlsdhxq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmlsdhxq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqdmlsdhxq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqnegq_m_s16.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqnegq_m_s32.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqnegq_m_s8.c | 33 ++++++++++++++++-- .../arm/mve/intrinsics/vqnegq_s16.c | 28 ++++++++++++--- .../arm/mve/intrinsics/vqnegq_s32.c | 24 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmladhq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmladhq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmladhq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmladhxq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 32 +++++++++++++---- .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 32 +++++++++++++---- .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 32 +++++++++++++---- .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmlsdhq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmlsdhq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmlsdhq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmulhq_m_s8.c | 34 ++++++++++++++++--- .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmulhq_n_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmulhq_s16.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmulhq_s32.c | 24 +++++++++++-- .../arm/mve/intrinsics/vqrdmulhq_s8.c | 24 +++++++++++-- .../arm/mve/intrinsics/vsetq_lane_f16.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_f32.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_s16.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_s32.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_s64.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_s8.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_u16.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_u32.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_u64.c | 8 +++++ .../arm/mve/intrinsics/vsetq_lane_u8.c | 8 +++++ gcc/testsuite/gcc.target/arm/simd/mve-vclz.c | 6 ++-- gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 4 +-- gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 2 +- 368 files changed, 8240 insertions(+), 878 deletions(-)