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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:41 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 0/7] Add XThead* support Date: Sun, 13 Nov 2022 22:46:29 +0100 Message-Id: <20221113214636.2747737-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This series adds support for the following vendor extensions from T-Head: * XTheadCmo, XTheadSync * XTheadBa, XTheadBb, XTheadBs * XTheadCondMov * XTheadMac * XTheadFmv, XTheadInt No regressions observed. Christoph Müllner (7): riscv: Add basic XThead* vendor extension support riscv: riscv-cores.def: Add T-Head XuanTie C906 riscv: thead: Add support for XTheadBa and XTheadBs ISA extensions riscv: thead: Add support for XTheadCondMov ISA extensions riscv: thead: Add support for XTheadBb ISA extension riscv: thead: Add support for XTheadMac ISA extension riscv: Add basic extension support for XTheadFmv and XTheadInt gcc/common/config/riscv/riscv-common.cc | 24 ++ gcc/config/riscv/bitmanip.md | 47 +++- gcc/config/riscv/iterators.md | 4 + gcc/config/riscv/riscv-cores.def | 2 + gcc/config/riscv/riscv-opts.h | 23 ++ gcc/config/riscv/riscv.cc | 67 ++++- gcc/config/riscv/riscv.md | 52 +++- gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/thead.md | 252 ++++++++++++++++++ .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++ gcc/testsuite/gcc.target/riscv/thead-mula-1.c | 40 +++ gcc/testsuite/gcc.target/riscv/thead-mula-2.c | 28 ++ .../gcc.target/riscv/xtheadba-addsl-64.c | 18 ++ .../gcc.target/riscv/xtheadba-addsl.c | 20 ++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 19 ++ .../gcc.target/riscv/xtheadbb-extu.c | 12 + gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 40 +++ .../gcc.target/riscv/xtheadbb-srri.c | 18 ++ gcc/testsuite/gcc.target/riscv/xtheadbb.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 12 + gcc/testsuite/gcc.target/riscv/xtheadbs.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 13 + .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 37 +++ .../riscv/xtheadcondmov-mveqz-imm-not.c | 37 +++ .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 37 +++ .../riscv/xtheadcondmov-mveqz-reg-not.c | 37 +++ .../riscv/xtheadcondmov-mvnez-imm-cond.c | 37 +++ .../riscv/xtheadcondmov-mvnez-imm-nez.c | 37 +++ .../riscv/xtheadcondmov-mvnez-reg-cond.c | 37 +++ .../riscv/xtheadcondmov-mvnez-reg-nez.c | 37 +++ .../gcc.target/riscv/xtheadcondmov.c | 13 + .../gcc.target/riscv/xtheadfmemidx.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadmac.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadsync.c | 13 + 38 files changed, 1123 insertions(+), 17 deletions(-) create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c