From patchwork Sun Nov 13 20:48:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 55289 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 94EA1388B681 for ; Sun, 13 Nov 2022 20:48:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id 82C3938582A1 for ; Sun, 13 Nov 2022 20:48:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 82C3938582A1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12e.google.com with SMTP id j16so16219915lfe.12 for ; Sun, 13 Nov 2022 12:48:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=UJX/c7H6uJyxaQPiWUya+9Z4D49uWUlDo6LtdKsLr20=; b=CqaXBUBtF9IsU4li3d8EuvNHpwkycSgLhbtuEw5LYN0coudOYvbKHuuSmz2wZ/UAVm E3lBWG/II0EEyZ2wxZ/DJ2Tk2lprSoXMbCC9BSymJ2CgKS4X+Bjrzd/KlLpooGgYjq29 jkgt4PacYcA4S+/ysZo6ARQ4a3j88FPANhgj81OhiAJGPwMDN4GOBPj/+tgdNlexJvsN t5GyZiYn6ZGhsGZLTH7dNu0dwOfKbD3da7uvnLcNo+clQvOMWbJ0ZIoxgGgcW0k89+pt FOYSXehhayAtWVf+Fpq5A99byXaKPwKyIWm51ubPEocIt5VxIg5hf2jpBhsQtCdI8Nu3 1clw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UJX/c7H6uJyxaQPiWUya+9Z4D49uWUlDo6LtdKsLr20=; b=Q7wPvGtgXImkpqb7WwUVqeizu15IDDSC3x4mfKh/aXvN+Uow0WvOWAsOr77dlVBLm8 0Hn8Wo5P3afKPpXzcPNLtZYggCRx7Wyp4kgZ5BHhNkoVxu5Nr/+gyAKFS0fEa1ubYkJZ 8rRLR+eYnfCydj2QVHJqnFrlCNN9nWkwB76MVzfv0wU98lkUkogfkwVAAS7OVUNLco4U AItHcfH/JQtiO1Wo1Yg1/NlSUqApfe6yAgNILMze0USTuZUFMWR25uvdoIwqSaUA00vI 6RPzmTF/vumUXp6+KMjxHYyOoeblzYRj6UojNnS/K/u0UclHcWhxkZqpuwbyGnw+/q8z r88g== X-Gm-Message-State: ANoB5pmsFSl2+0l3RMSLxAbyPtuHCz81nspSpuiQ2UUxgdOKwweX77jr ODnWT/yjwCdyqQLAk7RG9qhg2jFelHBBjvl6 X-Google-Smtp-Source: AA0mqf4GUxyYSXIUOpgQgNpAfhhZrGuacgUr478p26MH/EwADBf5tejdi3CJr/4X4+WmugwtJT5fKQ== X-Received: by 2002:ac2:46f7:0:b0:4a2:7c6a:5cad with SMTP id q23-20020ac246f7000000b004a27c6a5cadmr3191103lfo.366.1668372506745; Sun, 13 Nov 2022 12:48:26 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id m5-20020a056512114500b004979db5aa5bsm1520567lfg.223.2022.11.13.12.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 12:48:26 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Palmer Dabbelt , Vineet Gupta , Jeff Law , Kito Cheng , Christoph Muellner , Philipp Tomsich Subject: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion Date: Sun, 13 Nov 2022 21:48:22 +0100 Message-Id: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This series provides support for the Ventana VT1 (a 4-way superscalar rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support for the supported instruction fusion patterns. This includes the addition of the fusion-aware scheduling infrastructure for RISC-V and implements idiom recognition for the fusion patterns supported by VT1. Note that we don't signal support for XVentanaCondOps at this point, as the XVentanaCondOps support is in-flight separately. Changing the defaults for VT1 can happen late in the cycle, so no need to link the two different changesets. Changes in v2: - Rebased and changed over to .rst-based documentation - Updated to catch more fusion cases - Signals support for Zifencei Philipp Tomsich (2): RISC-V: Add basic support for the Ventana-VT1 core RISC-V: Add instruction fusion (for ventana-vt1) gcc/config/riscv/riscv-cores.def | 3 + gcc/config/riscv/riscv-opts.h | 2 +- gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ .../risc-v-options.rst | 5 +- 4 files changed, 240 insertions(+), 3 deletions(-)