From patchwork Fri May 27 06:07:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 54442 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D1AE382D471 for ; Fri, 27 May 2022 06:07:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7D1AE382D471 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653631677; bh=Vfynz9o6eRMF5R9tI1se8ijBJsdkz6U51xMel1sc6xo=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=AB1LqyBupYv9wEqj3kF3USRAc13sMubN7E2ZJQJAvP6ayjWOX7Mm7JMXcQwzsqxtg 6z6ZPnlCPCQ6Ug5NfGNTJh/5mbFkiNcrMI8MTI06xw27evch4PZMmDg449QMLSU9k3 SqyoQHMNlnXOW7z7UjZFC5EMArN6oaGdb+FmjMDY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by sourceware.org (Postfix) with ESMTPS id 117D9383D810; Fri, 27 May 2022 06:07:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 117D9383D810 Received: by mail-wr1-f52.google.com with SMTP id e28so4515429wra.10; Thu, 26 May 2022 23:07:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Vfynz9o6eRMF5R9tI1se8ijBJsdkz6U51xMel1sc6xo=; b=oPK5ST0EtcCQcMW6W5iv4vunwV4RoE1US8OgMRuwLeXrxETeAgdnunHko5Vw9XvJ6v lsRJSBUyhaQV2WYrOwEfiQ1kt+NLBa15cj1doXEt1fFeXzfwlbEMlJUx+ZOizfbhq6Oc FlicEHeTsHAYX1BA81BqN1REN3kHNQdvHgxOokmdpgAuCvBlTToS/P9R/2EbW5gS+Mpd OXun2Qtj2kNvGMTTNMdONWEDGCAw2RR3k8H2/fFELnBdlejDEtHq3ILBd5QhtIjN4ykR n21taQFDn5vhUnI7ArP3zsX0qCGswczb+IBUFllM8QtHhgrBe/5PRndZfMWWO0SuW4Rz 1JXQ== X-Gm-Message-State: AOAM532nDyIDTGDO+1IQ1m5msdBthNSNup6AubQbbQ2ApHffQESNHch5 4agPCZvhLC/+IsU2c1KsSGB6ufZvjcm0DOyd X-Google-Smtp-Source: ABdhPJzL//Synqw12MJyxVjU2cTwhU8KVr/egOORcyUzbqky3VStsMCtBETBP0eJViKnpxkigJSjgg== X-Received: by 2002:a5d:6dc6:0:b0:20f:bf64:c9fc with SMTP id d6-20020a5d6dc6000000b0020fbf64c9fcmr26847746wrz.648.1653631646520; Thu, 26 May 2022 23:07:26 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:26 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 0/9] [RISC-V] Atomics improvements Date: Fri, 27 May 2022 08:07:14 +0200 Message-Id: <20220527060723.235095-1-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This series provides a cleanup of the current atomics implementation of RISC-V (PR100265: Use proper fences for atomic load/store). The first patch could be squashed into the following patches, but I found it easier to understand the chances with it in place. The series has been tested as follows: * Building and testing a multilib RV32/64 toolchain (bootstrapped with riscv-gnu-toolchain repo) * Manual review of generated sequences for GCC's atomic builtins API This series was developed more than a year ago, but got never merged. v1 can be found here: https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568684.html v2 can be found here: https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569691.html Jim expressed concerns about patch 9/10 (which was inspired by the AArch64 implementation), that it won't emit the expected CAS sequence under register pressure. Therefore, I've dropped the patch from the series in v3. Changes for v3: * Rebase/retest on master * Drop patch 9/10 ("Provide programmatic implementation of CAS") Changes for v2: * Guard LL/SC sequence by compiler barriers ("blockage") (suggested by Andrew Waterman) * Changed commit message for AMOSWAP->STORE change (suggested by Andrew Waterman) * Extracted cbranch4 patch from patchset (suggested by Kito Cheng) * Introduce predicate riscv_sync_memory_operand (suggested by Jim Wilson) * Fix small code style issue Christoph Muellner (9): RISC-V: Simplify memory model code [PR 100265] RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265] RISC-V: Emit fences according to chosen memory model [PR 100265] RISC-V: Implement atomic_{load,store} [PR 100265] RISC-V: Model INSNs for LR and SC [PR 100266] RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266] gcc/config/riscv/riscv.cc | 61 +++---------- gcc/config/riscv/sync.md | 183 ++++++++++++++++++++++++++++++-------- 2 files changed, 159 insertions(+), 85 deletions(-)