From patchwork Thu Apr 7 18:33:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 52718 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5F74D3857404 for ; Thu, 7 Apr 2022 18:34:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id C4F383858D28 for ; Thu, 7 Apr 2022 18:34:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C4F383858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x629.google.com with SMTP id m16so5804864plx.3 for ; Thu, 07 Apr 2022 11:34:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Pf6MJBBQ4vn5zeDRtrcuSHyPYg6n7ytViEADKu7N2ow=; b=7tzXlqqCvYjYe7nDtD+J9KK86AorZZ8suFGUrzqfRDNKtfoIY10jr6M+hmH6JVkT09 t1tn1dU3NYLmm95jz1tm1hwaXFEwPIZHkN0a/JS2OQxDe2AT58YOg3iyR84AnXH7gQy1 RINlnEhid+iyB9ZLcTr0uqkqkBd41luweQeBKz6XrBNuWbXUpN4lmzLBAHRDjAUmmLrF kr4C4w8tku6odF0jtohdHls2VLXg/LjDZVRANLGmH9VFRApDXCSaFKolrAfqXBbR5BJf fQufyLpDnvkV6/7UypcJxzrfJxnL25tA+OAYs+xu4W5wlvjHTgVEbjKCSIchd2RbRQkc hXiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Pf6MJBBQ4vn5zeDRtrcuSHyPYg6n7ytViEADKu7N2ow=; b=Q30YLoH3tzPQW0wJdRZHo/5SRWj1MHffAblQhxxv0v+qpnqWGegrnKZKZh1Mzz4LNq 8ybk6mveslNz88Do8Xhuy+FwKWh3X4qPW0V6Ku2rL4is1Cm66EQJ524gjaJf1GG149Nj 6RN33dWmhLtY1Jbyux92y8sk30PaEIExFz8PrpQ7SSwCXcA7OgNL+AEiXPPc82UDqrjb qIzzCXRsE90p5jPMCaVWo1xtvm4x4Z8soegXFJTdWq5H4CQmYHyXnI1MIlkE9JN2t9W+ DWqVoG0XhBF8pasSNbVAqwUEeRp2g+MZSQhb/k/5pKErm3BVYX60kqg1lc7dJ6+C2ttd 0fdg== X-Gm-Message-State: AOAM532yUbUXpUD/nVMw+b3ostRqcM2LcAkxiz4+hxCGFeM9uX0LxFTf oVuEnVn1Q1+FBlTvaFz8f6M+3R7WBqlPsIiv X-Google-Smtp-Source: ABdhPJzOtYdM+AlGRXESfyMStHQX4J3nO92xNHk2Zl8nzyMm8LoWS9MmKUY9IR1NoW5ckDIjIFmatQ== X-Received: by 2002:a17:902:e94f:b0:14f:1636:c8a8 with SMTP id b15-20020a170902e94f00b0014f1636c8a8mr15196000pll.130.1649356472364; Thu, 07 Apr 2022 11:34:32 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([12.3.194.138]) by smtp.gmail.com with ESMTPSA id w7-20020a63a747000000b003991d7d3728sm13927891pgo.74.2022.04.07.11.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 11:34:31 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Subject: [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings Date: Thu, 7 Apr 2022 11:33:44 -0700 Message-Id: <20220407183351.295188-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@sifive.com, Patrick O'Neill , dlustig@nvidia.com, vineetg@rivosinc.com, gnu-toolchain@rivosinc.com, kito.cheng@sifive.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This series should not be applied as it causes an ABI break. This RFC aims to bring the RISCV atomics implementation in line with the recommended mapping present in table A.6 of the ISA manual. https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157 This mapping being implemented would result in an ABI break due to libatomic's LR.aq/SC.rl mapping and the A.6's SEQ_CST store mapping not enforcing SEQ_CST when placed next to eachother. This can be seen using the following Herd7 litmus test: RISCV W-RMW (* Seq_cst store along with LR.aq/SC.rl is insufficient for a seq_cst store, seq_cst RMW mapping. *) { 0:x7=A; 0:x8=B; 1:x7=A; 1:x8=B; } P0 | P1 ; ori x1,x0,1 | ori x1,x0,1 ; fence rw,w | fence rw,rw ; sw x1,0(x8) | sw x1,0(x7) ; lr.w.aq x3,0(x7) | fence rw,rw ; sc.w.rl x1,x1,0(x7) | lw x2,0(x8) ; exists (0:x3=0 /\ 1:x2=0) In GCC for SEQ_CST store, we currently emit fence iorw,ow + amoswap.aq, which successfully enforces ordering for the given litmus test. This will only be a problem in GCC if we move the SEQ_CST store to the A.6 mapping. Note: LLVM implements fence rw,w + sw https://godbolt.org/z/n68P7ne1W That means that LLVM isn't compatible with libatomic's LR.aq/SC.rl. * PR target/89835: The RISC-V target uses amoswap.w for relaxed stores Patrick O'Neill (7): RISCV: Enforce Libatomic LR/SC SEQ_CST RISCV: Enforce Atomic Compare Exchange SEQ_CST RISCV: Add AMO release bits RISCV: Optimize AMO Ops RISCV: Optimize LR/SC Pairs RISCV: Optimize Atomic Stores RISCV: Relax mem_thread_fence gcc/config/riscv/riscv-protos.h | 6 ++ gcc/config/riscv/riscv.cc | 93 +++++++++++++++++-- gcc/config/riscv/sync.md | 46 ++++++--- .../gcc.target/riscv/amo-thread-fence-1.c | 6 ++ .../gcc.target/riscv/amo-thread-fence-2.c | 6 ++ .../gcc.target/riscv/amo-thread-fence-3.c | 6 ++ .../gcc.target/riscv/amo-thread-fence-4.c | 6 ++ .../gcc.target/riscv/amo-thread-fence-5.c | 6 ++ .../gcc.target/riscv/inline-atomics-model-1.c | 12 +++ .../gcc.target/riscv/inline-atomics-model-2.c | 12 +++ .../gcc.target/riscv/inline-atomics-model-3.c | 12 +++ .../gcc.target/riscv/inline-atomics-model-4.c | 12 +++ .../gcc.target/riscv/inline-atomics-model-5.c | 12 +++ gcc/testsuite/gcc.target/riscv/pr89835.c | 9 ++ libgcc/config/riscv/atomic.c | 4 +- 15 files changed, 223 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/inline-atomics-model-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c