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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:23 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 0/8] Improvements to bitmanip-1.0 (Zb[abcs]) support Date: Thu, 11 Nov 2021 15:10:12 +0100 Message-Id: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This series provides assorted improvements for the RISC-V Zb[abcs] support collected over the last year and a half and forward-ported to the recently merged upstream support for the Zb[abcs] extensions. Improvements include: - synthesis of HImode bswap from SImode/DImode rev8 - cost-model change to support shift-and-add (sh[123]add) in the strength-reduction of multiplication operations - support for constant-loading of (1ULL << 31) on RV64 using bseti - generating a polarity-reversed mask from a bit-test - adds orc.b as UNSPEC - improves min/minu/max/maxu patterns to suppress redundant extensions Philipp Tomsich (8): bswap: synthesize HImode bswap from SImode or DImode RISC-V: costs: handle BSWAP RISC-V: costs: support shift-and-add in strength-reduction RISC-V: bitmanip: fix constant-loading for (1ULL << 31) in DImode RISC-V: bitmanip: improvements to rotate instructions RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" RISC-V: bitmanip: add orc.b as an unspec RISC-V: bitmanip: relax minmax to operate on GPR gcc/config/riscv/bitmanip.md | 74 +++++++++++++++++--- gcc/config/riscv/riscv.c | 31 ++++++++ gcc/config/riscv/riscv.h | 11 ++- gcc/config/riscv/riscv.md | 3 + gcc/optabs.c | 6 ++ gcc/testsuite/gcc.target/riscv/zbb-bswap.c | 22 ++++++ gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 20 +++++- gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++ 8 files changed, 162 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-bswap.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c