[v2,1/5] aarch64: Create definitions for AARCH64_RA_SIGN_STATE register
Commit Message
From: German Gomez <german.gomez@arm.com>
This register will be used to indicate whether a return address is
mangled with a PAC or not, in accordance with the DWARF AARCH64 ABI [1].
[1] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#41dwarf-register-names
Signed-off-by: German Gomez <german.gomez@arm.com>
[SteveC: move DW_AARCH64_RA_SIGN_STATE to cfi.h, fix comments]
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
backends/aarch64_initreg.c | 2 ++
backends/aarch64_regs.c | 5 ++++-
libdw/cfi.h | 5 +++++
tests/run-addrcfi.sh | 1 +
tests/run-allregs.sh | 1 +
5 files changed, 13 insertions(+), 1 deletion(-)
@@ -73,6 +73,8 @@ aarch64_set_initial_registers_tid (pid_t tid __attribute__ ((unused)),
/* ELR cannot be found. */
+ /* RA_SIGN_STATE cannot be found */
+
/* FP registers (only 64bits are used). */
struct user_fpsimd_struct fregs;
iovec.iov_base = &fregs;
@@ -87,7 +87,10 @@ aarch64_register_info (Ebl *ebl __attribute__ ((unused)),
case 33:
return regtype ("integer", DW_ATE_address, "elr");
- case 34 ... 63:
+ case 34:
+ return regtype ("integer", DW_ATE_unsigned, "ra_sign_state");
+
+ case 35 ... 63:
return 0;
case 64 ... 95:
@@ -228,6 +228,11 @@ extern int __libdw_frame_at_address (Dwarf_CFI *cache, struct dwarf_fde *fde,
{ ((BYTE_ORDER == LITTLE_ENDIAN && e_ident[EI_DATA] == ELFDATA2MSB) \
|| (BYTE_ORDER == BIG_ENDIAN && e_ident[EI_DATA] == ELFDATA2LSB)) }
+/* AARCH64 DWARF registers. */
+enum
+ {
+ DW_AARCH64_RA_SIGN_STATE = 34
+ };
INTDECL (dwarf_next_cfi)
INTDECL (dwarf_getcfi)
@@ -3639,6 +3639,7 @@ dwarf_cfi_addrframe (.eh_frame): no matching address range
integer reg30 (x30): same_value
integer reg31 (sp): location expression: call_frame_cfa stack_value
integer reg33 (elr): undefined
+ integer reg34 (ra_sign_state): undefined
FP/SIMD reg64 (v0): undefined
FP/SIMD reg65 (v1): undefined
FP/SIMD reg66 (v2): undefined
@@ -2693,6 +2693,7 @@ integer registers:
30: x30 (x30), signed 64 bits
31: sp (sp), address 64 bits
33: elr (elr), address 64 bits
+ 34: ra_sign_state (ra_sign_state), unsigned 64 bits
FP/SIMD registers:
64: v0 (v0), unsigned 128 bits
65: v1 (v1), unsigned 128 bits