[1/3] AArch64: Refactor system register data

Message ID yw8jo7icrhd3.fsf@e125768.cambridge.arm.com
State Superseded
Headers
Series aarch64: standardize system register representation |

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Commit Message

Victor Do Nascimento Sept. 8, 2023, 12:15 p.m. UTC
  This patch  moves instances of system register definitions, represented
by the SYSREG macro, out of their original place in `aarch64-opc.c'
and into a dedicated .def file, `aarch64-system-regs.def'.

System register entries in this new file are ordered alphabetically by
name.  This choice is made to enable the use of fast search algorithms
such as binary search when validating register names.

The SYSREG macro, defined as SYSREG (name, encoding, flags, features)
is kept as is and used in the def file, but all other SR_* macros
which previously served as indirections to SYSREG are removed.

include/ChangeLog:
	* opcode/aarch64.h (AARCH64_FEATURE_CORE): New.

opcodes/ChangeLog:
	* aarch64-opc.c (SR_CORE): Macro definition and uses deleted.
	(SR_FEAT): Likewise.
	(SR_FEAT2): Likewise.
	(SR_V8_1_A): Likewise.
	(SR_V8_4_A): Likewise.
	(SR_V8A): Likewise.
	(SR_V8R): Likewise.
	(SR_V8_1A): Likewise.
	(SR_V8_2A): Likewise.
	(SR_V8_3A): Likewise.
	(SR_V8_4A): Likewise.
	(SR_V8_6A): Likewise.
	(SR_V8_7A): Likewise.
	(SR_V8_8A): Likewise.
	(SR_GIC): Likewise.
	(SR_AMU): Likewise.
	(SR_LOR): Likewise.
	(SR_PAN): Likewise.
	(SR_RAS): Likewise.
	(SR_RNG): Likewise.
	(SR_SME): Likewise.
	(SR_SSBS): Likewise.
	(SR_SVE): Likewise.
	(SR_ID_PFR2): Likewise.
	(SR_PROFILE): Likewise.
	(SR_MEMTAG): Likewise.
	(SR_SCXTNUM): Likewise.
	(SR_EXPAND_ELx): Likewise.
	(SR_EXPAND_EL12): Likewise.
	(FEAT): New
	* opcodes/aarch64-system-regs.def: New.
---
 include/opcode/aarch64.h        |    1 +
 opcodes/aarch64-opc.c           | 1091 +------------------------------
 opcodes/aarch64-system-regs.def | 1059 ++++++++++++++++++++++++++++++
 3 files changed, 1080 insertions(+), 1071 deletions(-)
 create mode 100644 opcodes/aarch64-system-regs.def


2.41.0
  

Comments

Victor Do Nascimento Sept. 26, 2023, 10:03 a.m. UTC | #1
Gentle reminder of review request for this patch, together with parts 2 & 3.

https://sourceware.org/pipermail/binutils/2023-September/129426.html
https://sourceware.org/pipermail/binutils/2023-September/129427.html
https://sourceware.org/pipermail/binutils/2023-September/129428.html

Patch series tested and regression-free.

Many thanks,
Victor

On 9/8/23 13:15, Victor L. Do Nascimento via Binutils wrote:
> 
> This patch  moves instances of system register definitions, represented
> by the SYSREG macro, out of their original place in `aarch64-opc.c'
> and into a dedicated .def file, `aarch64-system-regs.def'.
> 
> System register entries in this new file are ordered alphabetically by
> name.  This choice is made to enable the use of fast search algorithms
> such as binary search when validating register names.
> 
> The SYSREG macro, defined as SYSREG (name, encoding, flags, features)
> is kept as is and used in the def file, but all other SR_* macros
> which previously served as indirections to SYSREG are removed.
> 
> include/ChangeLog:
> 	* opcode/aarch64.h (AARCH64_FEATURE_CORE): New.
> 
> opcodes/ChangeLog:
> 	* aarch64-opc.c (SR_CORE): Macro definition and uses deleted.
> 	(SR_FEAT): Likewise.
> 	(SR_FEAT2): Likewise.
> 	(SR_V8_1_A): Likewise.
> 	(SR_V8_4_A): Likewise.
> 	(SR_V8A): Likewise.
> 	(SR_V8R): Likewise.
> 	(SR_V8_1A): Likewise.
> 	(SR_V8_2A): Likewise.
> 	(SR_V8_3A): Likewise.
> 	(SR_V8_4A): Likewise.
> 	(SR_V8_6A): Likewise.
> 	(SR_V8_7A): Likewise.
> 	(SR_V8_8A): Likewise.
> 	(SR_GIC): Likewise.
> 	(SR_AMU): Likewise.
> 	(SR_LOR): Likewise.
> 	(SR_PAN): Likewise.
> 	(SR_RAS): Likewise.
> 	(SR_RNG): Likewise.
> 	(SR_SME): Likewise.
> 	(SR_SSBS): Likewise.
> 	(SR_SVE): Likewise.
> 	(SR_ID_PFR2): Likewise.
> 	(SR_PROFILE): Likewise.
> 	(SR_MEMTAG): Likewise.
> 	(SR_SCXTNUM): Likewise.
> 	(SR_EXPAND_ELx): Likewise.
> 	(SR_EXPAND_EL12): Likewise.
> 	(FEAT): New
> 	* opcodes/aarch64-system-regs.def: New.
> ---
>   include/opcode/aarch64.h        |    1 +
>   opcodes/aarch64-opc.c           | 1091 +------------------------------
>   opcodes/aarch64-system-regs.def | 1059 ++++++++++++++++++++++++++++++
>   3 files changed, 1080 insertions(+), 1071 deletions(-)
>   create mode 100644 opcodes/aarch64-system-regs.def
> 
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 381934ab39b..4cd0ac70a13 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -39,6 +39,7 @@ extern "C" {
>   typedef uint32_t aarch64_insn;
>   
>   /* The following bitmasks control CPU features.  */
> +#define AARCH64_FEATURE_CORE	     (0ULL << 0) /*All processors.  */
>   #define AARCH64_FEATURE_V8	     (1ULL << 0) /* All processors.  */
>   #define AARCH64_FEATURE_V8_6A	     (1ULL << 1) /* ARMv8.6 processors.  */
>   #define AARCH64_FEATURE_BFLOAT16     (1ULL << 2) /* Bfloat16 insns.  */
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index 41dec5cdc04..e3f0ed13de0 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -4674,67 +4674,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
>   #define C14 14
>   #define C15 15
>   
> -#define SYSREG(name, encoding, flags, features) \
> -  { name, encoding, flags, features }
> -
> -#define SR_CORE(n,e,f) SYSREG (n,e,f,0)
> -
> -#define SR_FEAT(n,e,f,feat) \
> -  SYSREG ((n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE_##feat)
> -
> -#define SR_FEAT2(n,e,f,fe1,fe2) \
> -  SYSREG ((n), (e), (f) | F_ARCHEXT, \
> -	  AARCH64_FEATURE_##fe1 | AARCH64_FEATURE_##fe2)
> -
> -#define SR_V8_1_A(n,e,f) SR_FEAT2(n,e,f,V8A,V8_1A)
> -#define SR_V8_4_A(n,e,f) SR_FEAT2(n,e,f,V8A,V8_4A)
> -
> -#define SR_V8A(n,e,f)	  SR_FEAT (n,e,f,V8A)
> -#define SR_V8R(n,e,f)	  SR_FEAT (n,e,f,V8R)
> -#define SR_V8_1A(n,e,f)	  SR_FEAT (n,e,f,V8_1A)
> -#define SR_V8_2A(n,e,f)	  SR_FEAT (n,e,f,V8_2A)
> -#define SR_V8_3A(n,e,f)	  SR_FEAT (n,e,f,V8_3A)
> -#define SR_V8_4A(n,e,f)	  SR_FEAT (n,e,f,V8_4A)
> -#define SR_V8_6A(n,e,f)	  SR_FEAT (n,e,f,V8_6A)
> -#define SR_V8_7A(n,e,f)	  SR_FEAT (n,e,f,V8_7A)
> -#define SR_V8_8A(n,e,f)	  SR_FEAT (n,e,f,V8_8A)
> -/* Has no separate libopcodes feature flag, but separated out for clarity.  */
> -#define SR_GIC(n,e,f)	  SR_CORE (n,e,f)
> -/* Has no separate libopcodes feature flag, but separated out for clarity.  */
> -#define SR_AMU(n,e,f)	  SR_FEAT (n,e,f,V8_4A)
> -#define SR_LOR(n,e,f)	  SR_FEAT (n,e,f,LOR)
> -#define SR_PAN(n,e,f)	  SR_FEAT (n,e,f,PAN)
> -#define SR_RAS(n,e,f)	  SR_FEAT (n,e,f,RAS)
> -#define SR_RNG(n,e,f)	  SR_FEAT (n,e,f,RNG)
> -#define SR_SME(n,e,f)	  SR_FEAT (n,e,f,SME)
> -#define SR_SSBS(n,e,f)	  SR_FEAT (n,e,f,SSBS)
> -#define SR_SVE(n,e,f)	  SR_FEAT (n,e,f,SVE)
> -#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2)
> -#define SR_PROFILE(n,e,f) SR_FEAT (n,e,f,PROFILE)
> -#define SR_MEMTAG(n,e,f)  SR_FEAT (n,e,f,MEMTAG)
> -#define SR_SCXTNUM(n,e,f) SR_FEAT (n,e,f,SCXTNUM)
> -
> -#define SR_EXPAND_ELx(f,x) \
> -  f (x, 1),  \
> -  f (x, 2),  \
> -  f (x, 3),  \
> -  f (x, 4),  \
> -  f (x, 5),  \
> -  f (x, 6),  \
> -  f (x, 7),  \
> -  f (x, 8),  \
> -  f (x, 9),  \
> -  f (x, 10), \
> -  f (x, 11), \
> -  f (x, 12), \
> -  f (x, 13), \
> -  f (x, 14), \
> -  f (x, 15),
> -
> -#define SR_EXPAND_EL12(f) \
> -  SR_EXPAND_ELx (f,1) \
> -  SR_EXPAND_ELx (f,2)
> -
>   /* TODO there is one more issues need to be resolved
>      1. handle cpu-implementation-defined system registers.
>   
> @@ -4742,1001 +4681,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
>      respectively.  If neither of these are set then the register is read-write.  */
>   const aarch64_sys_reg aarch64_sys_regs [] =
>   {
> -  SR_CORE ("spsr_el1",		CPEN_ (0,C0,0),		0), /* = spsr_svc.  */
> -  SR_V8_1A ("spsr_el12",		CPEN_ (5,C0,0),		0),
> -  SR_CORE ("elr_el1",		CPEN_ (0,C0,1),		0),
> -  SR_V8_1A ("elr_el12",		CPEN_ (5,C0,1),		0),
> -  SR_CORE ("sp_el0",		CPEN_ (0,C1,0),		0),
> -  SR_CORE ("spsel",		CPEN_ (0,C2,0),		0),
> -  SR_CORE ("daif",		CPEN_ (3,C2,1),		0),
> -  SR_CORE ("currentel",		CPEN_ (0,C2,2),		F_REG_READ),
> -  SR_PAN  ("pan",		CPEN_ (0,C2,3),		0),
> -  SR_V8_2A ("uao",		CPEN_ (0,C2,4),		0),
> -  SR_CORE ("nzcv",		CPEN_ (3,C2,0),		0),
> -  SR_SSBS ("ssbs",		CPEN_ (3,C2,6),		0),
> -  SR_CORE ("fpcr",		CPEN_ (3,C4,0),		0),
> -  SR_CORE ("fpsr",		CPEN_ (3,C4,1),		0),
> -  SR_CORE ("dspsr_el0",		CPEN_ (3,C5,0),		0),
> -  SR_CORE ("dlr_el0",		CPEN_ (3,C5,1),		0),
> -  SR_CORE ("spsr_el2",		CPEN_ (4,C0,0),		0), /* = spsr_hyp.  */
> -  SR_CORE ("elr_el2",		CPEN_ (4,C0,1),		0),
> -  SR_CORE ("sp_el1",		CPEN_ (4,C1,0),		0),
> -  SR_CORE ("spsr_irq",		CPEN_ (4,C3,0),		0),
> -  SR_CORE ("spsr_abt",		CPEN_ (4,C3,1),		0),
> -  SR_CORE ("spsr_und",		CPEN_ (4,C3,2),		0),
> -  SR_CORE ("spsr_fiq",		CPEN_ (4,C3,3),		0),
> -  SR_CORE ("spsr_el3",		CPEN_ (6,C0,0),		0),
> -  SR_CORE ("elr_el3",		CPEN_ (6,C0,1),		0),
> -  SR_CORE ("sp_el2",		CPEN_ (6,C1,0),		0),
> -  SR_CORE ("spsr_svc",		CPEN_ (0,C0,0),		F_DEPRECATED), /* = spsr_el1.  */
> -  SR_CORE ("spsr_hyp",		CPEN_ (4,C0,0),		F_DEPRECATED), /* = spsr_el2.  */
> -  SR_CORE ("midr_el1",		CPENC (3,0,C0,C0,0),	F_REG_READ),
> -  SR_CORE ("ctr_el0",		CPENC (3,3,C0,C0,1),	F_REG_READ),
> -  SR_CORE ("mpidr_el1",		CPENC (3,0,C0,C0,5),	F_REG_READ),
> -  SR_CORE ("revidr_el1",	CPENC (3,0,C0,C0,6),	F_REG_READ),
> -  SR_CORE ("aidr_el1",		CPENC (3,1,C0,C0,7),	F_REG_READ),
> -  SR_CORE ("dczid_el0",		CPENC (3,3,C0,C0,7),	F_REG_READ),
> -  SR_CORE ("id_dfr0_el1",	CPENC (3,0,C0,C1,2),	F_REG_READ),
> -  SR_CORE ("id_dfr1_el1",	CPENC (3,0,C0,C3,5),	F_REG_READ),
> -  SR_CORE ("id_pfr0_el1",	CPENC (3,0,C0,C1,0),	F_REG_READ),
> -  SR_CORE ("id_pfr1_el1",	CPENC (3,0,C0,C1,1),	F_REG_READ),
> -  SR_ID_PFR2 ("id_pfr2_el1",	CPENC (3,0,C0,C3,4),	F_REG_READ),
> -  SR_CORE ("id_afr0_el1",	CPENC (3,0,C0,C1,3),	F_REG_READ),
> -  SR_CORE ("id_mmfr0_el1",	CPENC (3,0,C0,C1,4),	F_REG_READ),
> -  SR_CORE ("id_mmfr1_el1",	CPENC (3,0,C0,C1,5),	F_REG_READ),
> -  SR_CORE ("id_mmfr2_el1",	CPENC (3,0,C0,C1,6),	F_REG_READ),
> -  SR_CORE ("id_mmfr3_el1",	CPENC (3,0,C0,C1,7),	F_REG_READ),
> -  SR_CORE ("id_mmfr4_el1",	CPENC (3,0,C0,C2,6),	F_REG_READ),
> -  SR_CORE ("id_mmfr5_el1",	CPENC (3,0,C0,C3,6),	F_REG_READ),
> -  SR_CORE ("id_isar0_el1",	CPENC (3,0,C0,C2,0),	F_REG_READ),
> -  SR_CORE ("id_isar1_el1",	CPENC (3,0,C0,C2,1),	F_REG_READ),
> -  SR_CORE ("id_isar2_el1",	CPENC (3,0,C0,C2,2),	F_REG_READ),
> -  SR_CORE ("id_isar3_el1",	CPENC (3,0,C0,C2,3),	F_REG_READ),
> -  SR_CORE ("id_isar4_el1",	CPENC (3,0,C0,C2,4),	F_REG_READ),
> -  SR_CORE ("id_isar5_el1",	CPENC (3,0,C0,C2,5),	F_REG_READ),
> -  SR_CORE ("id_isar6_el1",	CPENC (3,0,C0,C2,7),	F_REG_READ),
> -  SR_CORE ("mvfr0_el1",		CPENC (3,0,C0,C3,0),	F_REG_READ),
> -  SR_CORE ("mvfr1_el1",		CPENC (3,0,C0,C3,1),	F_REG_READ),
> -  SR_CORE ("mvfr2_el1",		CPENC (3,0,C0,C3,2),	F_REG_READ),
> -  SR_CORE ("ccsidr_el1",	CPENC (3,1,C0,C0,0),	F_REG_READ),
> -  SR_V8_3A ("ccsidr2_el1",       CPENC (3,1,C0,C0,2),    F_REG_READ),
> -  SR_CORE ("id_aa64pfr0_el1",	CPENC (3,0,C0,C4,0),	F_REG_READ),
> -  SR_CORE ("id_aa64pfr1_el1",	CPENC (3,0,C0,C4,1),	F_REG_READ),
> -  SR_CORE ("id_aa64dfr0_el1",	CPENC (3,0,C0,C5,0),	F_REG_READ),
> -  SR_CORE ("id_aa64dfr1_el1",	CPENC (3,0,C0,C5,1),	F_REG_READ),
> -  SR_CORE ("id_aa64isar0_el1",	CPENC (3,0,C0,C6,0),	F_REG_READ),
> -  SR_CORE ("id_aa64isar1_el1",	CPENC (3,0,C0,C6,1),	F_REG_READ),
> -  SR_CORE ("id_aa64isar2_el1",	CPENC (3,0,C0,C6,2),	F_REG_READ),
> -  SR_CORE ("id_aa64mmfr0_el1",	CPENC (3,0,C0,C7,0),	F_REG_READ),
> -  SR_CORE ("id_aa64mmfr1_el1",	CPENC (3,0,C0,C7,1),	F_REG_READ),
> -  SR_CORE ("id_aa64mmfr2_el1",	CPENC (3,0,C0,C7,2),	F_REG_READ),
> -  SR_CORE ("id_aa64afr0_el1",	CPENC (3,0,C0,C5,4),	F_REG_READ),
> -  SR_CORE ("id_aa64afr1_el1",	CPENC (3,0,C0,C5,5),	F_REG_READ),
> -  SR_SVE  ("id_aa64zfr0_el1",	CPENC (3,0,C0,C4,4),	F_REG_READ),
> -  SR_CORE ("clidr_el1",		CPENC (3,1,C0,C0,1),	F_REG_READ),
> -  SR_CORE ("csselr_el1",	CPENC (3,2,C0,C0,0),	0),
> -  SR_CORE ("vpidr_el2",		CPENC (3,4,C0,C0,0),	0),
> -  SR_CORE ("vmpidr_el2",	CPENC (3,4,C0,C0,5),	0),
> -  SR_CORE ("sctlr_el1",		CPENC (3,0,C1,C0,0),	0),
> -  SR_CORE ("sctlr_el2",		CPENC (3,4,C1,C0,0),	0),
> -  SR_CORE ("sctlr_el3",		CPENC (3,6,C1,C0,0),	0),
> -  SR_V8_1A ("sctlr_el12",	CPENC (3,5,C1,C0,0),	0),
> -  SR_CORE ("actlr_el1",		CPENC (3,0,C1,C0,1),	0),
> -  SR_CORE ("actlr_el2",		CPENC (3,4,C1,C0,1),	0),
> -  SR_CORE ("actlr_el3",		CPENC (3,6,C1,C0,1),	0),
> -  SR_CORE ("cpacr_el1",		CPENC (3,0,C1,C0,2),	0),
> -  SR_V8_1A ("cpacr_el12",	CPENC (3,5,C1,C0,2),	0),
> -  SR_CORE ("cptr_el2",		CPENC (3,4,C1,C1,2),	0),
> -  SR_CORE ("cptr_el3",		CPENC (3,6,C1,C1,2),	0),
> -  SR_CORE ("scr_el3",		CPENC (3,6,C1,C1,0),	0),
> -  SR_CORE ("hcr_el2",		CPENC (3,4,C1,C1,0),	0),
> -  SR_CORE ("mdcr_el2",		CPENC (3,4,C1,C1,1),	0),
> -  SR_CORE ("mdcr_el3",		CPENC (3,6,C1,C3,1),	0),
> -  SR_CORE ("hstr_el2",		CPENC (3,4,C1,C1,3),	0),
> -  SR_CORE ("hacr_el2",		CPENC (3,4,C1,C1,7),	0),
> -  SR_SVE  ("zcr_el1",		CPENC (3,0,C1,C2,0),	0),
> -  SR_SVE  ("zcr_el12",		CPENC (3,5,C1,C2,0),	0),
> -  SR_SVE  ("zcr_el2",		CPENC (3,4,C1,C2,0),	0),
> -  SR_SVE  ("zcr_el3",		CPENC (3,6,C1,C2,0),	0),
> -  SR_CORE ("ttbr0_el1",		CPENC (3,0,C2,C0,0),	0),
> -  SR_CORE ("ttbr1_el1",		CPENC (3,0,C2,C0,1),	0),
> -  SR_V8A ("ttbr0_el2",		CPENC (3,4,C2,C0,0),	0),
> -  SR_V8_1_A ("ttbr1_el2",	CPENC (3,4,C2,C0,1),	0),
> -  SR_CORE ("ttbr0_el3",		CPENC (3,6,C2,C0,0),	0),
> -  SR_V8_1A ("ttbr0_el12",	CPENC (3,5,C2,C0,0),	0),
> -  SR_V8_1A ("ttbr1_el12",	CPENC (3,5,C2,C0,1),	0),
> -  SR_V8A ("vttbr_el2",		CPENC (3,4,C2,C1,0),	0),
> -  SR_CORE ("tcr_el1",		CPENC (3,0,C2,C0,2),	0),
> -  SR_CORE ("tcr_el2",		CPENC (3,4,C2,C0,2),	0),
> -  SR_CORE ("tcr_el3",		CPENC (3,6,C2,C0,2),	0),
> -  SR_V8_1A ("tcr_el12",		CPENC (3,5,C2,C0,2),	0),
> -  SR_CORE ("vtcr_el2",		CPENC (3,4,C2,C1,2),	0),
> -  SR_V8_3A ("apiakeylo_el1",	CPENC (3,0,C2,C1,0),	0),
> -  SR_V8_3A ("apiakeyhi_el1",	CPENC (3,0,C2,C1,1),	0),
> -  SR_V8_3A ("apibkeylo_el1",	CPENC (3,0,C2,C1,2),	0),
> -  SR_V8_3A ("apibkeyhi_el1",	CPENC (3,0,C2,C1,3),	0),
> -  SR_V8_3A ("apdakeylo_el1",	CPENC (3,0,C2,C2,0),	0),
> -  SR_V8_3A ("apdakeyhi_el1",	CPENC (3,0,C2,C2,1),	0),
> -  SR_V8_3A ("apdbkeylo_el1",	CPENC (3,0,C2,C2,2),	0),
> -  SR_V8_3A ("apdbkeyhi_el1",	CPENC (3,0,C2,C2,3),	0),
> -  SR_V8_3A ("apgakeylo_el1",	CPENC (3,0,C2,C3,0),	0),
> -  SR_V8_3A ("apgakeyhi_el1",	CPENC (3,0,C2,C3,1),	0),
> -  SR_CORE ("afsr0_el1",		CPENC (3,0,C5,C1,0),	0),
> -  SR_CORE ("afsr1_el1",		CPENC (3,0,C5,C1,1),	0),
> -  SR_CORE ("afsr0_el2",		CPENC (3,4,C5,C1,0),	0),
> -  SR_CORE ("afsr1_el2",		CPENC (3,4,C5,C1,1),	0),
> -  SR_CORE ("afsr0_el3",		CPENC (3,6,C5,C1,0),	0),
> -  SR_V8_1A ("afsr0_el12",	CPENC (3,5,C5,C1,0),	0),
> -  SR_CORE ("afsr1_el3",		CPENC (3,6,C5,C1,1),	0),
> -  SR_V8_1A ("afsr1_el12",	CPENC (3,5,C5,C1,1),	0),
> -  SR_CORE ("esr_el1",		CPENC (3,0,C5,C2,0),	0),
> -  SR_CORE ("esr_el2",		CPENC (3,4,C5,C2,0),	0),
> -  SR_CORE ("esr_el3",		CPENC (3,6,C5,C2,0),	0),
> -  SR_V8_1A ("esr_el12",		CPENC (3,5,C5,C2,0),	0),
> -  SR_RAS  ("vsesr_el2",		CPENC (3,4,C5,C2,3),	0),
> -  SR_CORE ("fpexc32_el2",	CPENC (3,4,C5,C3,0),	0),
> -  SR_RAS  ("erridr_el1",	CPENC (3,0,C5,C3,0),	F_REG_READ),
> -  SR_RAS  ("errselr_el1",	CPENC (3,0,C5,C3,1),	0),
> -  SR_RAS  ("erxfr_el1",		CPENC (3,0,C5,C4,0),	F_REG_READ),
> -  SR_RAS  ("erxctlr_el1",	CPENC (3,0,C5,C4,1),	0),
> -  SR_RAS  ("erxstatus_el1",	CPENC (3,0,C5,C4,2),	0),
> -  SR_RAS  ("erxaddr_el1",	CPENC (3,0,C5,C4,3),	0),
> -  SR_RAS  ("erxmisc0_el1",	CPENC (3,0,C5,C5,0),	0),
> -  SR_RAS  ("erxmisc1_el1",	CPENC (3,0,C5,C5,1),	0),
> -  SR_RAS  ("erxmisc2_el1",	CPENC (3,0,C5,C5,2),	0),
> -  SR_RAS  ("erxmisc3_el1",	CPENC (3,0,C5,C5,3),	0),
> -  SR_RAS  ("erxpfgcdn_el1",	CPENC (3,0,C5,C4,6),	0),
> -  SR_RAS  ("erxpfgctl_el1",	CPENC (3,0,C5,C4,5),	0),
> -  SR_RAS  ("erxpfgf_el1",	CPENC (3,0,C5,C4,4),	F_REG_READ),
> -  SR_CORE ("far_el1",		CPENC (3,0,C6,C0,0),	0),
> -  SR_CORE ("far_el2",		CPENC (3,4,C6,C0,0),	0),
> -  SR_CORE ("far_el3",		CPENC (3,6,C6,C0,0),	0),
> -  SR_V8_1A ("far_el12",		CPENC (3,5,C6,C0,0),	0),
> -  SR_CORE ("hpfar_el2",		CPENC (3,4,C6,C0,4),	0),
> -  SR_CORE ("par_el1",		CPENC (3,0,C7,C4,0),	0),
> -  SR_CORE ("mair_el1",		CPENC (3,0,C10,C2,0),	0),
> -  SR_CORE ("mair_el2",		CPENC (3,4,C10,C2,0),	0),
> -  SR_CORE ("mair_el3",		CPENC (3,6,C10,C2,0),	0),
> -  SR_V8_1A ("mair_el12",		CPENC (3,5,C10,C2,0),	0),
> -  SR_CORE ("amair_el1",		CPENC (3,0,C10,C3,0),	0),
> -  SR_CORE ("amair_el2",		CPENC (3,4,C10,C3,0),	0),
> -  SR_CORE ("amair_el3",		CPENC (3,6,C10,C3,0),	0),
> -  SR_V8_1A ("amair_el12",	CPENC (3,5,C10,C3,0),	0),
> -  SR_CORE ("vbar_el1",		CPENC (3,0,C12,C0,0),	0),
> -  SR_CORE ("vbar_el2",		CPENC (3,4,C12,C0,0),	0),
> -  SR_CORE ("vbar_el3",		CPENC (3,6,C12,C0,0),	0),
> -  SR_V8_1A ("vbar_el12",		CPENC (3,5,C12,C0,0),	0),
> -  SR_CORE ("rvbar_el1",		CPENC (3,0,C12,C0,1),	F_REG_READ),
> -  SR_CORE ("rvbar_el2",		CPENC (3,4,C12,C0,1),	F_REG_READ),
> -  SR_CORE ("rvbar_el3",		CPENC (3,6,C12,C0,1),	F_REG_READ),
> -  SR_CORE ("rmr_el1",		CPENC (3,0,C12,C0,2),	0),
> -  SR_CORE ("rmr_el2",		CPENC (3,4,C12,C0,2),	0),
> -  SR_CORE ("rmr_el3",		CPENC (3,6,C12,C0,2),	0),
> -  SR_CORE ("isr_el1",		CPENC (3,0,C12,C1,0),	F_REG_READ),
> -  SR_RAS  ("disr_el1",		CPENC (3,0,C12,C1,1),	0),
> -  SR_RAS  ("vdisr_el2",		CPENC (3,4,C12,C1,1),	0),
> -  SR_CORE ("contextidr_el1",	CPENC (3,0,C13,C0,1),	0),
> -  SR_V8_1A ("contextidr_el2",	CPENC (3,4,C13,C0,1),	0),
> -  SR_V8_1A ("contextidr_el12",	CPENC (3,5,C13,C0,1),	0),
> -  SR_RNG  ("rndr",		CPENC (3,3,C2,C4,0),	F_REG_READ),
> -  SR_RNG  ("rndrrs",		CPENC (3,3,C2,C4,1),	F_REG_READ),
> -  SR_MEMTAG ("tco",		CPENC (3,3,C4,C2,7),	0),
> -  SR_MEMTAG ("tfsre0_el1",	CPENC (3,0,C5,C6,1),	0),
> -  SR_MEMTAG ("tfsr_el1",	CPENC (3,0,C5,C6,0),	0),
> -  SR_MEMTAG ("tfsr_el2",	CPENC (3,4,C5,C6,0),	0),
> -  SR_MEMTAG ("tfsr_el3",	CPENC (3,6,C5,C6,0),	0),
> -  SR_MEMTAG ("tfsr_el12",	CPENC (3,5,C5,C6,0),	0),
> -  SR_MEMTAG ("rgsr_el1",	CPENC (3,0,C1,C0,5),	0),
> -  SR_MEMTAG ("gcr_el1",		CPENC (3,0,C1,C0,6),	0),
> -  SR_MEMTAG ("gmid_el1",	CPENC (3,1,C0,C0,4),	F_REG_READ),
> -  SR_CORE ("tpidr_el0",		CPENC (3,3,C13,C0,2),	0),
> -  SR_CORE ("tpidrro_el0",       CPENC (3,3,C13,C0,3),	0),
> -  SR_CORE ("tpidr_el1",		CPENC (3,0,C13,C0,4),	0),
> -  SR_CORE ("tpidr_el2",		CPENC (3,4,C13,C0,2),	0),
> -  SR_CORE ("tpidr_el3",		CPENC (3,6,C13,C0,2),	0),
> -  SR_SCXTNUM ("scxtnum_el0",	CPENC (3,3,C13,C0,7),	0),
> -  SR_SCXTNUM ("scxtnum_el1",	CPENC (3,0,C13,C0,7),	0),
> -  SR_SCXTNUM ("scxtnum_el2",	CPENC (3,4,C13,C0,7),	0),
> -  SR_SCXTNUM ("scxtnum_el12",   CPENC (3,5,C13,C0,7),	0),
> -  SR_SCXTNUM ("scxtnum_el3",    CPENC (3,6,C13,C0,7),	0),
> -  SR_CORE ("teecr32_el1",       CPENC (2,2,C0, C0,0),	0), /* See section 3.9.7.1.  */
> -  SR_CORE ("cntfrq_el0",	CPENC (3,3,C14,C0,0),	0),
> -  SR_CORE ("cntpct_el0",	CPENC (3,3,C14,C0,1),	F_REG_READ),
> -  SR_CORE ("cntvct_el0",	CPENC (3,3,C14,C0,2),	F_REG_READ),
> -  SR_CORE ("cntvoff_el2",       CPENC (3,4,C14,C0,3),	0),
> -  SR_CORE ("cntkctl_el1",       CPENC (3,0,C14,C1,0),	0),
> -  SR_V8_1A ("cntkctl_el12",	CPENC (3,5,C14,C1,0),	0),
> -  SR_CORE ("cnthctl_el2",	CPENC (3,4,C14,C1,0),	0),
> -  SR_CORE ("cntp_tval_el0",	CPENC (3,3,C14,C2,0),	0),
> -  SR_V8_1A ("cntp_tval_el02",	CPENC (3,5,C14,C2,0),	0),
> -  SR_CORE ("cntp_ctl_el0",      CPENC (3,3,C14,C2,1),	0),
> -  SR_V8_1A ("cntp_ctl_el02",	CPENC (3,5,C14,C2,1),	0),
> -  SR_CORE ("cntp_cval_el0",     CPENC (3,3,C14,C2,2),	0),
> -  SR_V8_1A ("cntp_cval_el02",	CPENC (3,5,C14,C2,2),	0),
> -  SR_CORE ("cntv_tval_el0",     CPENC (3,3,C14,C3,0),	0),
> -  SR_V8_1A ("cntv_tval_el02",	CPENC (3,5,C14,C3,0),	0),
> -  SR_CORE ("cntv_ctl_el0",      CPENC (3,3,C14,C3,1),	0),
> -  SR_V8_1A ("cntv_ctl_el02",	CPENC (3,5,C14,C3,1),	0),
> -  SR_CORE ("cntv_cval_el0",     CPENC (3,3,C14,C3,2),	0),
> -  SR_V8_1A ("cntv_cval_el02",	CPENC (3,5,C14,C3,2),	0),
> -  SR_CORE ("cnthp_tval_el2",	CPENC (3,4,C14,C2,0),	0),
> -  SR_CORE ("cnthp_ctl_el2",	CPENC (3,4,C14,C2,1),	0),
> -  SR_CORE ("cnthp_cval_el2",	CPENC (3,4,C14,C2,2),	0),
> -  SR_CORE ("cntps_tval_el1",	CPENC (3,7,C14,C2,0),	0),
> -  SR_CORE ("cntps_ctl_el1",	CPENC (3,7,C14,C2,1),	0),
> -  SR_CORE ("cntps_cval_el1",	CPENC (3,7,C14,C2,2),	0),
> -  SR_V8_1A ("cnthv_tval_el2",	CPENC (3,4,C14,C3,0),	0),
> -  SR_V8_1A ("cnthv_ctl_el2",	CPENC (3,4,C14,C3,1),	0),
> -  SR_V8_1A ("cnthv_cval_el2",	CPENC (3,4,C14,C3,2),	0),
> -  SR_CORE ("dacr32_el2",	CPENC (3,4,C3,C0,0),	0),
> -  SR_CORE ("ifsr32_el2",	CPENC (3,4,C5,C0,1),	0),
> -  SR_CORE ("teehbr32_el1",	CPENC (2,2,C1,C0,0),	0),
> -  SR_CORE ("sder32_el3",	CPENC (3,6,C1,C1,1),	0),
> -  SR_CORE ("mdscr_el1",		CPENC (2,0,C0,C2,2),	0),
> -  SR_CORE ("mdccsr_el0",	CPENC (2,3,C0,C1,0),	F_REG_READ),
> -  SR_CORE ("mdccint_el1",       CPENC (2,0,C0,C2,0),	0),
> -  SR_CORE ("dbgdtr_el0",	CPENC (2,3,C0,C4,0),	0),
> -  SR_CORE ("dbgdtrrx_el0",	CPENC (2,3,C0,C5,0),	F_REG_READ),
> -  SR_CORE ("dbgdtrtx_el0",	CPENC (2,3,C0,C5,0),	F_REG_WRITE),
> -  SR_CORE ("osdtrrx_el1",	CPENC (2,0,C0,C0,2),	0),
> -  SR_CORE ("osdtrtx_el1",	CPENC (2,0,C0,C3,2),	0),
> -  SR_CORE ("oseccr_el1",	CPENC (2,0,C0,C6,2),	0),
> -  SR_CORE ("dbgvcr32_el2",      CPENC (2,4,C0,C7,0),	0),
> -  SR_CORE ("dbgbvr0_el1",       CPENC (2,0,C0,C0,4),	0),
> -  SR_CORE ("dbgbvr1_el1",       CPENC (2,0,C0,C1,4),	0),
> -  SR_CORE ("dbgbvr2_el1",       CPENC (2,0,C0,C2,4),	0),
> -  SR_CORE ("dbgbvr3_el1",       CPENC (2,0,C0,C3,4),	0),
> -  SR_CORE ("dbgbvr4_el1",       CPENC (2,0,C0,C4,4),	0),
> -  SR_CORE ("dbgbvr5_el1",       CPENC (2,0,C0,C5,4),	0),
> -  SR_CORE ("dbgbvr6_el1",       CPENC (2,0,C0,C6,4),	0),
> -  SR_CORE ("dbgbvr7_el1",       CPENC (2,0,C0,C7,4),	0),
> -  SR_CORE ("dbgbvr8_el1",       CPENC (2,0,C0,C8,4),	0),
> -  SR_CORE ("dbgbvr9_el1",       CPENC (2,0,C0,C9,4),	0),
> -  SR_CORE ("dbgbvr10_el1",      CPENC (2,0,C0,C10,4),	0),
> -  SR_CORE ("dbgbvr11_el1",      CPENC (2,0,C0,C11,4),	0),
> -  SR_CORE ("dbgbvr12_el1",      CPENC (2,0,C0,C12,4),	0),
> -  SR_CORE ("dbgbvr13_el1",      CPENC (2,0,C0,C13,4),	0),
> -  SR_CORE ("dbgbvr14_el1",      CPENC (2,0,C0,C14,4),	0),
> -  SR_CORE ("dbgbvr15_el1",      CPENC (2,0,C0,C15,4),	0),
> -  SR_CORE ("dbgbcr0_el1",       CPENC (2,0,C0,C0,5),	0),
> -  SR_CORE ("dbgbcr1_el1",       CPENC (2,0,C0,C1,5),	0),
> -  SR_CORE ("dbgbcr2_el1",       CPENC (2,0,C0,C2,5),	0),
> -  SR_CORE ("dbgbcr3_el1",       CPENC (2,0,C0,C3,5),	0),
> -  SR_CORE ("dbgbcr4_el1",       CPENC (2,0,C0,C4,5),	0),
> -  SR_CORE ("dbgbcr5_el1",       CPENC (2,0,C0,C5,5),	0),
> -  SR_CORE ("dbgbcr6_el1",       CPENC (2,0,C0,C6,5),	0),
> -  SR_CORE ("dbgbcr7_el1",       CPENC (2,0,C0,C7,5),	0),
> -  SR_CORE ("dbgbcr8_el1",       CPENC (2,0,C0,C8,5),	0),
> -  SR_CORE ("dbgbcr9_el1",       CPENC (2,0,C0,C9,5),	0),
> -  SR_CORE ("dbgbcr10_el1",      CPENC (2,0,C0,C10,5),	0),
> -  SR_CORE ("dbgbcr11_el1",      CPENC (2,0,C0,C11,5),	0),
> -  SR_CORE ("dbgbcr12_el1",      CPENC (2,0,C0,C12,5),	0),
> -  SR_CORE ("dbgbcr13_el1",      CPENC (2,0,C0,C13,5),	0),
> -  SR_CORE ("dbgbcr14_el1",      CPENC (2,0,C0,C14,5),	0),
> -  SR_CORE ("dbgbcr15_el1",      CPENC (2,0,C0,C15,5),	0),
> -  SR_CORE ("dbgwvr0_el1",       CPENC (2,0,C0,C0,6),	0),
> -  SR_CORE ("dbgwvr1_el1",       CPENC (2,0,C0,C1,6),	0),
> -  SR_CORE ("dbgwvr2_el1",       CPENC (2,0,C0,C2,6),	0),
> -  SR_CORE ("dbgwvr3_el1",       CPENC (2,0,C0,C3,6),	0),
> -  SR_CORE ("dbgwvr4_el1",       CPENC (2,0,C0,C4,6),	0),
> -  SR_CORE ("dbgwvr5_el1",       CPENC (2,0,C0,C5,6),	0),
> -  SR_CORE ("dbgwvr6_el1",       CPENC (2,0,C0,C6,6),	0),
> -  SR_CORE ("dbgwvr7_el1",       CPENC (2,0,C0,C7,6),	0),
> -  SR_CORE ("dbgwvr8_el1",       CPENC (2,0,C0,C8,6),	0),
> -  SR_CORE ("dbgwvr9_el1",       CPENC (2,0,C0,C9,6),	0),
> -  SR_CORE ("dbgwvr10_el1",      CPENC (2,0,C0,C10,6),	0),
> -  SR_CORE ("dbgwvr11_el1",      CPENC (2,0,C0,C11,6),	0),
> -  SR_CORE ("dbgwvr12_el1",      CPENC (2,0,C0,C12,6),	0),
> -  SR_CORE ("dbgwvr13_el1",      CPENC (2,0,C0,C13,6),	0),
> -  SR_CORE ("dbgwvr14_el1",      CPENC (2,0,C0,C14,6),	0),
> -  SR_CORE ("dbgwvr15_el1",      CPENC (2,0,C0,C15,6),	0),
> -  SR_CORE ("dbgwcr0_el1",       CPENC (2,0,C0,C0,7),	0),
> -  SR_CORE ("dbgwcr1_el1",       CPENC (2,0,C0,C1,7),	0),
> -  SR_CORE ("dbgwcr2_el1",       CPENC (2,0,C0,C2,7),	0),
> -  SR_CORE ("dbgwcr3_el1",       CPENC (2,0,C0,C3,7),	0),
> -  SR_CORE ("dbgwcr4_el1",       CPENC (2,0,C0,C4,7),	0),
> -  SR_CORE ("dbgwcr5_el1",       CPENC (2,0,C0,C5,7),	0),
> -  SR_CORE ("dbgwcr6_el1",       CPENC (2,0,C0,C6,7),	0),
> -  SR_CORE ("dbgwcr7_el1",       CPENC (2,0,C0,C7,7),	0),
> -  SR_CORE ("dbgwcr8_el1",       CPENC (2,0,C0,C8,7),	0),
> -  SR_CORE ("dbgwcr9_el1",       CPENC (2,0,C0,C9,7),	0),
> -  SR_CORE ("dbgwcr10_el1",      CPENC (2,0,C0,C10,7),	0),
> -  SR_CORE ("dbgwcr11_el1",      CPENC (2,0,C0,C11,7),	0),
> -  SR_CORE ("dbgwcr12_el1",      CPENC (2,0,C0,C12,7),	0),
> -  SR_CORE ("dbgwcr13_el1",      CPENC (2,0,C0,C13,7),	0),
> -  SR_CORE ("dbgwcr14_el1",      CPENC (2,0,C0,C14,7),	0),
> -  SR_CORE ("dbgwcr15_el1",      CPENC (2,0,C0,C15,7),	0),
> -  SR_CORE ("mdrar_el1",		CPENC (2,0,C1,C0,0),	F_REG_READ),
> -  SR_CORE ("oslar_el1",		CPENC (2,0,C1,C0,4),	F_REG_WRITE),
> -  SR_CORE ("oslsr_el1",		CPENC (2,0,C1,C1,4),	F_REG_READ),
> -  SR_CORE ("osdlr_el1",		CPENC (2,0,C1,C3,4),	0),
> -  SR_CORE ("dbgprcr_el1",       CPENC (2,0,C1,C4,4),	0),
> -  SR_CORE ("dbgclaimset_el1",   CPENC (2,0,C7,C8,6),	0),
> -  SR_CORE ("dbgclaimclr_el1",   CPENC (2,0,C7,C9,6),	0),
> -  SR_CORE ("dbgauthstatus_el1", CPENC (2,0,C7,C14,6),	F_REG_READ),
> -  SR_PROFILE ("pmblimitr_el1",	CPENC (3,0,C9,C10,0),	0),
> -  SR_PROFILE ("pmbptr_el1",	CPENC (3,0,C9,C10,1),	0),
> -  SR_PROFILE ("pmbsr_el1",	CPENC (3,0,C9,C10,3),	0),
> -  SR_PROFILE ("pmbidr_el1",	CPENC (3,0,C9,C10,7),	F_REG_READ),
> -  SR_PROFILE ("pmscr_el1",	CPENC (3,0,C9,C9,0),	0),
> -  SR_PROFILE ("pmsicr_el1",	CPENC (3,0,C9,C9,2),	0),
> -  SR_PROFILE ("pmsirr_el1",	CPENC (3,0,C9,C9,3),	0),
> -  SR_PROFILE ("pmsfcr_el1",	CPENC (3,0,C9,C9,4),	0),
> -  SR_PROFILE ("pmsevfr_el1",	CPENC (3,0,C9,C9,5),	0),
> -  SR_PROFILE ("pmslatfr_el1",	CPENC (3,0,C9,C9,6),	0),
> -  SR_PROFILE ("pmsidr_el1",	CPENC (3,0,C9,C9,7),	F_REG_READ),
> -  SR_PROFILE ("pmscr_el2",	CPENC (3,4,C9,C9,0),	0),
> -  SR_PROFILE ("pmscr_el12",	CPENC (3,5,C9,C9,0),	0),
> -  SR_CORE ("pmcr_el0",		CPENC (3,3,C9,C12,0),	0),
> -  SR_CORE ("pmcntenset_el0",    CPENC (3,3,C9,C12,1),	0),
> -  SR_CORE ("pmcntenclr_el0",    CPENC (3,3,C9,C12,2),	0),
> -  SR_CORE ("pmovsclr_el0",      CPENC (3,3,C9,C12,3),	0),
> -  SR_CORE ("pmswinc_el0",       CPENC (3,3,C9,C12,4),	F_REG_WRITE),
> -  SR_CORE ("pmselr_el0",	CPENC (3,3,C9,C12,5),	0),
> -  SR_CORE ("pmceid0_el0",       CPENC (3,3,C9,C12,6),	F_REG_READ),
> -  SR_CORE ("pmceid1_el0",       CPENC (3,3,C9,C12,7),	F_REG_READ),
> -  SR_CORE ("pmccntr_el0",       CPENC (3,3,C9,C13,0),	0),
> -  SR_CORE ("pmxevtyper_el0",    CPENC (3,3,C9,C13,1),	0),
> -  SR_CORE ("pmxevcntr_el0",     CPENC (3,3,C9,C13,2),	0),
> -  SR_CORE ("pmuserenr_el0",     CPENC (3,3,C9,C14,0),	0),
> -  SR_CORE ("pmintenset_el1",    CPENC (3,0,C9,C14,1),	0),
> -  SR_CORE ("pmintenclr_el1",    CPENC (3,0,C9,C14,2),	0),
> -  SR_CORE ("pmovsset_el0",      CPENC (3,3,C9,C14,3),	0),
> -  SR_CORE ("pmevcntr0_el0",     CPENC (3,3,C14,C8,0),	0),
> -  SR_CORE ("pmevcntr1_el0",     CPENC (3,3,C14,C8,1),	0),
> -  SR_CORE ("pmevcntr2_el0",     CPENC (3,3,C14,C8,2),	0),
> -  SR_CORE ("pmevcntr3_el0",     CPENC (3,3,C14,C8,3),	0),
> -  SR_CORE ("pmevcntr4_el0",     CPENC (3,3,C14,C8,4),	0),
> -  SR_CORE ("pmevcntr5_el0",     CPENC (3,3,C14,C8,5),	0),
> -  SR_CORE ("pmevcntr6_el0",     CPENC (3,3,C14,C8,6),	0),
> -  SR_CORE ("pmevcntr7_el0",     CPENC (3,3,C14,C8,7),	0),
> -  SR_CORE ("pmevcntr8_el0",     CPENC (3,3,C14,C9,0),	0),
> -  SR_CORE ("pmevcntr9_el0",     CPENC (3,3,C14,C9,1),	0),
> -  SR_CORE ("pmevcntr10_el0",    CPENC (3,3,C14,C9,2),	0),
> -  SR_CORE ("pmevcntr11_el0",    CPENC (3,3,C14,C9,3),	0),
> -  SR_CORE ("pmevcntr12_el0",    CPENC (3,3,C14,C9,4),	0),
> -  SR_CORE ("pmevcntr13_el0",    CPENC (3,3,C14,C9,5),	0),
> -  SR_CORE ("pmevcntr14_el0",    CPENC (3,3,C14,C9,6),	0),
> -  SR_CORE ("pmevcntr15_el0",    CPENC (3,3,C14,C9,7),	0),
> -  SR_CORE ("pmevcntr16_el0",    CPENC (3,3,C14,C10,0),	0),
> -  SR_CORE ("pmevcntr17_el0",    CPENC (3,3,C14,C10,1),	0),
> -  SR_CORE ("pmevcntr18_el0",    CPENC (3,3,C14,C10,2),	0),
> -  SR_CORE ("pmevcntr19_el0",    CPENC (3,3,C14,C10,3),	0),
> -  SR_CORE ("pmevcntr20_el0",    CPENC (3,3,C14,C10,4),	0),
> -  SR_CORE ("pmevcntr21_el0",    CPENC (3,3,C14,C10,5),	0),
> -  SR_CORE ("pmevcntr22_el0",    CPENC (3,3,C14,C10,6),	0),
> -  SR_CORE ("pmevcntr23_el0",    CPENC (3,3,C14,C10,7),	0),
> -  SR_CORE ("pmevcntr24_el0",    CPENC (3,3,C14,C11,0),	0),
> -  SR_CORE ("pmevcntr25_el0",    CPENC (3,3,C14,C11,1),	0),
> -  SR_CORE ("pmevcntr26_el0",    CPENC (3,3,C14,C11,2),	0),
> -  SR_CORE ("pmevcntr27_el0",    CPENC (3,3,C14,C11,3),	0),
> -  SR_CORE ("pmevcntr28_el0",    CPENC (3,3,C14,C11,4),	0),
> -  SR_CORE ("pmevcntr29_el0",    CPENC (3,3,C14,C11,5),	0),
> -  SR_CORE ("pmevcntr30_el0",    CPENC (3,3,C14,C11,6),	0),
> -  SR_CORE ("pmevtyper0_el0",    CPENC (3,3,C14,C12,0),	0),
> -  SR_CORE ("pmevtyper1_el0",    CPENC (3,3,C14,C12,1),	0),
> -  SR_CORE ("pmevtyper2_el0",    CPENC (3,3,C14,C12,2),	0),
> -  SR_CORE ("pmevtyper3_el0",    CPENC (3,3,C14,C12,3),	0),
> -  SR_CORE ("pmevtyper4_el0",    CPENC (3,3,C14,C12,4),	0),
> -  SR_CORE ("pmevtyper5_el0",    CPENC (3,3,C14,C12,5),	0),
> -  SR_CORE ("pmevtyper6_el0",    CPENC (3,3,C14,C12,6),	0),
> -  SR_CORE ("pmevtyper7_el0",    CPENC (3,3,C14,C12,7),	0),
> -  SR_CORE ("pmevtyper8_el0",    CPENC (3,3,C14,C13,0),	0),
> -  SR_CORE ("pmevtyper9_el0",    CPENC (3,3,C14,C13,1),	0),
> -  SR_CORE ("pmevtyper10_el0",   CPENC (3,3,C14,C13,2),	0),
> -  SR_CORE ("pmevtyper11_el0",   CPENC (3,3,C14,C13,3),	0),
> -  SR_CORE ("pmevtyper12_el0",   CPENC (3,3,C14,C13,4),	0),
> -  SR_CORE ("pmevtyper13_el0",   CPENC (3,3,C14,C13,5),	0),
> -  SR_CORE ("pmevtyper14_el0",   CPENC (3,3,C14,C13,6),	0),
> -  SR_CORE ("pmevtyper15_el0",   CPENC (3,3,C14,C13,7),	0),
> -  SR_CORE ("pmevtyper16_el0",   CPENC (3,3,C14,C14,0),	0),
> -  SR_CORE ("pmevtyper17_el0",   CPENC (3,3,C14,C14,1),	0),
> -  SR_CORE ("pmevtyper18_el0",   CPENC (3,3,C14,C14,2),	0),
> -  SR_CORE ("pmevtyper19_el0",   CPENC (3,3,C14,C14,3),	0),
> -  SR_CORE ("pmevtyper20_el0",   CPENC (3,3,C14,C14,4),	0),
> -  SR_CORE ("pmevtyper21_el0",   CPENC (3,3,C14,C14,5),	0),
> -  SR_CORE ("pmevtyper22_el0",   CPENC (3,3,C14,C14,6),	0),
> -  SR_CORE ("pmevtyper23_el0",   CPENC (3,3,C14,C14,7),	0),
> -  SR_CORE ("pmevtyper24_el0",   CPENC (3,3,C14,C15,0),	0),
> -  SR_CORE ("pmevtyper25_el0",   CPENC (3,3,C14,C15,1),	0),
> -  SR_CORE ("pmevtyper26_el0",   CPENC (3,3,C14,C15,2),	0),
> -  SR_CORE ("pmevtyper27_el0",   CPENC (3,3,C14,C15,3),	0),
> -  SR_CORE ("pmevtyper28_el0",   CPENC (3,3,C14,C15,4),	0),
> -  SR_CORE ("pmevtyper29_el0",   CPENC (3,3,C14,C15,5),	0),
> -  SR_CORE ("pmevtyper30_el0",   CPENC (3,3,C14,C15,6),	0),
> -  SR_CORE ("pmccfiltr_el0",     CPENC (3,3,C14,C15,7),	0),
> -
> -  SR_V8_4A ("dit",		CPEN_ (3,C2,5),		0),
> -  SR_V8_4A ("trfcr_el1",		CPENC (3,0,C1,C2,1),	0),
> -  SR_V8_4A ("pmmir_el1",		CPENC (3,0,C9,C14,6),	F_REG_READ),
> -  SR_V8_4A ("trfcr_el2",		CPENC (3,4,C1,C2,1),	0),
> -  SR_V8_4A ("vstcr_el2",		CPENC (3,4,C2,C6,2),	0),
> -  SR_V8_4_A ("vsttbr_el2",	CPENC (3,4,C2,C6,0),	0),
> -  SR_V8_4A ("cnthvs_tval_el2",	CPENC (3,4,C14,C4,0),	0),
> -  SR_V8_4A ("cnthvs_cval_el2",	CPENC (3,4,C14,C4,2),	0),
> -  SR_V8_4A ("cnthvs_ctl_el2",	CPENC (3,4,C14,C4,1),	0),
> -  SR_V8_4A ("cnthps_tval_el2",	CPENC (3,4,C14,C5,0),	0),
> -  SR_V8_4A ("cnthps_cval_el2",	CPENC (3,4,C14,C5,2),	0),
> -  SR_V8_4A ("cnthps_ctl_el2",	CPENC (3,4,C14,C5,1),	0),
> -  SR_V8_4A ("sder32_el2",	CPENC (3,4,C1,C3,1),	0),
> -  SR_V8_4A ("vncr_el2",		CPENC (3,4,C2,C2,0),	0),
> -  SR_V8_4A ("trfcr_el12",	CPENC (3,5,C1,C2,1),	0),
> -
> -  SR_CORE ("mpam0_el1",		CPENC (3,0,C10,C5,1),	0),
> -  SR_CORE ("mpam1_el1",		CPENC (3,0,C10,C5,0),	0),
> -  SR_CORE ("mpam1_el12",	CPENC (3,5,C10,C5,0),	0),
> -  SR_CORE ("mpam2_el2",		CPENC (3,4,C10,C5,0),	0),
> -  SR_CORE ("mpam3_el3",		CPENC (3,6,C10,C5,0),	0),
> -  SR_CORE ("mpamhcr_el2",	CPENC (3,4,C10,C4,0),	0),
> -  SR_CORE ("mpamidr_el1",	CPENC (3,0,C10,C4,4),	F_REG_READ),
> -  SR_CORE ("mpamvpm0_el2",	CPENC (3,4,C10,C6,0),	0),
> -  SR_CORE ("mpamvpm1_el2",	CPENC (3,4,C10,C6,1),	0),
> -  SR_CORE ("mpamvpm2_el2",	CPENC (3,4,C10,C6,2),	0),
> -  SR_CORE ("mpamvpm3_el2",	CPENC (3,4,C10,C6,3),	0),
> -  SR_CORE ("mpamvpm4_el2",	CPENC (3,4,C10,C6,4),	0),
> -  SR_CORE ("mpamvpm5_el2",	CPENC (3,4,C10,C6,5),	0),
> -  SR_CORE ("mpamvpm6_el2",	CPENC (3,4,C10,C6,6),	0),
> -  SR_CORE ("mpamvpm7_el2",	CPENC (3,4,C10,C6,7),	0),
> -  SR_CORE ("mpamvpmv_el2",	CPENC (3,4,C10,C4,1),	0),
> -
> -  SR_V8R ("mpuir_el1",		CPENC (3,0,C0,C0,4),	F_REG_READ),
> -  SR_V8R ("mpuir_el2",		CPENC (3,4,C0,C0,4),	F_REG_READ),
> -  SR_V8R ("prbar_el1",		CPENC (3,0,C6,C8,0),	0),
> -  SR_V8R ("prbar_el2",		CPENC (3,4,C6,C8,0),	0),
> -
> -#define ENC_BARLAR(x,n,lar) \
> -  CPENC (3, (x-1) << 2, C6, 8 | (n >> 1), ((n & 1) << 2) | lar)
> -
> -#define PRBARn_ELx(x,n) SR_V8R ("prbar" #n "_el" #x, ENC_BARLAR (x,n,0), 0)
> -#define PRLARn_ELx(x,n) SR_V8R ("prlar" #n "_el" #x, ENC_BARLAR (x,n,1), 0)
> -
> -  SR_EXPAND_EL12 (PRBARn_ELx)
> -  SR_V8R ("prenr_el1",		CPENC (3,0,C6,C1,1),	0),
> -  SR_V8R ("prenr_el2",		CPENC (3,4,C6,C1,1),	0),
> -  SR_V8R ("prlar_el1",		CPENC (3,0,C6,C8,1),	0),
> -  SR_V8R ("prlar_el2",		CPENC (3,4,C6,C8,1),	0),
> -  SR_EXPAND_EL12 (PRLARn_ELx)
> -  SR_V8R ("prselr_el1",	CPENC (3,0,C6,C2,1),	0),
> -  SR_V8R ("prselr_el2",	CPENC (3,4,C6,C2,1),	0),
> -  SR_V8R ("vsctlr_el2",	CPENC (3,4,C2,C0,0),	0),
> -
> -  SR_CORE("trbbaser_el1", 	CPENC (3,0,C9,C11,2),	0),
> -  SR_CORE("trbidr_el1", 	CPENC (3,0,C9,C11,7),	F_REG_READ),
> -  SR_CORE("trblimitr_el1", 	CPENC (3,0,C9,C11,0),	0),
> -  SR_CORE("trbmar_el1", 	CPENC (3,0,C9,C11,4),	0),
> -  SR_CORE("trbptr_el1", 	CPENC (3,0,C9,C11,1),	0),
> -  SR_CORE("trbsr_el1",  	CPENC (3,0,C9,C11,3),	0),
> -  SR_CORE("trbtrg_el1", 	CPENC (3,0,C9,C11,6),	0),
> -
> -  SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ),
> -  SR_CORE ("trccidr0",      CPENC (2,1,C7,C12,7), F_REG_READ),
> -  SR_CORE ("trccidr1",      CPENC (2,1,C7,C13,7), F_REG_READ),
> -  SR_CORE ("trccidr2",      CPENC (2,1,C7,C14,7), F_REG_READ),
> -  SR_CORE ("trccidr3",      CPENC (2,1,C7,C15,7), F_REG_READ),
> -  SR_CORE ("trcdevaff0",    CPENC (2,1,C7,C10,6), F_REG_READ),
> -  SR_CORE ("trcdevaff1",    CPENC (2,1,C7,C11,6), F_REG_READ),
> -  SR_CORE ("trcdevarch",    CPENC (2,1,C7,C15,6), F_REG_READ),
> -  SR_CORE ("trcdevid",      CPENC (2,1,C7,C2,7),  F_REG_READ),
> -  SR_CORE ("trcdevtype",    CPENC (2,1,C7,C3,7),  F_REG_READ),
> -  SR_CORE ("trcidr0",       CPENC (2,1,C0,C8,7),  F_REG_READ),
> -  SR_CORE ("trcidr1",       CPENC (2,1,C0,C9,7),  F_REG_READ),
> -  SR_CORE ("trcidr2",       CPENC (2,1,C0,C10,7), F_REG_READ),
> -  SR_CORE ("trcidr3",       CPENC (2,1,C0,C11,7), F_REG_READ),
> -  SR_CORE ("trcidr4",       CPENC (2,1,C0,C12,7), F_REG_READ),
> -  SR_CORE ("trcidr5",       CPENC (2,1,C0,C13,7), F_REG_READ),
> -  SR_CORE ("trcidr6",       CPENC (2,1,C0,C14,7), F_REG_READ),
> -  SR_CORE ("trcidr7",       CPENC (2,1,C0,C15,7), F_REG_READ),
> -  SR_CORE ("trcidr8",       CPENC (2,1,C0,C0,6),  F_REG_READ),
> -  SR_CORE ("trcidr9",       CPENC (2,1,C0,C1,6),  F_REG_READ),
> -  SR_CORE ("trcidr10",      CPENC (2,1,C0,C2,6),  F_REG_READ),
> -  SR_CORE ("trcidr11",      CPENC (2,1,C0,C3,6),  F_REG_READ),
> -  SR_CORE ("trcidr12",      CPENC (2,1,C0,C4,6),  F_REG_READ),
> -  SR_CORE ("trcidr13",      CPENC (2,1,C0,C5,6),  F_REG_READ),
> -  SR_CORE ("trclsr",        CPENC (2,1,C7,C13,6), F_REG_READ),
> -  SR_CORE ("trcoslsr",      CPENC (2,1,C1,C1,4),  F_REG_READ),
> -  SR_CORE ("trcpdsr",       CPENC (2,1,C1,C5,4),  F_REG_READ),
> -  SR_CORE ("trcpidr0",      CPENC (2,1,C7,C8,7),  F_REG_READ),
> -  SR_CORE ("trcpidr1",      CPENC (2,1,C7,C9,7),  F_REG_READ),
> -  SR_CORE ("trcpidr2",      CPENC (2,1,C7,C10,7), F_REG_READ),
> -  SR_CORE ("trcpidr3",      CPENC (2,1,C7,C11,7), F_REG_READ),
> -  SR_CORE ("trcpidr4",      CPENC (2,1,C7,C4,7),  F_REG_READ),
> -  SR_CORE ("trcpidr5",      CPENC (2,1,C7,C5,7),  F_REG_READ),
> -  SR_CORE ("trcpidr6",      CPENC (2,1,C7,C6,7),  F_REG_READ),
> -  SR_CORE ("trcpidr7",      CPENC (2,1,C7,C7,7),  F_REG_READ),
> -  SR_CORE ("trcstatr",      CPENC (2,1,C0,C3,0),  F_REG_READ),
> -  SR_CORE ("trcacatr0",     CPENC (2,1,C2,C0,2),  0),
> -  SR_CORE ("trcacatr1",     CPENC (2,1,C2,C2,2),  0),
> -  SR_CORE ("trcacatr2",     CPENC (2,1,C2,C4,2),  0),
> -  SR_CORE ("trcacatr3",     CPENC (2,1,C2,C6,2),  0),
> -  SR_CORE ("trcacatr4",     CPENC (2,1,C2,C8,2),  0),
> -  SR_CORE ("trcacatr5",     CPENC (2,1,C2,C10,2), 0),
> -  SR_CORE ("trcacatr6",     CPENC (2,1,C2,C12,2), 0),
> -  SR_CORE ("trcacatr7",     CPENC (2,1,C2,C14,2), 0),
> -  SR_CORE ("trcacatr8",     CPENC (2,1,C2,C0,3),  0),
> -  SR_CORE ("trcacatr9",     CPENC (2,1,C2,C2,3),  0),
> -  SR_CORE ("trcacatr10",    CPENC (2,1,C2,C4,3),  0),
> -  SR_CORE ("trcacatr11",    CPENC (2,1,C2,C6,3),  0),
> -  SR_CORE ("trcacatr12",    CPENC (2,1,C2,C8,3),  0),
> -  SR_CORE ("trcacatr13",    CPENC (2,1,C2,C10,3), 0),
> -  SR_CORE ("trcacatr14",    CPENC (2,1,C2,C12,3), 0),
> -  SR_CORE ("trcacatr15",    CPENC (2,1,C2,C14,3), 0),
> -  SR_CORE ("trcacvr0",      CPENC (2,1,C2,C0,0),  0),
> -  SR_CORE ("trcacvr1",      CPENC (2,1,C2,C2,0),  0),
> -  SR_CORE ("trcacvr2",      CPENC (2,1,C2,C4,0),  0),
> -  SR_CORE ("trcacvr3",      CPENC (2,1,C2,C6,0),  0),
> -  SR_CORE ("trcacvr4",      CPENC (2,1,C2,C8,0),  0),
> -  SR_CORE ("trcacvr5",      CPENC (2,1,C2,C10,0), 0),
> -  SR_CORE ("trcacvr6",      CPENC (2,1,C2,C12,0), 0),
> -  SR_CORE ("trcacvr7",      CPENC (2,1,C2,C14,0), 0),
> -  SR_CORE ("trcacvr8",      CPENC (2,1,C2,C0,1),  0),
> -  SR_CORE ("trcacvr9",      CPENC (2,1,C2,C2,1),  0),
> -  SR_CORE ("trcacvr10",     CPENC (2,1,C2,C4,1),  0),
> -  SR_CORE ("trcacvr11",     CPENC (2,1,C2,C6,1),  0),
> -  SR_CORE ("trcacvr12",     CPENC (2,1,C2,C8,1),  0),
> -  SR_CORE ("trcacvr13",     CPENC (2,1,C2,C10,1), 0),
> -  SR_CORE ("trcacvr14",     CPENC (2,1,C2,C12,1), 0),
> -  SR_CORE ("trcacvr15",     CPENC (2,1,C2,C14,1), 0),
> -  SR_CORE ("trcauxctlr",    CPENC (2,1,C0,C6,0),  0),
> -  SR_CORE ("trcbbctlr",     CPENC (2,1,C0,C15,0), 0),
> -  SR_CORE ("trcccctlr",     CPENC (2,1,C0,C14,0), 0),
> -  SR_CORE ("trccidcctlr0",  CPENC (2,1,C3,C0,2),  0),
> -  SR_CORE ("trccidcctlr1",  CPENC (2,1,C3,C1,2),  0),
> -  SR_CORE ("trccidcvr0",    CPENC (2,1,C3,C0,0),  0),
> -  SR_CORE ("trccidcvr1",    CPENC (2,1,C3,C2,0),  0),
> -  SR_CORE ("trccidcvr2",    CPENC (2,1,C3,C4,0),  0),
> -  SR_CORE ("trccidcvr3",    CPENC (2,1,C3,C6,0),  0),
> -  SR_CORE ("trccidcvr4",    CPENC (2,1,C3,C8,0),  0),
> -  SR_CORE ("trccidcvr5",    CPENC (2,1,C3,C10,0), 0),
> -  SR_CORE ("trccidcvr6",    CPENC (2,1,C3,C12,0), 0),
> -  SR_CORE ("trccidcvr7",    CPENC (2,1,C3,C14,0), 0),
> -  SR_CORE ("trcclaimclr",   CPENC (2,1,C7,C9,6),  0),
> -  SR_CORE ("trcclaimset",   CPENC (2,1,C7,C8,6),  0),
> -  SR_CORE ("trccntctlr0",   CPENC (2,1,C0,C4,5),  0),
> -  SR_CORE ("trccntctlr1",   CPENC (2,1,C0,C5,5),  0),
> -  SR_CORE ("trccntctlr2",   CPENC (2,1,C0,C6,5),  0),
> -  SR_CORE ("trccntctlr3",   CPENC (2,1,C0,C7,5),  0),
> -  SR_CORE ("trccntrldvr0",  CPENC (2,1,C0,C0,5),  0),
> -  SR_CORE ("trccntrldvr1",  CPENC (2,1,C0,C1,5),  0),
> -  SR_CORE ("trccntrldvr2",  CPENC (2,1,C0,C2,5),  0),
> -  SR_CORE ("trccntrldvr3",  CPENC (2,1,C0,C3,5),  0),
> -  SR_CORE ("trccntvr0",     CPENC (2,1,C0,C8,5),  0),
> -  SR_CORE ("trccntvr1",     CPENC (2,1,C0,C9,5),  0),
> -  SR_CORE ("trccntvr2",     CPENC (2,1,C0,C10,5), 0),
> -  SR_CORE ("trccntvr3",     CPENC (2,1,C0,C11,5), 0),
> -  SR_CORE ("trcconfigr",    CPENC (2,1,C0,C4,0),  0),
> -  SR_CORE ("trcdvcmr0",     CPENC (2,1,C2,C0,6),  0),
> -  SR_CORE ("trcdvcmr1",     CPENC (2,1,C2,C4,6),  0),
> -  SR_CORE ("trcdvcmr2",     CPENC (2,1,C2,C8,6),  0),
> -  SR_CORE ("trcdvcmr3",     CPENC (2,1,C2,C12,6), 0),
> -  SR_CORE ("trcdvcmr4",     CPENC (2,1,C2,C0,7),  0),
> -  SR_CORE ("trcdvcmr5",     CPENC (2,1,C2,C4,7),  0),
> -  SR_CORE ("trcdvcmr6",     CPENC (2,1,C2,C8,7),  0),
> -  SR_CORE ("trcdvcmr7",     CPENC (2,1,C2,C12,7), 0),
> -  SR_CORE ("trcdvcvr0",     CPENC (2,1,C2,C0,4),  0),
> -  SR_CORE ("trcdvcvr1",     CPENC (2,1,C2,C4,4),  0),
> -  SR_CORE ("trcdvcvr2",     CPENC (2,1,C2,C8,4),  0),
> -  SR_CORE ("trcdvcvr3",     CPENC (2,1,C2,C12,4), 0),
> -  SR_CORE ("trcdvcvr4",     CPENC (2,1,C2,C0,5),  0),
> -  SR_CORE ("trcdvcvr5",     CPENC (2,1,C2,C4,5),  0),
> -  SR_CORE ("trcdvcvr6",     CPENC (2,1,C2,C8,5),  0),
> -  SR_CORE ("trcdvcvr7",     CPENC (2,1,C2,C12,5), 0),
> -  SR_CORE ("trceventctl0r", CPENC (2,1,C0,C8,0),  0),
> -  SR_CORE ("trceventctl1r", CPENC (2,1,C0,C9,0),  0),
> -  SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4),  0),
> -  SR_CORE ("trcextinselr",  CPENC (2,1,C0,C8,4),  0),
> -  SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4),  0),
> -  SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
> -  SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
> -  SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0),
> -  SR_CORE ("trcimspec1",    CPENC (2,1,C0,C1,7),  0),
> -  SR_CORE ("trcimspec2",    CPENC (2,1,C0,C2,7),  0),
> -  SR_CORE ("trcimspec3",    CPENC (2,1,C0,C3,7),  0),
> -  SR_CORE ("trcimspec4",    CPENC (2,1,C0,C4,7),  0),
> -  SR_CORE ("trcimspec5",    CPENC (2,1,C0,C5,7),  0),
> -  SR_CORE ("trcimspec6",    CPENC (2,1,C0,C6,7),  0),
> -  SR_CORE ("trcimspec7",    CPENC (2,1,C0,C7,7),  0),
> -  SR_CORE ("trcitctrl",     CPENC (2,1,C7,C0,4),  0),
> -  SR_CORE ("trcpdcr",       CPENC (2,1,C1,C4,4),  0),
> -  SR_CORE ("trcprgctlr",    CPENC (2,1,C0,C1,0),  0),
> -  SR_CORE ("trcprocselr",   CPENC (2,1,C0,C2,0),  0),
> -  SR_CORE ("trcqctlr",      CPENC (2,1,C0,C1,1),  0),
> -  SR_CORE ("trcrsr",        CPENC (2,1,C0,C10,0), 0),
> -  SR_CORE ("trcrsctlr2",    CPENC (2,1,C1,C2,0),  0),
> -  SR_CORE ("trcrsctlr3",    CPENC (2,1,C1,C3,0),  0),
> -  SR_CORE ("trcrsctlr4",    CPENC (2,1,C1,C4,0),  0),
> -  SR_CORE ("trcrsctlr5",    CPENC (2,1,C1,C5,0),  0),
> -  SR_CORE ("trcrsctlr6",    CPENC (2,1,C1,C6,0),  0),
> -  SR_CORE ("trcrsctlr7",    CPENC (2,1,C1,C7,0),  0),
> -  SR_CORE ("trcrsctlr8",    CPENC (2,1,C1,C8,0),  0),
> -  SR_CORE ("trcrsctlr9",    CPENC (2,1,C1,C9,0),  0),
> -  SR_CORE ("trcrsctlr10",   CPENC (2,1,C1,C10,0), 0),
> -  SR_CORE ("trcrsctlr11",   CPENC (2,1,C1,C11,0), 0),
> -  SR_CORE ("trcrsctlr12",   CPENC (2,1,C1,C12,0), 0),
> -  SR_CORE ("trcrsctlr13",   CPENC (2,1,C1,C13,0), 0),
> -  SR_CORE ("trcrsctlr14",   CPENC (2,1,C1,C14,0), 0),
> -  SR_CORE ("trcrsctlr15",   CPENC (2,1,C1,C15,0), 0),
> -  SR_CORE ("trcrsctlr16",   CPENC (2,1,C1,C0,1),  0),
> -  SR_CORE ("trcrsctlr17",   CPENC (2,1,C1,C1,1),  0),
> -  SR_CORE ("trcrsctlr18",   CPENC (2,1,C1,C2,1),  0),
> -  SR_CORE ("trcrsctlr19",   CPENC (2,1,C1,C3,1),  0),
> -  SR_CORE ("trcrsctlr20",   CPENC (2,1,C1,C4,1),  0),
> -  SR_CORE ("trcrsctlr21",   CPENC (2,1,C1,C5,1),  0),
> -  SR_CORE ("trcrsctlr22",   CPENC (2,1,C1,C6,1),  0),
> -  SR_CORE ("trcrsctlr23",   CPENC (2,1,C1,C7,1),  0),
> -  SR_CORE ("trcrsctlr24",   CPENC (2,1,C1,C8,1),  0),
> -  SR_CORE ("trcrsctlr25",   CPENC (2,1,C1,C9,1),  0),
> -  SR_CORE ("trcrsctlr26",   CPENC (2,1,C1,C10,1), 0),
> -  SR_CORE ("trcrsctlr27",   CPENC (2,1,C1,C11,1), 0),
> -  SR_CORE ("trcrsctlr28",   CPENC (2,1,C1,C12,1), 0),
> -  SR_CORE ("trcrsctlr29",   CPENC (2,1,C1,C13,1), 0),
> -  SR_CORE ("trcrsctlr30",   CPENC (2,1,C1,C14,1), 0),
> -  SR_CORE ("trcrsctlr31",   CPENC (2,1,C1,C15,1), 0),
> -  SR_CORE ("trcseqevr0",    CPENC (2,1,C0,C0,4),  0),
> -  SR_CORE ("trcseqevr1",    CPENC (2,1,C0,C1,4),  0),
> -  SR_CORE ("trcseqevr2",    CPENC (2,1,C0,C2,4),  0),
> -  SR_CORE ("trcseqrstevr",  CPENC (2,1,C0,C6,4),  0),
> -  SR_CORE ("trcseqstr",     CPENC (2,1,C0,C7,4),  0),
> -  SR_CORE ("trcssccr0",     CPENC (2,1,C1,C0,2),  0),
> -  SR_CORE ("trcssccr1",     CPENC (2,1,C1,C1,2),  0),
> -  SR_CORE ("trcssccr2",     CPENC (2,1,C1,C2,2),  0),
> -  SR_CORE ("trcssccr3",     CPENC (2,1,C1,C3,2),  0),
> -  SR_CORE ("trcssccr4",     CPENC (2,1,C1,C4,2),  0),
> -  SR_CORE ("trcssccr5",     CPENC (2,1,C1,C5,2),  0),
> -  SR_CORE ("trcssccr6",     CPENC (2,1,C1,C6,2),  0),
> -  SR_CORE ("trcssccr7",     CPENC (2,1,C1,C7,2),  0),
> -  SR_CORE ("trcsscsr0",     CPENC (2,1,C1,C8,2),  0),
> -  SR_CORE ("trcsscsr1",     CPENC (2,1,C1,C9,2),  0),
> -  SR_CORE ("trcsscsr2",     CPENC (2,1,C1,C10,2), 0),
> -  SR_CORE ("trcsscsr3",     CPENC (2,1,C1,C11,2), 0),
> -  SR_CORE ("trcsscsr4",     CPENC (2,1,C1,C12,2), 0),
> -  SR_CORE ("trcsscsr5",     CPENC (2,1,C1,C13,2), 0),
> -  SR_CORE ("trcsscsr6",     CPENC (2,1,C1,C14,2), 0),
> -  SR_CORE ("trcsscsr7",     CPENC (2,1,C1,C15,2), 0),
> -  SR_CORE ("trcsspcicr0",   CPENC (2,1,C1,C0,3),  0),
> -  SR_CORE ("trcsspcicr1",   CPENC (2,1,C1,C1,3),  0),
> -  SR_CORE ("trcsspcicr2",   CPENC (2,1,C1,C2,3),  0),
> -  SR_CORE ("trcsspcicr3",   CPENC (2,1,C1,C3,3),  0),
> -  SR_CORE ("trcsspcicr4",   CPENC (2,1,C1,C4,3),  0),
> -  SR_CORE ("trcsspcicr5",   CPENC (2,1,C1,C5,3),  0),
> -  SR_CORE ("trcsspcicr6",   CPENC (2,1,C1,C6,3),  0),
> -  SR_CORE ("trcsspcicr7",   CPENC (2,1,C1,C7,3),  0),
> -  SR_CORE ("trcstallctlr",  CPENC (2,1,C0,C11,0), 0),
> -  SR_CORE ("trcsyncpr",     CPENC (2,1,C0,C13,0), 0),
> -  SR_CORE ("trctraceidr",   CPENC (2,1,C0,C0,1),  0),
> -  SR_CORE ("trctsctlr",     CPENC (2,1,C0,C12,0), 0),
> -  SR_CORE ("trcvdarcctlr",  CPENC (2,1,C0,C10,2), 0),
> -  SR_CORE ("trcvdctlr",     CPENC (2,1,C0,C8,2),  0),
> -  SR_CORE ("trcvdsacctlr",  CPENC (2,1,C0,C9,2),  0),
> -  SR_CORE ("trcvictlr",     CPENC (2,1,C0,C0,2),  0),
> -  SR_CORE ("trcviiectlr",   CPENC (2,1,C0,C1,2),  0),
> -  SR_CORE ("trcvipcssctlr", CPENC (2,1,C0,C3,2),  0),
> -  SR_CORE ("trcvissctlr",   CPENC (2,1,C0,C2,2),  0),
> -  SR_CORE ("trcvmidcctlr0", CPENC (2,1,C3,C2,2),  0),
> -  SR_CORE ("trcvmidcctlr1", CPENC (2,1,C3,C3,2),  0),
> -  SR_CORE ("trcvmidcvr0",   CPENC (2,1,C3,C0,1),  0),
> -  SR_CORE ("trcvmidcvr1",   CPENC (2,1,C3,C2,1),  0),
> -  SR_CORE ("trcvmidcvr2",   CPENC (2,1,C3,C4,1),  0),
> -  SR_CORE ("trcvmidcvr3",   CPENC (2,1,C3,C6,1),  0),
> -  SR_CORE ("trcvmidcvr4",   CPENC (2,1,C3,C8,1),  0),
> -  SR_CORE ("trcvmidcvr5",   CPENC (2,1,C3,C10,1), 0),
> -  SR_CORE ("trcvmidcvr6",   CPENC (2,1,C3,C12,1), 0),
> -  SR_CORE ("trcvmidcvr7",   CPENC (2,1,C3,C14,1), 0),
> -  SR_CORE ("trclar",        CPENC (2,1,C7,C12,6), F_REG_WRITE),
> -  SR_CORE ("trcoslar",      CPENC (2,1,C1,C0,4),  F_REG_WRITE),
> -
> -  SR_CORE ("csrcr_el0",     CPENC (2,3,C8,C0,0),  0),
> -  SR_CORE ("csrptr_el0",    CPENC (2,3,C8,C0,1),  0),
> -  SR_CORE ("csridr_el0",    CPENC (2,3,C8,C0,2),  F_REG_READ),
> -  SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3),  F_REG_READ),
> -  SR_CORE ("csrcr_el1",     CPENC (2,0,C8,C0,0),  0),
> -  SR_CORE ("csrcr_el12",    CPENC (2,5,C8,C0,0),  0),
> -  SR_CORE ("csrptr_el1",    CPENC (2,0,C8,C0,1),  0),
> -  SR_CORE ("csrptr_el12",   CPENC (2,5,C8,C0,1),  0),
> -  SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3),  F_REG_READ),
> -  SR_CORE ("csrcr_el2",     CPENC (2,4,C8,C0,0),  0),
> -  SR_CORE ("csrptr_el2",    CPENC (2,4,C8,C0,1),  0),
> -  SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3),  F_REG_READ),
> -
> -  SR_LOR ("lorid_el1",      CPENC (3,0,C10,C4,7),  F_REG_READ),
> -  SR_LOR ("lorc_el1",       CPENC (3,0,C10,C4,3),  0),
> -  SR_LOR ("lorea_el1",      CPENC (3,0,C10,C4,1),  0),
> -  SR_LOR ("lorn_el1",       CPENC (3,0,C10,C4,2),  0),
> -  SR_LOR ("lorsa_el1",      CPENC (3,0,C10,C4,0),  0),
> -
> -  SR_CORE ("icc_ctlr_el3",  CPENC (3,6,C12,C12,4), 0),
> -  SR_CORE ("icc_sre_el1",   CPENC (3,0,C12,C12,5), 0),
> -  SR_CORE ("icc_sre_el2",   CPENC (3,4,C12,C9,5),  0),
> -  SR_CORE ("icc_sre_el3",   CPENC (3,6,C12,C12,5), 0),
> -  SR_CORE ("ich_vtr_el2",   CPENC (3,4,C12,C11,1), F_REG_READ),
> -
> -  SR_CORE ("brbcr_el1",     CPENC (2,1,C9,C0,0),  0),
> -  SR_CORE ("brbcr_el12",    CPENC (2,5,C9,C0,0),  0),
> -  SR_CORE ("brbfcr_el1",    CPENC (2,1,C9,C0,1),  0),
> -  SR_CORE ("brbts_el1",     CPENC (2,1,C9,C0,2),  0),
> -  SR_CORE ("brbinfinj_el1", CPENC (2,1,C9,C1,0),  0),
> -  SR_CORE ("brbsrcinj_el1", CPENC (2,1,C9,C1,1),  0),
> -  SR_CORE ("brbtgtinj_el1", CPENC (2,1,C9,C1,2),  0),
> -  SR_CORE ("brbidr0_el1",   CPENC (2,1,C9,C2,0),  F_REG_READ),
> -  SR_CORE ("brbcr_el2",     CPENC (2,4,C9,C0,0),  0),
> -  SR_CORE ("brbsrc0_el1",   CPENC (2,1,C8,C0,1),  F_REG_READ),
> -  SR_CORE ("brbsrc1_el1",   CPENC (2,1,C8,C1,1),  F_REG_READ),
> -  SR_CORE ("brbsrc2_el1",   CPENC (2,1,C8,C2,1),  F_REG_READ),
> -  SR_CORE ("brbsrc3_el1",   CPENC (2,1,C8,C3,1),  F_REG_READ),
> -  SR_CORE ("brbsrc4_el1",   CPENC (2,1,C8,C4,1),  F_REG_READ),
> -  SR_CORE ("brbsrc5_el1",   CPENC (2,1,C8,C5,1),  F_REG_READ),
> -  SR_CORE ("brbsrc6_el1",   CPENC (2,1,C8,C6,1),  F_REG_READ),
> -  SR_CORE ("brbsrc7_el1",   CPENC (2,1,C8,C7,1),  F_REG_READ),
> -  SR_CORE ("brbsrc8_el1",   CPENC (2,1,C8,C8,1),  F_REG_READ),
> -  SR_CORE ("brbsrc9_el1",   CPENC (2,1,C8,C9,1),  F_REG_READ),
> -  SR_CORE ("brbsrc10_el1",  CPENC (2,1,C8,C10,1), F_REG_READ),
> -  SR_CORE ("brbsrc11_el1",  CPENC (2,1,C8,C11,1), F_REG_READ),
> -  SR_CORE ("brbsrc12_el1",  CPENC (2,1,C8,C12,1), F_REG_READ),
> -  SR_CORE ("brbsrc13_el1",  CPENC (2,1,C8,C13,1), F_REG_READ),
> -  SR_CORE ("brbsrc14_el1",  CPENC (2,1,C8,C14,1), F_REG_READ),
> -  SR_CORE ("brbsrc15_el1",  CPENC (2,1,C8,C15,1), F_REG_READ),
> -  SR_CORE ("brbsrc16_el1",  CPENC (2,1,C8,C0,5),  F_REG_READ),
> -  SR_CORE ("brbsrc17_el1",  CPENC (2,1,C8,C1,5),  F_REG_READ),
> -  SR_CORE ("brbsrc18_el1",  CPENC (2,1,C8,C2,5),  F_REG_READ),
> -  SR_CORE ("brbsrc19_el1",  CPENC (2,1,C8,C3,5),  F_REG_READ),
> -  SR_CORE ("brbsrc20_el1",  CPENC (2,1,C8,C4,5),  F_REG_READ),
> -  SR_CORE ("brbsrc21_el1",  CPENC (2,1,C8,C5,5),  F_REG_READ),
> -  SR_CORE ("brbsrc22_el1",  CPENC (2,1,C8,C6,5),  F_REG_READ),
> -  SR_CORE ("brbsrc23_el1",  CPENC (2,1,C8,C7,5),  F_REG_READ),
> -  SR_CORE ("brbsrc24_el1",  CPENC (2,1,C8,C8,5),  F_REG_READ),
> -  SR_CORE ("brbsrc25_el1",  CPENC (2,1,C8,C9,5),  F_REG_READ),
> -  SR_CORE ("brbsrc26_el1",  CPENC (2,1,C8,C10,5), F_REG_READ),
> -  SR_CORE ("brbsrc27_el1",  CPENC (2,1,C8,C11,5), F_REG_READ),
> -  SR_CORE ("brbsrc28_el1",  CPENC (2,1,C8,C12,5), F_REG_READ),
> -  SR_CORE ("brbsrc29_el1",  CPENC (2,1,C8,C13,5), F_REG_READ),
> -  SR_CORE ("brbsrc30_el1",  CPENC (2,1,C8,C14,5), F_REG_READ),
> -  SR_CORE ("brbsrc31_el1",  CPENC (2,1,C8,C15,5), F_REG_READ),
> -  SR_CORE ("brbtgt0_el1",   CPENC (2,1,C8,C0,2),  F_REG_READ),
> -  SR_CORE ("brbtgt1_el1",   CPENC (2,1,C8,C1,2),  F_REG_READ),
> -  SR_CORE ("brbtgt2_el1",   CPENC (2,1,C8,C2,2),  F_REG_READ),
> -  SR_CORE ("brbtgt3_el1",   CPENC (2,1,C8,C3,2),  F_REG_READ),
> -  SR_CORE ("brbtgt4_el1",   CPENC (2,1,C8,C4,2),  F_REG_READ),
> -  SR_CORE ("brbtgt5_el1",   CPENC (2,1,C8,C5,2),  F_REG_READ),
> -  SR_CORE ("brbtgt6_el1",   CPENC (2,1,C8,C6,2),  F_REG_READ),
> -  SR_CORE ("brbtgt7_el1",   CPENC (2,1,C8,C7,2),  F_REG_READ),
> -  SR_CORE ("brbtgt8_el1",   CPENC (2,1,C8,C8,2),  F_REG_READ),
> -  SR_CORE ("brbtgt9_el1",   CPENC (2,1,C8,C9,2),  F_REG_READ),
> -  SR_CORE ("brbtgt10_el1",  CPENC (2,1,C8,C10,2), F_REG_READ),
> -  SR_CORE ("brbtgt11_el1",  CPENC (2,1,C8,C11,2), F_REG_READ),
> -  SR_CORE ("brbtgt12_el1",  CPENC (2,1,C8,C12,2), F_REG_READ),
> -  SR_CORE ("brbtgt13_el1",  CPENC (2,1,C8,C13,2), F_REG_READ),
> -  SR_CORE ("brbtgt14_el1",  CPENC (2,1,C8,C14,2), F_REG_READ),
> -  SR_CORE ("brbtgt15_el1",  CPENC (2,1,C8,C15,2), F_REG_READ),
> -  SR_CORE ("brbtgt16_el1",  CPENC (2,1,C8,C0,6),  F_REG_READ),
> -  SR_CORE ("brbtgt17_el1",  CPENC (2,1,C8,C1,6),  F_REG_READ),
> -  SR_CORE ("brbtgt18_el1",  CPENC (2,1,C8,C2,6),  F_REG_READ),
> -  SR_CORE ("brbtgt19_el1",  CPENC (2,1,C8,C3,6),  F_REG_READ),
> -  SR_CORE ("brbtgt20_el1",  CPENC (2,1,C8,C4,6),  F_REG_READ),
> -  SR_CORE ("brbtgt21_el1",  CPENC (2,1,C8,C5,6),  F_REG_READ),
> -  SR_CORE ("brbtgt22_el1",  CPENC (2,1,C8,C6,6),  F_REG_READ),
> -  SR_CORE ("brbtgt23_el1",  CPENC (2,1,C8,C7,6),  F_REG_READ),
> -  SR_CORE ("brbtgt24_el1",  CPENC (2,1,C8,C8,6),  F_REG_READ),
> -  SR_CORE ("brbtgt25_el1",  CPENC (2,1,C8,C9,6),  F_REG_READ),
> -  SR_CORE ("brbtgt26_el1",  CPENC (2,1,C8,C10,6), F_REG_READ),
> -  SR_CORE ("brbtgt27_el1",  CPENC (2,1,C8,C11,6), F_REG_READ),
> -  SR_CORE ("brbtgt28_el1",  CPENC (2,1,C8,C12,6), F_REG_READ),
> -  SR_CORE ("brbtgt29_el1",  CPENC (2,1,C8,C13,6), F_REG_READ),
> -  SR_CORE ("brbtgt30_el1",  CPENC (2,1,C8,C14,6), F_REG_READ),
> -  SR_CORE ("brbtgt31_el1",  CPENC (2,1,C8,C15,6), F_REG_READ),
> -  SR_CORE ("brbinf0_el1",   CPENC (2,1,C8,C0,0),  F_REG_READ),
> -  SR_CORE ("brbinf1_el1",   CPENC (2,1,C8,C1,0),  F_REG_READ),
> -  SR_CORE ("brbinf2_el1",   CPENC (2,1,C8,C2,0),  F_REG_READ),
> -  SR_CORE ("brbinf3_el1",   CPENC (2,1,C8,C3,0),  F_REG_READ),
> -  SR_CORE ("brbinf4_el1",   CPENC (2,1,C8,C4,0),  F_REG_READ),
> -  SR_CORE ("brbinf5_el1",   CPENC (2,1,C8,C5,0),  F_REG_READ),
> -  SR_CORE ("brbinf6_el1",   CPENC (2,1,C8,C6,0),  F_REG_READ),
> -  SR_CORE ("brbinf7_el1",   CPENC (2,1,C8,C7,0),  F_REG_READ),
> -  SR_CORE ("brbinf8_el1",   CPENC (2,1,C8,C8,0),  F_REG_READ),
> -  SR_CORE ("brbinf9_el1",   CPENC (2,1,C8,C9,0),  F_REG_READ),
> -  SR_CORE ("brbinf10_el1",  CPENC (2,1,C8,C10,0), F_REG_READ),
> -  SR_CORE ("brbinf11_el1",  CPENC (2,1,C8,C11,0), F_REG_READ),
> -  SR_CORE ("brbinf12_el1",  CPENC (2,1,C8,C12,0), F_REG_READ),
> -  SR_CORE ("brbinf13_el1",  CPENC (2,1,C8,C13,0), F_REG_READ),
> -  SR_CORE ("brbinf14_el1",  CPENC (2,1,C8,C14,0), F_REG_READ),
> -  SR_CORE ("brbinf15_el1",  CPENC (2,1,C8,C15,0), F_REG_READ),
> -  SR_CORE ("brbinf16_el1",  CPENC (2,1,C8,C0,4),  F_REG_READ),
> -  SR_CORE ("brbinf17_el1",  CPENC (2,1,C8,C1,4),  F_REG_READ),
> -  SR_CORE ("brbinf18_el1",  CPENC (2,1,C8,C2,4),  F_REG_READ),
> -  SR_CORE ("brbinf19_el1",  CPENC (2,1,C8,C3,4),  F_REG_READ),
> -  SR_CORE ("brbinf20_el1",  CPENC (2,1,C8,C4,4),  F_REG_READ),
> -  SR_CORE ("brbinf21_el1",  CPENC (2,1,C8,C5,4),  F_REG_READ),
> -  SR_CORE ("brbinf22_el1",  CPENC (2,1,C8,C6,4),  F_REG_READ),
> -  SR_CORE ("brbinf23_el1",  CPENC (2,1,C8,C7,4),  F_REG_READ),
> -  SR_CORE ("brbinf24_el1",  CPENC (2,1,C8,C8,4),  F_REG_READ),
> -  SR_CORE ("brbinf25_el1",  CPENC (2,1,C8,C9,4),  F_REG_READ),
> -  SR_CORE ("brbinf26_el1",  CPENC (2,1,C8,C10,4), F_REG_READ),
> -  SR_CORE ("brbinf27_el1",  CPENC (2,1,C8,C11,4), F_REG_READ),
> -  SR_CORE ("brbinf28_el1",  CPENC (2,1,C8,C12,4), F_REG_READ),
> -  SR_CORE ("brbinf29_el1",  CPENC (2,1,C8,C13,4), F_REG_READ),
> -  SR_CORE ("brbinf30_el1",  CPENC (2,1,C8,C14,4), F_REG_READ),
> -  SR_CORE ("brbinf31_el1",  CPENC (2,1,C8,C15,4), F_REG_READ),
> -
> -  SR_CORE ("accdata_el1",   CPENC (3,0,C13,C0,5), 0),
> -
> -  SR_CORE ("mfar_el3",      CPENC (3,6,C6,C0,5), 0),
> -  SR_CORE ("gpccr_el3",     CPENC (3,6,C2,C1,6), 0),
> -  SR_CORE ("gptbr_el3",     CPENC (3,6,C2,C1,4), 0),
> -
> -  SR_CORE ("mecidr_el2",    CPENC (3,4,C10,C8,7),  F_REG_READ),
> -  SR_CORE ("mecid_p0_el2",  CPENC (3,4,C10,C8,0),  0),
> -  SR_CORE ("mecid_a0_el2",  CPENC (3,4,C10,C8,1),  0),
> -  SR_CORE ("mecid_p1_el2",  CPENC (3,4,C10,C8,2),  0),
> -  SR_CORE ("mecid_a1_el2",  CPENC (3,4,C10,C8,3),  0),
> -  SR_CORE ("vmecid_p_el2",  CPENC (3,4,C10,C9,0),  0),
> -  SR_CORE ("vmecid_a_el2",  CPENC (3,4,C10,C9,1),  0),
> -  SR_CORE ("mecid_rl_a_el3",CPENC (3,6,C10,C10,1), 0),
> -
> -  SR_SME ("svcr",             CPENC (3,3,C4,C2,2),  0),
> -  SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5),  F_REG_READ),
> -  SR_SME ("smcr_el1",         CPENC (3,0,C1,C2,6),  0),
> -  SR_SME ("smcr_el12",        CPENC (3,5,C1,C2,6),  0),
> -  SR_SME ("smcr_el2",         CPENC (3,4,C1,C2,6),  0),
> -  SR_SME ("smcr_el3",         CPENC (3,6,C1,C2,6),  0),
> -  SR_SME ("smpri_el1",        CPENC (3,0,C1,C2,4),  0),
> -  SR_SME ("smprimap_el2",     CPENC (3,4,C1,C2,5),  0),
> -  SR_SME ("smidr_el1",        CPENC (3,1,C0,C0,6),  F_REG_READ),
> -  SR_SME ("tpidr2_el0",       CPENC (3,3,C13,C0,5), 0),
> -  SR_SME ("mpamsm_el1",       CPENC (3,0,C10,C5,3), 0),
> -
> -  SR_AMU ("amcr_el0",           CPENC (3,3,C13,C2,0),   0),
> -  SR_AMU ("amcfgr_el0",         CPENC (3,3,C13,C2,1),   F_REG_READ),
> -  SR_AMU ("amcgcr_el0",         CPENC (3,3,C13,C2,2),   F_REG_READ),
> -  SR_AMU ("amuserenr_el0",      CPENC (3,3,C13,C2,3),   0),
> -  SR_AMU ("amcntenclr0_el0",    CPENC (3,3,C13,C2,4),   0),
> -  SR_AMU ("amcntenset0_el0",    CPENC (3,3,C13,C2,5),   0),
> -  SR_AMU ("amcntenclr1_el0",    CPENC (3,3,C13,C3,0),   0),
> -  SR_AMU ("amcntenset1_el0",    CPENC (3,3,C13,C3,1),   0),
> -  SR_AMU ("amevcntr00_el0",     CPENC (3,3,C13,C4,0),   0),
> -  SR_AMU ("amevcntr01_el0",     CPENC (3,3,C13,C4,1),   0),
> -  SR_AMU ("amevcntr02_el0",     CPENC (3,3,C13,C4,2),   0),
> -  SR_AMU ("amevcntr03_el0",     CPENC (3,3,C13,C4,3),   0),
> -  SR_AMU ("amevtyper00_el0",    CPENC (3,3,C13,C6,0),   F_REG_READ),
> -  SR_AMU ("amevtyper01_el0",    CPENC (3,3,C13,C6,1),   F_REG_READ),
> -  SR_AMU ("amevtyper02_el0",    CPENC (3,3,C13,C6,2),   F_REG_READ),
> -  SR_AMU ("amevtyper03_el0",    CPENC (3,3,C13,C6,3),   F_REG_READ),
> -  SR_AMU ("amevcntr10_el0",     CPENC (3,3,C13,C12,0),  0),
> -  SR_AMU ("amevcntr11_el0",     CPENC (3,3,C13,C12,1),  0),
> -  SR_AMU ("amevcntr12_el0",     CPENC (3,3,C13,C12,2),  0),
> -  SR_AMU ("amevcntr13_el0",     CPENC (3,3,C13,C12,3),  0),
> -  SR_AMU ("amevcntr14_el0",     CPENC (3,3,C13,C12,4),  0),
> -  SR_AMU ("amevcntr15_el0",     CPENC (3,3,C13,C12,5),  0),
> -  SR_AMU ("amevcntr16_el0",     CPENC (3,3,C13,C12,6),  0),
> -  SR_AMU ("amevcntr17_el0",     CPENC (3,3,C13,C12,7),  0),
> -  SR_AMU ("amevcntr18_el0",     CPENC (3,3,C13,C13,0),  0),
> -  SR_AMU ("amevcntr19_el0",     CPENC (3,3,C13,C13,1),  0),
> -  SR_AMU ("amevcntr110_el0",    CPENC (3,3,C13,C13,2),  0),
> -  SR_AMU ("amevcntr111_el0",    CPENC (3,3,C13,C13,3),  0),
> -  SR_AMU ("amevcntr112_el0",    CPENC (3,3,C13,C13,4),  0),
> -  SR_AMU ("amevcntr113_el0",    CPENC (3,3,C13,C13,5),  0),
> -  SR_AMU ("amevcntr114_el0",    CPENC (3,3,C13,C13,6),  0),
> -  SR_AMU ("amevcntr115_el0",    CPENC (3,3,C13,C13,7),  0),
> -  SR_AMU ("amevtyper10_el0",    CPENC (3,3,C13,C14,0),  0),
> -  SR_AMU ("amevtyper11_el0",    CPENC (3,3,C13,C14,1),  0),
> -  SR_AMU ("amevtyper12_el0",    CPENC (3,3,C13,C14,2),  0),
> -  SR_AMU ("amevtyper13_el0",    CPENC (3,3,C13,C14,3),  0),
> -  SR_AMU ("amevtyper14_el0",    CPENC (3,3,C13,C14,4),  0),
> -  SR_AMU ("amevtyper15_el0",    CPENC (3,3,C13,C14,5),  0),
> -  SR_AMU ("amevtyper16_el0",    CPENC (3,3,C13,C14,6),  0),
> -  SR_AMU ("amevtyper17_el0",    CPENC (3,3,C13,C14,7),  0),
> -  SR_AMU ("amevtyper18_el0",    CPENC (3,3,C13,C15,0),  0),
> -  SR_AMU ("amevtyper19_el0",    CPENC (3,3,C13,C15,1),  0),
> -  SR_AMU ("amevtyper110_el0",   CPENC (3,3,C13,C15,2),  0),
> -  SR_AMU ("amevtyper111_el0",   CPENC (3,3,C13,C15,3),  0),
> -  SR_AMU ("amevtyper112_el0",   CPENC (3,3,C13,C15,4),  0),
> -  SR_AMU ("amevtyper113_el0",   CPENC (3,3,C13,C15,5),  0),
> -  SR_AMU ("amevtyper114_el0",   CPENC (3,3,C13,C15,6),  0),
> -  SR_AMU ("amevtyper115_el0",   CPENC (3,3,C13,C15,7),  0),
> -
> -  SR_GIC ("icc_pmr_el1",        CPENC (3,0,C4,C6,0),    0),
> -  SR_GIC ("icc_iar0_el1",       CPENC (3,0,C12,C8,0),   F_REG_READ),
> -  SR_GIC ("icc_eoir0_el1",      CPENC (3,0,C12,C8,1),   F_REG_WRITE),
> -  SR_GIC ("icc_hppir0_el1",     CPENC (3,0,C12,C8,2),   F_REG_READ),
> -  SR_GIC ("icc_bpr0_el1",       CPENC (3,0,C12,C8,3),   0),
> -  SR_GIC ("icc_ap0r0_el1",      CPENC (3,0,C12,C8,4),   0),
> -  SR_GIC ("icc_ap0r1_el1",      CPENC (3,0,C12,C8,5),   0),
> -  SR_GIC ("icc_ap0r2_el1",      CPENC (3,0,C12,C8,6),   0),
> -  SR_GIC ("icc_ap0r3_el1",      CPENC (3,0,C12,C8,7),   0),
> -  SR_GIC ("icc_ap1r0_el1",      CPENC (3,0,C12,C9,0),   0),
> -  SR_GIC ("icc_ap1r1_el1",      CPENC (3,0,C12,C9,1),   0),
> -  SR_GIC ("icc_ap1r2_el1",      CPENC (3,0,C12,C9,2),   0),
> -  SR_GIC ("icc_ap1r3_el1",      CPENC (3,0,C12,C9,3),   0),
> -  SR_GIC ("icc_dir_el1",        CPENC (3,0,C12,C11,1),  F_REG_WRITE),
> -  SR_GIC ("icc_rpr_el1",        CPENC (3,0,C12,C11,3),  F_REG_READ),
> -  SR_GIC ("icc_sgi1r_el1",      CPENC (3,0,C12,C11,5),  F_REG_WRITE),
> -  SR_GIC ("icc_asgi1r_el1",     CPENC (3,0,C12,C11,6),  F_REG_WRITE),
> -  SR_GIC ("icc_sgi0r_el1",      CPENC (3,0,C12,C11,7),  F_REG_WRITE),
> -  SR_GIC ("icc_iar1_el1",       CPENC (3,0,C12,C12,0),  F_REG_READ),
> -  SR_GIC ("icc_eoir1_el1",      CPENC (3,0,C12,C12,1),  F_REG_WRITE),
> -  SR_GIC ("icc_hppir1_el1",     CPENC (3,0,C12,C12,2),  F_REG_READ),
> -  SR_GIC ("icc_bpr1_el1",       CPENC (3,0,C12,C12,3),  0),
> -  SR_GIC ("icc_ctlr_el1",       CPENC (3,0,C12,C12,4),  0),
> -  SR_GIC ("icc_igrpen0_el1",    CPENC (3,0,C12,C12,6),  0),
> -  SR_GIC ("icc_igrpen1_el1",    CPENC (3,0,C12,C12,7),  0),
> -  SR_GIC ("ich_ap0r0_el2",      CPENC (3,4,C12,C8,0),   0),
> -  SR_GIC ("ich_ap0r1_el2",      CPENC (3,4,C12,C8,1),   0),
> -  SR_GIC ("ich_ap0r2_el2",      CPENC (3,4,C12,C8,2),   0),
> -  SR_GIC ("ich_ap0r3_el2",      CPENC (3,4,C12,C8,3),   0),
> -  SR_GIC ("ich_ap1r0_el2",      CPENC (3,4,C12,C9,0),   0),
> -  SR_GIC ("ich_ap1r1_el2",      CPENC (3,4,C12,C9,1),   0),
> -  SR_GIC ("ich_ap1r2_el2",      CPENC (3,4,C12,C9,2),   0),
> -  SR_GIC ("ich_ap1r3_el2",      CPENC (3,4,C12,C9,3),   0),
> -  SR_GIC ("ich_hcr_el2",        CPENC (3,4,C12,C11,0),  0),
> -  SR_GIC ("ich_misr_el2",       CPENC (3,4,C12,C11,2),  F_REG_READ),
> -  SR_GIC ("ich_eisr_el2",       CPENC (3,4,C12,C11,3),  F_REG_READ),
> -  SR_GIC ("ich_elrsr_el2",      CPENC (3,4,C12,C11,5),  F_REG_READ),
> -  SR_GIC ("ich_vmcr_el2",       CPENC (3,4,C12,C11,7),  0),
> -  SR_GIC ("ich_lr0_el2",        CPENC (3,4,C12,C12,0),  0),
> -  SR_GIC ("ich_lr1_el2",        CPENC (3,4,C12,C12,1),  0),
> -  SR_GIC ("ich_lr2_el2",        CPENC (3,4,C12,C12,2),  0),
> -  SR_GIC ("ich_lr3_el2",        CPENC (3,4,C12,C12,3),  0),
> -  SR_GIC ("ich_lr4_el2",        CPENC (3,4,C12,C12,4),  0),
> -  SR_GIC ("ich_lr5_el2",        CPENC (3,4,C12,C12,5),  0),
> -  SR_GIC ("ich_lr6_el2",        CPENC (3,4,C12,C12,6),  0),
> -  SR_GIC ("ich_lr7_el2",        CPENC (3,4,C12,C12,7),  0),
> -  SR_GIC ("ich_lr8_el2",        CPENC (3,4,C12,C13,0),  0),
> -  SR_GIC ("ich_lr9_el2",        CPENC (3,4,C12,C13,1),  0),
> -  SR_GIC ("ich_lr10_el2",       CPENC (3,4,C12,C13,2),  0),
> -  SR_GIC ("ich_lr11_el2",       CPENC (3,4,C12,C13,3),  0),
> -  SR_GIC ("ich_lr12_el2",       CPENC (3,4,C12,C13,4),  0),
> -  SR_GIC ("ich_lr13_el2",       CPENC (3,4,C12,C13,5),  0),
> -  SR_GIC ("ich_lr14_el2",       CPENC (3,4,C12,C13,6),  0),
> -  SR_GIC ("ich_lr15_el2",       CPENC (3,4,C12,C13,7),  0),
> -  SR_GIC ("icc_igrpen1_el3",    CPENC (3,6,C12,C12,7),  0),
> -
> -  SR_V8_6A ("amcg1idr_el0",      CPENC (3,3,C13,C2,6),   F_REG_READ),
> -  SR_V8_6A ("cntpctss_el0",      CPENC (3,3,C14,C0,5),   F_REG_READ),
> -  SR_V8_6A ("cntvctss_el0",      CPENC (3,3,C14,C0,6),   F_REG_READ),
> -  SR_V8_6A ("hfgrtr_el2",        CPENC (3,4,C1,C1,4),    0),
> -  SR_V8_6A ("hfgwtr_el2",        CPENC (3,4,C1,C1,5),    0),
> -  SR_V8_6A ("hfgitr_el2",        CPENC (3,4,C1,C1,6),    0),
> -  SR_V8_6A ("hdfgrtr_el2",       CPENC (3,4,C3,C1,4),    0),
> -  SR_V8_6A ("hdfgwtr_el2",       CPENC (3,4,C3,C1,5),    0),
> -  SR_V8_6A ("hafgrtr_el2",       CPENC (3,4,C3,C1,6),    0),
> -  SR_V8_6A ("amevcntvoff00_el2", CPENC (3,4,C13,C8,0),   0),
> -  SR_V8_6A ("amevcntvoff01_el2", CPENC (3,4,C13,C8,1),   0),
> -  SR_V8_6A ("amevcntvoff02_el2", CPENC (3,4,C13,C8,2),   0),
> -  SR_V8_6A ("amevcntvoff03_el2", CPENC (3,4,C13,C8,3),   0),
> -  SR_V8_6A ("amevcntvoff04_el2", CPENC (3,4,C13,C8,4),   0),
> -  SR_V8_6A ("amevcntvoff05_el2", CPENC (3,4,C13,C8,5),   0),
> -  SR_V8_6A ("amevcntvoff06_el2", CPENC (3,4,C13,C8,6),   0),
> -  SR_V8_6A ("amevcntvoff07_el2", CPENC (3,4,C13,C8,7),   0),
> -  SR_V8_6A ("amevcntvoff08_el2", CPENC (3,4,C13,C9,0),   0),
> -  SR_V8_6A ("amevcntvoff09_el2", CPENC (3,4,C13,C9,1),   0),
> -  SR_V8_6A ("amevcntvoff010_el2", CPENC (3,4,C13,C9,2),  0),
> -  SR_V8_6A ("amevcntvoff011_el2", CPENC (3,4,C13,C9,3),  0),
> -  SR_V8_6A ("amevcntvoff012_el2", CPENC (3,4,C13,C9,4),  0),
> -  SR_V8_6A ("amevcntvoff013_el2", CPENC (3,4,C13,C9,5),  0),
> -  SR_V8_6A ("amevcntvoff014_el2", CPENC (3,4,C13,C9,6),  0),
> -  SR_V8_6A ("amevcntvoff015_el2", CPENC (3,4,C13,C9,7),  0),
> -  SR_V8_6A ("amevcntvoff10_el2", CPENC (3,4,C13,C10,0),  0),
> -  SR_V8_6A ("amevcntvoff11_el2", CPENC (3,4,C13,C10,1),  0),
> -  SR_V8_6A ("amevcntvoff12_el2", CPENC (3,4,C13,C10,2),  0),
> -  SR_V8_6A ("amevcntvoff13_el2", CPENC (3,4,C13,C10,3),  0),
> -  SR_V8_6A ("amevcntvoff14_el2", CPENC (3,4,C13,C10,4),  0),
> -  SR_V8_6A ("amevcntvoff15_el2", CPENC (3,4,C13,C10,5),  0),
> -  SR_V8_6A ("amevcntvoff16_el2", CPENC (3,4,C13,C10,6),  0),
> -  SR_V8_6A ("amevcntvoff17_el2", CPENC (3,4,C13,C10,7),  0),
> -  SR_V8_6A ("amevcntvoff18_el2", CPENC (3,4,C13,C11,0),  0),
> -  SR_V8_6A ("amevcntvoff19_el2", CPENC (3,4,C13,C11,1),  0),
> -  SR_V8_6A ("amevcntvoff110_el2", CPENC (3,4,C13,C11,2), 0),
> -  SR_V8_6A ("amevcntvoff111_el2", CPENC (3,4,C13,C11,3), 0),
> -  SR_V8_6A ("amevcntvoff112_el2", CPENC (3,4,C13,C11,4), 0),
> -  SR_V8_6A ("amevcntvoff113_el2", CPENC (3,4,C13,C11,5), 0),
> -  SR_V8_6A ("amevcntvoff114_el2", CPENC (3,4,C13,C11,6), 0),
> -  SR_V8_6A ("amevcntvoff115_el2", CPENC (3,4,C13,C11,7), 0),
> -  SR_V8_6A ("cntpoff_el2",       CPENC (3,4,C14,C0,6),   0),
> -
> -  SR_V8_7A ("pmsnevfr_el1",      CPENC (3,0,C9,C9,1),    0),
> -  SR_V8_7A ("hcrx_el2",          CPENC (3,4,C1,C2,2),    0),
> -
> -  SR_V8_8A ("allint",            CPENC (3,0,C4,C3,0),    0),
> -  SR_V8_8A ("icc_nmiar1_el1",    CPENC (3,0,C12,C9,5),   F_REG_READ),
> -
> +#define SYSREG(name, encoding, flags, features) \
> +  { name, encoding, flags, features },
> +#include "aarch64-system-regs.def"
>     { 0, CPENC (0,0,0,0,0), 0, 0 }
> +#undef SYSREG
>   };
>   
>   bool
> @@ -5754,22 +4703,22 @@ aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
>      0b011010 (0x1a).  */
>   const aarch64_sys_reg aarch64_pstatefields [] =
>   {
> -  SR_CORE ("spsel",	  0x05,	F_REG_MAX_VALUE (1)),
> -  SR_CORE ("daifset",	  0x1e,	F_REG_MAX_VALUE (15)),
> -  SR_CORE ("daifclr",	  0x1f,	F_REG_MAX_VALUE (15)),
> -  SR_PAN  ("pan",	  0x04, F_REG_MAX_VALUE (1)),
> -  SR_V8_2A ("uao",	  0x03, F_REG_MAX_VALUE (1)),
> -  SR_SSBS ("ssbs",	  0x19, F_REG_MAX_VALUE (1)),
> -  SR_V8_4A ("dit",	  0x1a,	F_REG_MAX_VALUE (1)),
> -  SR_MEMTAG ("tco",	  0x1c,	F_REG_MAX_VALUE (1)),
> -  SR_SME  ("svcrsm",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x2,0x1)
> -				| F_REG_MAX_VALUE (1)),
> -  SR_SME  ("svcrza",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x4,0x1)
> -				| F_REG_MAX_VALUE (1)),
> -  SR_SME  ("svcrsmza",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1)
> -				| F_REG_MAX_VALUE (1)),
> -  SR_V8_8A ("allint",	  0x08,	F_REG_MAX_VALUE (1)),
> -  { 0,	  CPENC (0,0,0,0,0), 0, 0 },
> +  { "spsel",	 0x05, F_REG_MAX_VALUE (1), AARCH64_FEATURE_CORE },
> +  { "daifset",	 0x1e, F_REG_MAX_VALUE (15), AARCH64_FEATURE_CORE },
> +  { "daifclr",	 0x1f, F_REG_MAX_VALUE (15), AARCH64_FEATURE_CORE },
> +  { "pan",	 0x04, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_PAN },
> +  { "uao",	 0x03, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_V8_2A },
> +  { "ssbs",	 0x19, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_SSBS },
> +  { "dit",	 0x1a, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_V8_4A },
> +  { "tco",	 0x1c, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_MEMTAG },
> +  { "svcrsm",	 0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x2,0x1) | F_REG_MAX_VALUE (1)
> +		       | F_ARCHEXT, AARCH64_FEATURE_SME },
> +  { "svcrza",	 0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x4,0x1) | F_REG_MAX_VALUE (1)
> +		       | F_ARCHEXT, AARCH64_FEATURE_SME },
> +  { "svcrsmza",	 0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x6,0x1) | F_REG_MAX_VALUE (1)
> +		       | F_ARCHEXT, AARCH64_FEATURE_SME },
> +  { "allint",	 0x08, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_V8_8A },
> +  { 0,	  CPENC (0,0,0,0,0), 0, 0 }
>   };
>   
>   bool
> diff --git a/opcodes/aarch64-system-regs.def b/opcodes/aarch64-system-regs.def
> new file mode 100644
> index 00000000000..bf8c488472a
> --- /dev/null
> +++ b/opcodes/aarch64-system-regs.def
> @@ -0,0 +1,1059 @@
> +/* aarch64-system-regs.def -- AArch64 opcode support.
> +   Copyright (C) 2009-2023 Free Software Foundation, Inc.
> +   Contributed by ARM Ltd.
> +
> +   This file is part of the GNU opcodes library.
> +
> +   This library is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3, or (at your option)
> +   any later version.
> +
> +   It is distributed in the hope that it will be useful, but WITHOUT
> +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
> +   License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with this program; see the file COPYING3.  If not,
> +   see <http://www.gnu.org/licenses/>.  */
> +
> +/* Array of system registers and their associated arch features.
> +
> +   Before using #include to read this file, define a macro:
> +
> +     SYSREG (name, encoding, flags, features)
> +
> +  The NAME is the system register name, as recognized by the
> +  assembler.  CPENC provides the necessay information for the binary
> +  encoding of the system register.  The FLAGS field is a bitmask of
> +  operations supported by the particular register.  The ARCH is one of
> +  the ISA flags recognized by the compiler and specifies the
> +  architectural requirements of the system register.  */
> +
> +  SYSREG ("accdata_el1",	CPENC (3,0,13,0,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("actlr_el1",		CPENC (3,0,1,0,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("actlr_el2",		CPENC (3,4,1,0,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("actlr_el3",		CPENC (3,6,1,0,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("afsr0_el1",		CPENC (3,0,5,1,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("afsr0_el12",		CPENC (3,5,5,1,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("afsr0_el2",		CPENC (3,4,5,1,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("afsr0_el3",		CPENC (3,6,5,1,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("afsr1_el1",		CPENC (3,0,5,1,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("afsr1_el12",		CPENC (3,5,5,1,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("afsr1_el2",		CPENC (3,4,5,1,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("afsr1_el3",		CPENC (3,6,5,1,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("aidr_el1",		CPENC (3,1,0,0,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("allint",		CPENC (3,0,4,3,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_8A)
> +  SYSREG ("amair_el1",		CPENC (3,0,10,3,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("amair_el12",		CPENC (3,5,10,3,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("amair_el2",		CPENC (3,4,10,3,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("amair_el3",		CPENC (3,6,10,3,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("amcfgr_el0",		CPENC (3,3,13,2,1),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amcg1idr_el0",	CPENC (3,3,13,2,6),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amcgcr_el0",		CPENC (3,3,13,2,2),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amcntenclr0_el0",	CPENC (3,3,13,2,4),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amcntenclr1_el0",	CPENC (3,3,13,3,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amcntenset0_el0",	CPENC (3,3,13,2,5),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amcntenset1_el0",	CPENC (3,3,13,3,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amcr_el0",		CPENC (3,3,13,2,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr00_el0",	CPENC (3,3,13,4,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr01_el0",	CPENC (3,3,13,4,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr02_el0",	CPENC (3,3,13,4,2),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr03_el0",	CPENC (3,3,13,4,3),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr10_el0",	CPENC (3,3,13,12,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr110_el0",	CPENC (3,3,13,13,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr111_el0",	CPENC (3,3,13,13,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr112_el0",	CPENC (3,3,13,13,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr113_el0",	CPENC (3,3,13,13,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr114_el0",	CPENC (3,3,13,13,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr115_el0",	CPENC (3,3,13,13,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr11_el0",	CPENC (3,3,13,12,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr12_el0",	CPENC (3,3,13,12,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr13_el0",	CPENC (3,3,13,12,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr14_el0",	CPENC (3,3,13,12,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr15_el0",	CPENC (3,3,13,12,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr16_el0",	CPENC (3,3,13,12,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr17_el0",	CPENC (3,3,13,12,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr18_el0",	CPENC (3,3,13,13,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntr19_el0",	CPENC (3,3,13,13,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevcntvoff00_el2",	CPENC (3,4,13,8,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff010_el2",	CPENC (3,4,13,9,2),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff011_el2",	CPENC (3,4,13,9,3),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff012_el2",	CPENC (3,4,13,9,4),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff013_el2",	CPENC (3,4,13,9,5),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff014_el2",	CPENC (3,4,13,9,6),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff015_el2",	CPENC (3,4,13,9,7),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff01_el2",	CPENC (3,4,13,8,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff02_el2",	CPENC (3,4,13,8,2),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff03_el2",	CPENC (3,4,13,8,3),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff04_el2",	CPENC (3,4,13,8,4),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff05_el2",	CPENC (3,4,13,8,5),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff06_el2",	CPENC (3,4,13,8,6),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff07_el2",	CPENC (3,4,13,8,7),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff08_el2",	CPENC (3,4,13,9,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff09_el2",	CPENC (3,4,13,9,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff10_el2",	CPENC (3,4,13,10,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff110_el2",	CPENC (3,4,13,11,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff111_el2",	CPENC (3,4,13,11,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff112_el2",	CPENC (3,4,13,11,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff113_el2",	CPENC (3,4,13,11,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff114_el2",	CPENC (3,4,13,11,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff115_el2",	CPENC (3,4,13,11,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff11_el2",	CPENC (3,4,13,10,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff12_el2",	CPENC (3,4,13,10,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff13_el2",	CPENC (3,4,13,10,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff14_el2",	CPENC (3,4,13,10,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff15_el2",	CPENC (3,4,13,10,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff16_el2",	CPENC (3,4,13,10,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff17_el2",	CPENC (3,4,13,10,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff18_el2",	CPENC (3,4,13,11,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevcntvoff19_el2",	CPENC (3,4,13,11,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("amevtyper00_el0",	CPENC (3,3,13,6,0),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper01_el0",	CPENC (3,3,13,6,1),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper02_el0",	CPENC (3,3,13,6,2),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper03_el0",	CPENC (3,3,13,6,3),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper10_el0",	CPENC (3,3,13,14,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper110_el0",	CPENC (3,3,13,15,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper111_el0",	CPENC (3,3,13,15,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper112_el0",	CPENC (3,3,13,15,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper113_el0",	CPENC (3,3,13,15,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper114_el0",	CPENC (3,3,13,15,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper115_el0",	CPENC (3,3,13,15,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper11_el0",	CPENC (3,3,13,14,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper12_el0",	CPENC (3,3,13,14,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper13_el0",	CPENC (3,3,13,14,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper14_el0",	CPENC (3,3,13,14,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper15_el0",	CPENC (3,3,13,14,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper16_el0",	CPENC (3,3,13,14,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper17_el0",	CPENC (3,3,13,14,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper18_el0",	CPENC (3,3,13,15,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amevtyper19_el0",	CPENC (3,3,13,15,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("amuserenr_el0",	CPENC (3,3,13,2,3),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("apdakeyhi_el1",	CPENC (3,0,2,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apdakeylo_el1",	CPENC (3,0,2,2,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apdbkeyhi_el1",	CPENC (3,0,2,2,3),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apdbkeylo_el1",	CPENC (3,0,2,2,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apgakeyhi_el1",	CPENC (3,0,2,3,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apgakeylo_el1",	CPENC (3,0,2,3,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apiakeyhi_el1",	CPENC (3,0,2,1,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apiakeylo_el1",	CPENC (3,0,2,1,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apibkeyhi_el1",	CPENC (3,0,2,1,3),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("apibkeylo_el1",	CPENC (3,0,2,1,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
> +  SYSREG ("brbcr_el1",		CPENC (2,1,9,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbcr_el12",		CPENC (2,5,9,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbcr_el2",		CPENC (2,4,9,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbfcr_el1",		CPENC (2,1,9,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbidr0_el1",	CPENC (2,1,9,2,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf0_el1",	CPENC (2,1,8,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf10_el1",	CPENC (2,1,8,10,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf11_el1",	CPENC (2,1,8,11,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf12_el1",	CPENC (2,1,8,12,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf13_el1",	CPENC (2,1,8,13,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf14_el1",	CPENC (2,1,8,14,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf15_el1",	CPENC (2,1,8,15,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf16_el1",	CPENC (2,1,8,0,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf17_el1",	CPENC (2,1,8,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf18_el1",	CPENC (2,1,8,2,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf19_el1",	CPENC (2,1,8,3,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf1_el1",	CPENC (2,1,8,1,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf20_el1",	CPENC (2,1,8,4,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf21_el1",	CPENC (2,1,8,5,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf22_el1",	CPENC (2,1,8,6,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf23_el1",	CPENC (2,1,8,7,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf24_el1",	CPENC (2,1,8,8,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf25_el1",	CPENC (2,1,8,9,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf26_el1",	CPENC (2,1,8,10,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf27_el1",	CPENC (2,1,8,11,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf28_el1",	CPENC (2,1,8,12,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf29_el1",	CPENC (2,1,8,13,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf2_el1",	CPENC (2,1,8,2,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf30_el1",	CPENC (2,1,8,14,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf31_el1",	CPENC (2,1,8,15,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf3_el1",	CPENC (2,1,8,3,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf4_el1",	CPENC (2,1,8,4,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf5_el1",	CPENC (2,1,8,5,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf6_el1",	CPENC (2,1,8,6,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf7_el1",	CPENC (2,1,8,7,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf8_el1",	CPENC (2,1,8,8,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinf9_el1",	CPENC (2,1,8,9,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbinfinj_el1",	CPENC (2,1,9,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc0_el1",	CPENC (2,1,8,0,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc10_el1",	CPENC (2,1,8,10,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc11_el1",	CPENC (2,1,8,11,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc12_el1",	CPENC (2,1,8,12,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc13_el1",	CPENC (2,1,8,13,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc14_el1",	CPENC (2,1,8,14,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc15_el1",	CPENC (2,1,8,15,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc16_el1",	CPENC (2,1,8,0,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc17_el1",	CPENC (2,1,8,1,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc18_el1",	CPENC (2,1,8,2,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc19_el1",	CPENC (2,1,8,3,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc1_el1",	CPENC (2,1,8,1,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc20_el1",	CPENC (2,1,8,4,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc21_el1",	CPENC (2,1,8,5,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc22_el1",	CPENC (2,1,8,6,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc23_el1",	CPENC (2,1,8,7,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc24_el1",	CPENC (2,1,8,8,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc25_el1",	CPENC (2,1,8,9,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc26_el1",	CPENC (2,1,8,10,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc27_el1",	CPENC (2,1,8,11,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc28_el1",	CPENC (2,1,8,12,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc29_el1",	CPENC (2,1,8,13,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc2_el1",	CPENC (2,1,8,2,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc30_el1",	CPENC (2,1,8,14,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc31_el1",	CPENC (2,1,8,15,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc3_el1",	CPENC (2,1,8,3,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc4_el1",	CPENC (2,1,8,4,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc5_el1",	CPENC (2,1,8,5,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc6_el1",	CPENC (2,1,8,6,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc7_el1",	CPENC (2,1,8,7,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc8_el1",	CPENC (2,1,8,8,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrc9_el1",	CPENC (2,1,8,9,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbsrcinj_el1",	CPENC (2,1,9,1,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt0_el1",	CPENC (2,1,8,0,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt10_el1",	CPENC (2,1,8,10,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt11_el1",	CPENC (2,1,8,11,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt12_el1",	CPENC (2,1,8,12,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt13_el1",	CPENC (2,1,8,13,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt14_el1",	CPENC (2,1,8,14,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt15_el1",	CPENC (2,1,8,15,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt16_el1",	CPENC (2,1,8,0,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt17_el1",	CPENC (2,1,8,1,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt18_el1",	CPENC (2,1,8,2,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt19_el1",	CPENC (2,1,8,3,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt1_el1",	CPENC (2,1,8,1,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt20_el1",	CPENC (2,1,8,4,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt21_el1",	CPENC (2,1,8,5,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt22_el1",	CPENC (2,1,8,6,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt23_el1",	CPENC (2,1,8,7,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt24_el1",	CPENC (2,1,8,8,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt25_el1",	CPENC (2,1,8,9,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt26_el1",	CPENC (2,1,8,10,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt27_el1",	CPENC (2,1,8,11,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt28_el1",	CPENC (2,1,8,12,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt29_el1",	CPENC (2,1,8,13,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt2_el1",	CPENC (2,1,8,2,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt30_el1",	CPENC (2,1,8,14,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt31_el1",	CPENC (2,1,8,15,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt3_el1",	CPENC (2,1,8,3,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt4_el1",	CPENC (2,1,8,4,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt5_el1",	CPENC (2,1,8,5,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt6_el1",	CPENC (2,1,8,6,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt7_el1",	CPENC (2,1,8,7,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt8_el1",	CPENC (2,1,8,8,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgt9_el1",	CPENC (2,1,8,9,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("brbtgtinj_el1",	CPENC (2,1,9,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("brbts_el1",		CPENC (2,1,9,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ccsidr2_el1",	CPENC (3,1,0,0,2),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_3A)
> +  SYSREG ("ccsidr_el1",		CPENC (3,1,0,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("clidr_el1",		CPENC (3,1,0,0,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("cntfrq_el0",		CPENC (3,3,14,0,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cnthctl_el2",	CPENC (3,4,14,1,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cnthp_ctl_el2",	CPENC (3,4,14,2,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cnthp_cval_el2",	CPENC (3,4,14,2,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cnthp_tval_el2",	CPENC (3,4,14,2,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cnthps_ctl_el2",	CPENC (3,4,14,5,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("cnthps_cval_el2",	CPENC (3,4,14,5,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("cnthps_tval_el2",	CPENC (3,4,14,5,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("cnthv_ctl_el2",	CPENC (3,4,14,3,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cnthv_cval_el2",	CPENC (3,4,14,3,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cnthv_tval_el2",	CPENC (3,4,14,3,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cnthvs_ctl_el2",	CPENC (3,4,14,4,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("cnthvs_cval_el2",	CPENC (3,4,14,4,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("cnthvs_tval_el2",	CPENC (3,4,14,4,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("cntkctl_el1",	CPENC (3,0,14,1,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntkctl_el12",	CPENC (3,5,14,1,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntp_ctl_el0",	CPENC (3,3,14,2,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntp_ctl_el02",	CPENC (3,5,14,2,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntp_cval_el0",	CPENC (3,3,14,2,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntp_cval_el02",	CPENC (3,5,14,2,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntp_tval_el0",	CPENC (3,3,14,2,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntp_tval_el02",	CPENC (3,5,14,2,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntpct_el0",		CPENC (3,3,14,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("cntpctss_el0",	CPENC (3,3,14,0,5),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_6A)
> +  SYSREG ("cntpoff_el2",	CPENC (3,4,14,0,6),      F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("cntps_ctl_el1",	CPENC (3,7,14,2,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntps_cval_el1",	CPENC (3,7,14,2,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntps_tval_el1",	CPENC (3,7,14,2,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntv_ctl_el0",	CPENC (3,3,14,3,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntv_ctl_el02",	CPENC (3,5,14,3,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntv_cval_el0",	CPENC (3,3,14,3,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntv_cval_el02",	CPENC (3,5,14,3,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntv_tval_el0",	CPENC (3,3,14,3,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cntv_tval_el02",	CPENC (3,5,14,3,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cntvct_el0",		CPENC (3,3,14,0,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("cntvctss_el0",	CPENC (3,3,14,0,6),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_6A)
> +  SYSREG ("cntvoff_el2",	CPENC (3,4,14,0,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("contextidr_el1",	CPENC (3,0,13,0,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("contextidr_el12",	CPENC (3,5,13,0,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("contextidr_el2",	CPENC (3,4,13,0,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cpacr_el1",		CPENC (3,0,1,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cpacr_el12",		CPENC (3,5,1,0,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("cptr_el2",		CPENC (3,4,1,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("cptr_el3",		CPENC (3,6,1,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrcr_el0",		CPENC (2,3,8,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrcr_el1",		CPENC (2,0,8,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrcr_el12",		CPENC (2,5,8,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrcr_el2",		CPENC (2,4,8,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csridr_el0",		CPENC (2,3,8,0,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptr_el0",		CPENC (2,3,8,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptr_el1",		CPENC (2,0,8,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptr_el12",	CPENC (2,5,8,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptr_el2",		CPENC (2,4,8,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptridx_el0",	CPENC (2,3,8,0,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptridx_el1",	CPENC (2,0,8,0,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("csrptridx_el2",	CPENC (2,4,8,0,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("csselr_el1",		CPENC (3,2,0,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ctr_el0",		CPENC (3,3,0,0,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("currentel",		CPENC (3,0,4,2,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("dacr32_el2",		CPENC (3,4,3,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("daif",		CPENC (3,3,4,2,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgauthstatus_el1",	CPENC (2,0,7,14,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr0_el1",	CPENC (2,0,0,0,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr10_el1",	CPENC (2,0,0,10,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr11_el1",	CPENC (2,0,0,11,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr12_el1",	CPENC (2,0,0,12,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr13_el1",	CPENC (2,0,0,13,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr14_el1",	CPENC (2,0,0,14,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr15_el1",	CPENC (2,0,0,15,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr1_el1",	CPENC (2,0,0,1,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr2_el1",	CPENC (2,0,0,2,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr3_el1",	CPENC (2,0,0,3,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr4_el1",	CPENC (2,0,0,4,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr5_el1",	CPENC (2,0,0,5,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr6_el1",	CPENC (2,0,0,6,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr7_el1",	CPENC (2,0,0,7,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr8_el1",	CPENC (2,0,0,8,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbcr9_el1",	CPENC (2,0,0,9,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr0_el1",	CPENC (2,0,0,0,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr10_el1",	CPENC (2,0,0,10,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr11_el1",	CPENC (2,0,0,11,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr12_el1",	CPENC (2,0,0,12,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr13_el1",	CPENC (2,0,0,13,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr14_el1",	CPENC (2,0,0,14,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr15_el1",	CPENC (2,0,0,15,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr1_el1",	CPENC (2,0,0,1,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr2_el1",	CPENC (2,0,0,2,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr3_el1",	CPENC (2,0,0,3,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr4_el1",	CPENC (2,0,0,4,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr5_el1",	CPENC (2,0,0,5,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr6_el1",	CPENC (2,0,0,6,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr7_el1",	CPENC (2,0,0,7,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr8_el1",	CPENC (2,0,0,8,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgbvr9_el1",	CPENC (2,0,0,9,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgclaimclr_el1",	CPENC (2,0,7,9,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgclaimset_el1",	CPENC (2,0,7,8,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgdtr_el0",		CPENC (2,3,0,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgdtrrx_el0",	CPENC (2,3,0,5,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgdtrtx_el0",	CPENC (2,3,0,5,0),       F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgprcr_el1",	CPENC (2,0,1,4,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgvcr32_el2",	CPENC (2,4,0,7,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr0_el1",	CPENC (2,0,0,0,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr10_el1",	CPENC (2,0,0,10,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr11_el1",	CPENC (2,0,0,11,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr12_el1",	CPENC (2,0,0,12,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr13_el1",	CPENC (2,0,0,13,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr14_el1",	CPENC (2,0,0,14,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr15_el1",	CPENC (2,0,0,15,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr1_el1",	CPENC (2,0,0,1,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr2_el1",	CPENC (2,0,0,2,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr3_el1",	CPENC (2,0,0,3,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr4_el1",	CPENC (2,0,0,4,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr5_el1",	CPENC (2,0,0,5,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr6_el1",	CPENC (2,0,0,6,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr7_el1",	CPENC (2,0,0,7,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr8_el1",	CPENC (2,0,0,8,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwcr9_el1",	CPENC (2,0,0,9,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr0_el1",	CPENC (2,0,0,0,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr10_el1",	CPENC (2,0,0,10,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr11_el1",	CPENC (2,0,0,11,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr12_el1",	CPENC (2,0,0,12,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr13_el1",	CPENC (2,0,0,13,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr14_el1",	CPENC (2,0,0,14,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr15_el1",	CPENC (2,0,0,15,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr1_el1",	CPENC (2,0,0,1,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr2_el1",	CPENC (2,0,0,2,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr3_el1",	CPENC (2,0,0,3,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr4_el1",	CPENC (2,0,0,4,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr5_el1",	CPENC (2,0,0,5,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr6_el1",	CPENC (2,0,0,6,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr7_el1",	CPENC (2,0,0,7,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr8_el1",	CPENC (2,0,0,8,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dbgwvr9_el1",	CPENC (2,0,0,9,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dczid_el0",		CPENC (3,3,0,0,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("disr_el1",		CPENC (3,0,12,1,1),      F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("dit",		CPENC (3,3,4,2,5),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("dlr_el0",		CPENC (3,3,4,5,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("dspsr_el0",		CPENC (3,3,4,5,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("elr_el1",		CPENC (3,0,4,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("elr_el12",		CPENC (3,5,4,0,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("elr_el2",		CPENC (3,4,4,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("elr_el3",		CPENC (3,6,4,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("erridr_el1",		CPENC (3,0,5,3,0),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RAS)
> +  SYSREG ("errselr_el1",	CPENC (3,0,5,3,1),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxaddr_el1",	CPENC (3,0,5,4,3),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxctlr_el1",	CPENC (3,0,5,4,1),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxfr_el1",		CPENC (3,0,5,4,0),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RAS)
> +  SYSREG ("erxmisc0_el1",	CPENC (3,0,5,5,0),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxmisc1_el1",	CPENC (3,0,5,5,1),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxmisc2_el1",	CPENC (3,0,5,5,2),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxmisc3_el1",	CPENC (3,0,5,5,3),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxpfgcdn_el1",	CPENC (3,0,5,4,6),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxpfgctl_el1",	CPENC (3,0,5,4,5),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("erxpfgf_el1",	CPENC (3,0,5,4,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RAS)
> +  SYSREG ("erxstatus_el1",	CPENC (3,0,5,4,2),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("esr_el1",		CPENC (3,0,5,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("esr_el12",		CPENC (3,5,5,2,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("esr_el2",		CPENC (3,4,5,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("esr_el3",		CPENC (3,6,5,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("far_el1",		CPENC (3,0,6,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("far_el12",		CPENC (3,5,6,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("far_el2",		CPENC (3,4,6,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("far_el3",		CPENC (3,6,6,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("fpcr",		CPENC (3,3,4,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("fpexc32_el2",	CPENC (3,4,5,3,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("fpsr",		CPENC (3,3,4,4,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("gcr_el1",		CPENC (3,0,1,0,6),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("gmid_el1",		CPENC (3,1,0,0,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("gpccr_el3",		CPENC (3,6,2,1,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("gptbr_el3",		CPENC (3,6,2,1,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("hacr_el2",		CPENC (3,4,1,1,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("hafgrtr_el2",	CPENC (3,4,3,1,6),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("hcr_el2",		CPENC (3,4,1,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("hcrx_el2",		CPENC (3,4,1,2,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_7A)
> +  SYSREG ("hdfgrtr_el2",	CPENC (3,4,3,1,4),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("hdfgwtr_el2",	CPENC (3,4,3,1,5),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("hfgitr_el2",		CPENC (3,4,1,1,6),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("hfgrtr_el2",		CPENC (3,4,1,1,4),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("hfgwtr_el2",		CPENC (3,4,1,1,5),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
> +  SYSREG ("hpfar_el2",		CPENC (3,4,6,0,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("hstr_el2",		CPENC (3,4,1,1,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap0r0_el1",	CPENC (3,0,12,8,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap0r1_el1",	CPENC (3,0,12,8,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap0r2_el1",	CPENC (3,0,12,8,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap0r3_el1",	CPENC (3,0,12,8,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap1r0_el1",	CPENC (3,0,12,9,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap1r1_el1",	CPENC (3,0,12,9,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap1r2_el1",	CPENC (3,0,12,9,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ap1r3_el1",	CPENC (3,0,12,9,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_asgi1r_el1",	CPENC (3,0,12,11,6),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_bpr0_el1",	CPENC (3,0,12,8,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_bpr1_el1",	CPENC (3,0,12,12,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ctlr_el1",	CPENC (3,0,12,12,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_ctlr_el3",	CPENC (3,6,12,12,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_dir_el1",	CPENC (3,0,12,11,1),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_eoir0_el1",	CPENC (3,0,12,8,1),      F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_eoir1_el1",	CPENC (3,0,12,12,1),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_hppir0_el1",	CPENC (3,0,12,8,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_hppir1_el1",	CPENC (3,0,12,12,2),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_iar0_el1",	CPENC (3,0,12,8,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_iar1_el1",	CPENC (3,0,12,12,0),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_igrpen0_el1",	CPENC (3,0,12,12,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_igrpen1_el1",	CPENC (3,0,12,12,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_igrpen1_el3",	CPENC (3,6,12,12,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_nmiar1_el1",	CPENC (3,0,12,9,5),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_8A)
> +  SYSREG ("icc_pmr_el1",	CPENC (3,0,4,6,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_rpr_el1",	CPENC (3,0,12,11,3),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_sgi0r_el1",	CPENC (3,0,12,11,7),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_sgi1r_el1",	CPENC (3,0,12,11,5),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_sre_el1",	CPENC (3,0,12,12,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_sre_el2",	CPENC (3,4,12,9,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("icc_sre_el3",	CPENC (3,6,12,12,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap0r0_el2",	CPENC (3,4,12,8,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap0r1_el2",	CPENC (3,4,12,8,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap0r2_el2",	CPENC (3,4,12,8,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap0r3_el2",	CPENC (3,4,12,8,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap1r0_el2",	CPENC (3,4,12,9,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap1r1_el2",	CPENC (3,4,12,9,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap1r2_el2",	CPENC (3,4,12,9,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_ap1r3_el2",	CPENC (3,4,12,9,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_eisr_el2",	CPENC (3,4,12,11,3),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_elrsr_el2",	CPENC (3,4,12,11,5),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_hcr_el2",	CPENC (3,4,12,11,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr0_el2",	CPENC (3,4,12,12,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr10_el2",	CPENC (3,4,12,13,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr11_el2",	CPENC (3,4,12,13,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr12_el2",	CPENC (3,4,12,13,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr13_el2",	CPENC (3,4,12,13,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr14_el2",	CPENC (3,4,12,13,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr15_el2",	CPENC (3,4,12,13,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr1_el2",	CPENC (3,4,12,12,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr2_el2",	CPENC (3,4,12,12,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr3_el2",	CPENC (3,4,12,12,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr4_el2",	CPENC (3,4,12,12,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr5_el2",	CPENC (3,4,12,12,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr6_el2",	CPENC (3,4,12,12,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr7_el2",	CPENC (3,4,12,12,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr8_el2",	CPENC (3,4,12,13,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_lr9_el2",	CPENC (3,4,12,13,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_misr_el2",	CPENC (3,4,12,11,2),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_vmcr_el2",	CPENC (3,4,12,11,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ich_vtr_el2",	CPENC (3,4,12,11,1),     F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64afr0_el1",	CPENC (3,0,0,5,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64afr1_el1",	CPENC (3,0,0,5,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64dfr0_el1",	CPENC (3,0,0,5,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64dfr1_el1",	CPENC (3,0,0,5,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64isar0_el1",	CPENC (3,0,0,6,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64isar1_el1",	CPENC (3,0,0,6,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64isar2_el1",	CPENC (3,0,0,6,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64mmfr0_el1",	CPENC (3,0,0,7,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64mmfr1_el1",	CPENC (3,0,0,7,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64mmfr2_el1",	CPENC (3,0,0,7,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64pfr0_el1",	CPENC (3,0,0,4,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64pfr1_el1",	CPENC (3,0,0,4,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_aa64smfr0_el1",	CPENC (3,0,0,4,5),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_SME)
> +  SYSREG ("id_aa64zfr0_el1",	CPENC (3,0,0,4,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_SVE)
> +  SYSREG ("id_afr0_el1",	CPENC (3,0,0,1,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_dfr0_el1",	CPENC (3,0,0,1,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_dfr1_el1",	CPENC (3,0,0,3,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar0_el1",	CPENC (3,0,0,2,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar1_el1",	CPENC (3,0,0,2,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar2_el1",	CPENC (3,0,0,2,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar3_el1",	CPENC (3,0,0,2,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar4_el1",	CPENC (3,0,0,2,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar5_el1",	CPENC (3,0,0,2,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_isar6_el1",	CPENC (3,0,0,2,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_mmfr0_el1",	CPENC (3,0,0,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_mmfr1_el1",	CPENC (3,0,0,1,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_mmfr2_el1",	CPENC (3,0,0,1,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_mmfr3_el1",	CPENC (3,0,0,1,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_mmfr4_el1",	CPENC (3,0,0,2,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_mmfr5_el1",	CPENC (3,0,0,3,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_pfr0_el1",	CPENC (3,0,0,1,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_pfr1_el1",	CPENC (3,0,0,1,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("id_pfr2_el1",	CPENC (3,0,0,3,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_ID_PFR2)
> +  SYSREG ("ifsr32_el2",		CPENC (3,4,5,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("isr_el1",		CPENC (3,0,12,1,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("lorc_el1",		CPENC (3,0,10,4,3),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
> +  SYSREG ("lorea_el1",		CPENC (3,0,10,4,1),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
> +  SYSREG ("lorid_el1",		CPENC (3,0,10,4,7),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_LOR)
> +  SYSREG ("lorn_el1",		CPENC (3,0,10,4,2),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
> +  SYSREG ("lorsa_el1",		CPENC (3,0,10,4,0),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
> +  SYSREG ("mair_el1",		CPENC (3,0,10,2,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mair_el12",		CPENC (3,5,10,2,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("mair_el2",		CPENC (3,4,10,2,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mair_el3",		CPENC (3,6,10,2,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mdccint_el1",	CPENC (2,0,0,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mdccsr_el0",		CPENC (2,3,0,1,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mdcr_el2",		CPENC (3,4,1,1,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mdcr_el3",		CPENC (3,6,1,3,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mdrar_el1",		CPENC (2,0,1,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mdscr_el1",		CPENC (2,0,0,2,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mecid_a0_el2",	CPENC (3,4,10,8,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mecid_a1_el2",	CPENC (3,4,10,8,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mecid_p0_el2",	CPENC (3,4,10,8,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mecid_p1_el2",	CPENC (3,4,10,8,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mecid_rl_a_el3",	CPENC (3,6,10,10,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mecidr_el2",		CPENC (3,4,10,8,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mfar_el3",		CPENC (3,6,6,0,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("midr_el1",		CPENC (3,0,0,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mpam0_el1",		CPENC (3,0,10,5,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpam1_el1",		CPENC (3,0,10,5,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpam1_el12",		CPENC (3,5,10,5,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpam2_el2",		CPENC (3,4,10,5,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpam3_el3",		CPENC (3,6,10,5,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),      F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("mpamvpm0_el2",	CPENC (3,4,10,6,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm1_el2",	CPENC (3,4,10,6,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm2_el2",	CPENC (3,4,10,6,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm3_el2",	CPENC (3,4,10,6,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm4_el2",	CPENC (3,4,10,6,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm5_el2",	CPENC (3,4,10,6,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm6_el2",	CPENC (3,4,10,6,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpm7_el2",	CPENC (3,4,10,6,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpamvpmv_el2",	CPENC (3,4,10,4,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("mpidr_el1",		CPENC (3,0,0,0,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mpuir_el1",		CPENC (3,0,0,0,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8R)
> +  SYSREG ("mpuir_el2",		CPENC (3,4,0,0,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8R)
> +  SYSREG ("mvfr0_el1",		CPENC (3,0,0,3,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mvfr1_el1",		CPENC (3,0,0,3,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("mvfr2_el1",		CPENC (3,0,0,3,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("nzcv",		CPENC (3,3,4,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("osdlr_el1",		CPENC (2,0,1,3,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("osdtrrx_el1",	CPENC (2,0,0,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("osdtrtx_el1",	CPENC (2,0,0,3,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("oseccr_el1",		CPENC (2,0,0,6,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("oslar_el1",		CPENC (2,0,1,0,4),       F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("oslsr_el1",		CPENC (2,0,1,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("pan",		CPENC (3,0,4,2,3),       F_ARCHEXT,		AARCH64_FEATURE_PAN)
> +  SYSREG ("par_el1",		CPENC (3,0,7,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmbidr_el1",		CPENC (3,0,9,10,7),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmblimitr_el1",	CPENC (3,0,9,10,0),      F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmbptr_el1",		CPENC (3,0,9,10,1),      F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmbsr_el1",		CPENC (3,0,9,10,3),      F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmccfiltr_el0",	CPENC (3,3,14,15,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmccntr_el0",	CPENC (3,3,9,13,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmceid0_el0",	CPENC (3,3,9,12,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("pmceid1_el0",	CPENC (3,3,9,12,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("pmcntenclr_el0",	CPENC (3,3,9,12,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmcntenset_el0",	CPENC (3,3,9,12,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmcr_el0",		CPENC (3,3,9,12,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr0_el0",	CPENC (3,3,14,8,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr10_el0",	CPENC (3,3,14,9,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr11_el0",	CPENC (3,3,14,9,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr12_el0",	CPENC (3,3,14,9,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr13_el0",	CPENC (3,3,14,9,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr14_el0",	CPENC (3,3,14,9,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr15_el0",	CPENC (3,3,14,9,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr16_el0",	CPENC (3,3,14,10,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr17_el0",	CPENC (3,3,14,10,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr18_el0",	CPENC (3,3,14,10,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr19_el0",	CPENC (3,3,14,10,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr1_el0",	CPENC (3,3,14,8,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr20_el0",	CPENC (3,3,14,10,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr21_el0",	CPENC (3,3,14,10,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr22_el0",	CPENC (3,3,14,10,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr23_el0",	CPENC (3,3,14,10,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr24_el0",	CPENC (3,3,14,11,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr25_el0",	CPENC (3,3,14,11,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr26_el0",	CPENC (3,3,14,11,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr27_el0",	CPENC (3,3,14,11,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr28_el0",	CPENC (3,3,14,11,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr29_el0",	CPENC (3,3,14,11,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr2_el0",	CPENC (3,3,14,8,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr30_el0",	CPENC (3,3,14,11,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr3_el0",	CPENC (3,3,14,8,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr4_el0",	CPENC (3,3,14,8,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr5_el0",	CPENC (3,3,14,8,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr6_el0",	CPENC (3,3,14,8,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr7_el0",	CPENC (3,3,14,8,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr8_el0",	CPENC (3,3,14,9,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevcntr9_el0",	CPENC (3,3,14,9,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper0_el0",	CPENC (3,3,14,12,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper10_el0",	CPENC (3,3,14,13,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper11_el0",	CPENC (3,3,14,13,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper12_el0",	CPENC (3,3,14,13,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper13_el0",	CPENC (3,3,14,13,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper14_el0",	CPENC (3,3,14,13,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper15_el0",	CPENC (3,3,14,13,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper16_el0",	CPENC (3,3,14,14,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper17_el0",	CPENC (3,3,14,14,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper18_el0",	CPENC (3,3,14,14,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper19_el0",	CPENC (3,3,14,14,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper1_el0",	CPENC (3,3,14,12,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper20_el0",	CPENC (3,3,14,14,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper21_el0",	CPENC (3,3,14,14,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper22_el0",	CPENC (3,3,14,14,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper23_el0",	CPENC (3,3,14,14,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper24_el0",	CPENC (3,3,14,15,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper25_el0",	CPENC (3,3,14,15,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper26_el0",	CPENC (3,3,14,15,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper27_el0",	CPENC (3,3,14,15,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper28_el0",	CPENC (3,3,14,15,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper29_el0",	CPENC (3,3,14,15,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper2_el0",	CPENC (3,3,14,12,2),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper30_el0",	CPENC (3,3,14,15,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper3_el0",	CPENC (3,3,14,12,3),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper4_el0",	CPENC (3,3,14,12,4),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper5_el0",	CPENC (3,3,14,12,5),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper6_el0",	CPENC (3,3,14,12,6),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper7_el0",	CPENC (3,3,14,12,7),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper8_el0",	CPENC (3,3,14,13,0),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmevtyper9_el0",	CPENC (3,3,14,13,1),     0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmintenclr_el1",	CPENC (3,0,9,14,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmintenset_el1",	CPENC (3,0,9,14,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmmir_el1",		CPENC (3,0,9,14,6),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
> +  SYSREG ("pmovsclr_el0",	CPENC (3,3,9,12,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmovsset_el0",	CPENC (3,3,9,14,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmscr_el12",		CPENC (3,5,9,9,0),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmscr_el2",		CPENC (3,4,9,9,0),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmscr_el1",		CPENC (3,0,9,9,0),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmselr_el0",		CPENC (3,3,9,12,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmsevfr_el1",	CPENC (3,0,9,9,5),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmsfcr_el1",		CPENC (3,0,9,9,4),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmsicr_el1",		CPENC (3,0,9,9,2),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmsidr_el1",		CPENC (3,0,9,9,7),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmsirr_el1",		CPENC (3,0,9,9,3),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmslatfr_el1",	CPENC (3,0,9,9,6),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
> +  SYSREG ("pmsnevfr_el1",	CPENC (3,0,9,9,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_7A)
> +  SYSREG ("pmswinc_el0",	CPENC (3,3,9,12,4),      F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("pmuserenr_el0",	CPENC (3,3,9,14,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmxevcntr_el0",	CPENC (3,3,9,13,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("pmxevtyper_el0",	CPENC (3,3,9,13,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("prbar10_el1",	CPENC (3,0,6,13,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar10_el2",	CPENC (3,4,6,13,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar11_el1",	CPENC (3,0,6,13,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar11_el2",	CPENC (3,4,6,13,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar12_el1",	CPENC (3,0,6,14,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar12_el2",	CPENC (3,4,6,14,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar13_el1",	CPENC (3,0,6,14,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar13_el2",	CPENC (3,4,6,14,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar14_el1",	CPENC (3,0,6,15,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar14_el2",	CPENC (3,4,6,15,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar15_el1",	CPENC (3,0,6,15,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar15_el2",	CPENC (3,4,6,15,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar1_el1",		CPENC (3,0,6,8,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar1_el2",		CPENC (3,4,6,8,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar2_el1",		CPENC (3,0,6,9,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar2_el2",		CPENC (3,4,6,9,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar3_el1",		CPENC (3,0,6,9,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar3_el2",		CPENC (3,4,6,9,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar4_el1",		CPENC (3,0,6,10,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar4_el2",		CPENC (3,4,6,10,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar5_el1",		CPENC (3,0,6,10,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar5_el2",		CPENC (3,4,6,10,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar6_el1",		CPENC (3,0,6,11,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar6_el2",		CPENC (3,4,6,11,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar7_el1",		CPENC (3,0,6,11,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar7_el2",		CPENC (3,4,6,11,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar8_el1",		CPENC (3,0,6,12,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar8_el2",		CPENC (3,4,6,12,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar9_el1",		CPENC (3,0,6,12,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar9_el2",		CPENC (3,4,6,12,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar_el1",		CPENC (3,0,6,8,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prbar_el2",		CPENC (3,4,6,8,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prenr_el1",		CPENC (3,0,6,1,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prenr_el2",		CPENC (3,4,6,1,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar10_el1",	CPENC (3,0,6,13,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar10_el2",	CPENC (3,4,6,13,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar11_el1",	CPENC (3,0,6,13,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar11_el2",	CPENC (3,4,6,13,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar12_el1",	CPENC (3,0,6,14,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar12_el2",	CPENC (3,4,6,14,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar13_el1",	CPENC (3,0,6,14,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar13_el2",	CPENC (3,4,6,14,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar14_el1",	CPENC (3,0,6,15,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar14_el2",	CPENC (3,4,6,15,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar15_el1",	CPENC (3,0,6,15,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar15_el2",	CPENC (3,4,6,15,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar1_el1",		CPENC (3,0,6,8,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar1_el2",		CPENC (3,4,6,8,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar2_el1",		CPENC (3,0,6,9,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar2_el2",		CPENC (3,4,6,9,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar3_el1",		CPENC (3,0,6,9,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar3_el2",		CPENC (3,4,6,9,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar4_el1",		CPENC (3,0,6,10,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar4_el2",		CPENC (3,4,6,10,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar5_el1",		CPENC (3,0,6,10,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar5_el2",		CPENC (3,4,6,10,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar6_el1",		CPENC (3,0,6,11,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar6_el2",		CPENC (3,4,6,11,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar7_el1",		CPENC (3,0,6,11,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar7_el2",		CPENC (3,4,6,11,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar8_el1",		CPENC (3,0,6,12,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar8_el2",		CPENC (3,4,6,12,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar9_el1",		CPENC (3,0,6,12,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar9_el2",		CPENC (3,4,6,12,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar_el1",		CPENC (3,0,6,8,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prlar_el2",		CPENC (3,4,6,8,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prselr_el1",		CPENC (3,0,6,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("prselr_el2",		CPENC (3,4,6,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("revidr_el1",		CPENC (3,0,0,0,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("rgsr_el1",		CPENC (3,0,1,0,5),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("rmr_el1",		CPENC (3,0,12,0,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("rmr_el2",		CPENC (3,4,12,0,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("rmr_el3",		CPENC (3,6,12,0,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("rndr",		CPENC (3,3,2,4,0),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RNG)
> +  SYSREG ("rndrrs",		CPENC (3,3,2,4,1),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RNG)
> +  SYSREG ("rvbar_el1",		CPENC (3,0,12,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("rvbar_el2",		CPENC (3,4,12,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("rvbar_el3",		CPENC (3,6,12,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("scr_el3",		CPENC (3,6,1,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("sctlr_el1",		CPENC (3,0,1,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("sctlr_el12",		CPENC (3,5,1,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("sctlr_el2",		CPENC (3,4,1,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("sctlr_el3",		CPENC (3,6,1,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("scxtnum_el0",	CPENC (3,3,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
> +  SYSREG ("scxtnum_el1",	CPENC (3,0,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
> +  SYSREG ("scxtnum_el12",	CPENC (3,5,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
> +  SYSREG ("scxtnum_el2",	CPENC (3,4,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
> +  SYSREG ("scxtnum_el3",	CPENC (3,6,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
> +  SYSREG ("sder32_el2",		CPENC (3,4,1,3,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("sder32_el3",		CPENC (3,6,1,1,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("smcr_el1",		CPENC (3,0,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("smcr_el12",		CPENC (3,5,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("smcr_el2",		CPENC (3,4,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("smcr_el3",		CPENC (3,6,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("smidr_el1",		CPENC (3,1,0,0,6),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_SME)
> +  SYSREG ("smpri_el1",		CPENC (3,0,1,2,4),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("smprimap_el2",	CPENC (3,4,1,2,5),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("sp_el0",		CPENC (3,0,4,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("sp_el1",		CPENC (3,4,4,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("sp_el2",		CPENC (3,6,4,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsel",		CPENC (3,0,4,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_abt",		CPENC (3,4,4,3,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_el1",		CPENC (3,0,4,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_el12",		CPENC (3,5,4,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("spsr_el2",		CPENC (3,4,4,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_el3",		CPENC (3,6,4,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_fiq",		CPENC (3,4,4,3,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_hyp",		CPENC (3,4,4,0,0),       F_DEPRECATED,		AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_irq",		CPENC (3,4,4,3,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_svc",		CPENC (3,0,4,0,0),       F_DEPRECATED,		AARCH64_FEATURE_CORE)
> +  SYSREG ("spsr_und",		CPENC (3,4,4,3,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ssbs",		CPENC (3,3,4,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SSBS)
> +  SYSREG ("svcr",		CPENC (3,3,4,2,2),       F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("tco",		CPENC (3,3,4,2,7),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("tcr_el1",		CPENC (3,0,2,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tcr_el12",		CPENC (3,5,2,0,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("tcr_el2",		CPENC (3,4,2,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tcr_el3",		CPENC (3,6,2,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("teecr32_el1",	CPENC (2,2,0,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("teehbr32_el1",	CPENC (2,2,1,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tfsr_el1",		CPENC (3,0,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("tfsr_el12",		CPENC (3,5,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("tfsr_el2",		CPENC (3,4,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("tfsr_el3",		CPENC (3,6,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("tfsre0_el1",		CPENC (3,0,5,6,1),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
> +  SYSREG ("tpidr2_el0",		CPENC (3,3,13,0,5),      F_ARCHEXT,		AARCH64_FEATURE_SME)
> +  SYSREG ("tpidr_el0",		CPENC (3,3,13,0,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tpidr_el1",		CPENC (3,0,13,0,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tpidr_el2",		CPENC (3,4,13,0,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tpidr_el3",		CPENC (3,6,13,0,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("tpidrro_el0",	CPENC (3,3,13,0,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trbbaser_el1",	CPENC (3,0,9,11,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trbidr_el1",		CPENC (3,0,9,11,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trblimitr_el1",	CPENC (3,0,9,11,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trbmar_el1",		CPENC (3,0,9,11,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trbptr_el1",		CPENC (3,0,9,11,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trbsr_el1",		CPENC (3,0,9,11,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trbtrg_el1",		CPENC (3,0,9,11,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr0",		CPENC (2,1,2,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr1",		CPENC (2,1,2,2,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr10",		CPENC (2,1,2,4,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr11",		CPENC (2,1,2,6,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr12",		CPENC (2,1,2,8,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr13",		CPENC (2,1,2,10,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr14",		CPENC (2,1,2,12,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr15",		CPENC (2,1,2,14,3),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr2",		CPENC (2,1,2,4,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr3",		CPENC (2,1,2,6,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr4",		CPENC (2,1,2,8,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr5",		CPENC (2,1,2,10,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr6",		CPENC (2,1,2,12,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr7",		CPENC (2,1,2,14,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr8",		CPENC (2,1,2,0,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacatr9",		CPENC (2,1,2,2,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr0",		CPENC (2,1,2,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr1",		CPENC (2,1,2,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr10",		CPENC (2,1,2,4,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr11",		CPENC (2,1,2,6,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr12",		CPENC (2,1,2,8,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr13",		CPENC (2,1,2,10,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr14",		CPENC (2,1,2,12,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr15",		CPENC (2,1,2,14,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr2",		CPENC (2,1,2,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr3",		CPENC (2,1,2,6,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr4",		CPENC (2,1,2,8,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr5",		CPENC (2,1,2,10,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr6",		CPENC (2,1,2,12,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr7",		CPENC (2,1,2,14,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr8",		CPENC (2,1,2,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcacvr9",		CPENC (2,1,2,2,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcauthstatus",	CPENC (2,1,7,14,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcauxctlr",		CPENC (2,1,0,6,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcbbctlr",		CPENC (2,1,0,15,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcccctlr",		CPENC (2,1,0,14,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcctlr0",	CPENC (2,1,3,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcctlr1",	CPENC (2,1,3,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr0",		CPENC (2,1,3,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr1",		CPENC (2,1,3,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr2",		CPENC (2,1,3,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr3",		CPENC (2,1,3,6,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr4",		CPENC (2,1,3,8,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr5",		CPENC (2,1,3,10,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr6",		CPENC (2,1,3,12,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidcvr7",		CPENC (2,1,3,14,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidr0",		CPENC (2,1,7,12,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidr1",		CPENC (2,1,7,13,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidr2",		CPENC (2,1,7,14,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trccidr3",		CPENC (2,1,7,15,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcclaimclr",	CPENC (2,1,7,9,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcclaimset",	CPENC (2,1,7,8,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntctlr0",	CPENC (2,1,0,4,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntctlr1",	CPENC (2,1,0,5,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntctlr2",	CPENC (2,1,0,6,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntctlr3",	CPENC (2,1,0,7,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntrldvr0",	CPENC (2,1,0,0,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntrldvr1",	CPENC (2,1,0,1,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntrldvr2",	CPENC (2,1,0,2,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntrldvr3",	CPENC (2,1,0,3,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntvr0",		CPENC (2,1,0,8,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntvr1",		CPENC (2,1,0,9,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntvr2",		CPENC (2,1,0,10,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trccntvr3",		CPENC (2,1,0,11,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcconfigr",		CPENC (2,1,0,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdevaff0",		CPENC (2,1,7,10,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdevaff1",		CPENC (2,1,7,11,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdevarch",		CPENC (2,1,7,15,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdevid",		CPENC (2,1,7,2,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdevtype",		CPENC (2,1,7,3,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr0",		CPENC (2,1,2,0,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr1",		CPENC (2,1,2,4,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr2",		CPENC (2,1,2,8,6),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr3",		CPENC (2,1,2,12,6),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr4",		CPENC (2,1,2,0,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr5",		CPENC (2,1,2,4,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr6",		CPENC (2,1,2,8,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcmr7",		CPENC (2,1,2,12,7),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr0",		CPENC (2,1,2,0,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr1",		CPENC (2,1,2,4,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr2",		CPENC (2,1,2,8,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr3",		CPENC (2,1,2,12,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr4",		CPENC (2,1,2,0,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr5",		CPENC (2,1,2,4,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr6",		CPENC (2,1,2,8,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcdvcvr7",		CPENC (2,1,2,12,5),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trceventctl0r",	CPENC (2,1,0,8,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trceventctl1r",	CPENC (2,1,0,9,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcextinselr",	CPENC (2,1,0,8,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcextinselr0",	CPENC (2,1,0,8,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcextinselr1",	CPENC (2,1,0,9,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcextinselr2",	CPENC (2,1,0,10,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcextinselr3",	CPENC (2,1,0,11,4),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr0",		CPENC (2,1,0,8,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr1",		CPENC (2,1,0,9,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr10",		CPENC (2,1,0,2,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr11",		CPENC (2,1,0,3,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr12",		CPENC (2,1,0,4,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr13",		CPENC (2,1,0,5,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr2",		CPENC (2,1,0,10,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr3",		CPENC (2,1,0,11,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr4",		CPENC (2,1,0,12,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr5",		CPENC (2,1,0,13,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr6",		CPENC (2,1,0,14,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr7",		CPENC (2,1,0,15,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr8",		CPENC (2,1,0,0,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcidr9",		CPENC (2,1,0,1,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec0",		CPENC (2,1,0,0,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec1",		CPENC (2,1,0,1,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec2",		CPENC (2,1,0,2,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec3",		CPENC (2,1,0,3,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec4",		CPENC (2,1,0,4,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec5",		CPENC (2,1,0,5,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec6",		CPENC (2,1,0,6,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcimspec7",		CPENC (2,1,0,7,7),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcitctrl",		CPENC (2,1,7,0,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trclar",		CPENC (2,1,7,12,6),      F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trclsr",		CPENC (2,1,7,13,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcoslar",		CPENC (2,1,1,0,4),       F_REG_WRITE,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcoslsr",		CPENC (2,1,1,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpdcr",		CPENC (2,1,1,4,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpdsr",		CPENC (2,1,1,5,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr0",		CPENC (2,1,7,8,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr1",		CPENC (2,1,7,9,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr2",		CPENC (2,1,7,10,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr3",		CPENC (2,1,7,11,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr4",		CPENC (2,1,7,4,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr5",		CPENC (2,1,7,5,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr6",		CPENC (2,1,7,6,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcpidr7",		CPENC (2,1,7,7,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcprgctlr",		CPENC (2,1,0,1,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcprocselr",	CPENC (2,1,0,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcqctlr",		CPENC (2,1,0,1,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr10",	CPENC (2,1,1,10,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr11",	CPENC (2,1,1,11,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr12",	CPENC (2,1,1,12,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr13",	CPENC (2,1,1,13,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr14",	CPENC (2,1,1,14,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr15",	CPENC (2,1,1,15,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr16",	CPENC (2,1,1,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr17",	CPENC (2,1,1,1,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr18",	CPENC (2,1,1,2,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr19",	CPENC (2,1,1,3,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr2",		CPENC (2,1,1,2,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr20",	CPENC (2,1,1,4,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr21",	CPENC (2,1,1,5,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr22",	CPENC (2,1,1,6,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr23",	CPENC (2,1,1,7,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr24",	CPENC (2,1,1,8,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr25",	CPENC (2,1,1,9,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr26",	CPENC (2,1,1,10,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr27",	CPENC (2,1,1,11,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr28",	CPENC (2,1,1,12,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr29",	CPENC (2,1,1,13,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr3",		CPENC (2,1,1,3,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr30",	CPENC (2,1,1,14,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr31",	CPENC (2,1,1,15,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr4",		CPENC (2,1,1,4,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr5",		CPENC (2,1,1,5,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr6",		CPENC (2,1,1,6,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr7",		CPENC (2,1,1,7,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr8",		CPENC (2,1,1,8,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsctlr9",		CPENC (2,1,1,9,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcrsr",		CPENC (2,1,0,10,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcseqevr0",		CPENC (2,1,0,0,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcseqevr1",		CPENC (2,1,0,1,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcseqevr2",		CPENC (2,1,0,2,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcseqrstevr",	CPENC (2,1,0,6,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcseqstr",		CPENC (2,1,0,7,4),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr0",		CPENC (2,1,1,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr1",		CPENC (2,1,1,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr2",		CPENC (2,1,1,2,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr3",		CPENC (2,1,1,3,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr4",		CPENC (2,1,1,4,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr5",		CPENC (2,1,1,5,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr6",		CPENC (2,1,1,6,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcssccr7",		CPENC (2,1,1,7,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr0",		CPENC (2,1,1,8,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr1",		CPENC (2,1,1,9,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr2",		CPENC (2,1,1,10,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr3",		CPENC (2,1,1,11,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr4",		CPENC (2,1,1,12,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr5",		CPENC (2,1,1,13,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr6",		CPENC (2,1,1,14,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsscsr7",		CPENC (2,1,1,15,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr0",	CPENC (2,1,1,0,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr1",	CPENC (2,1,1,1,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr2",	CPENC (2,1,1,2,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr3",	CPENC (2,1,1,3,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr4",	CPENC (2,1,1,4,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr5",	CPENC (2,1,1,5,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr6",	CPENC (2,1,1,6,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsspcicr7",	CPENC (2,1,1,7,3),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcstallctlr",	CPENC (2,1,0,11,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcstatr",		CPENC (2,1,0,3,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
> +  SYSREG ("trcsyncpr",		CPENC (2,1,0,13,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trctraceidr",	CPENC (2,1,0,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trctsctlr",		CPENC (2,1,0,12,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvdarcctlr",	CPENC (2,1,0,10,2),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvdctlr",		CPENC (2,1,0,8,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvdsacctlr",	CPENC (2,1,0,9,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvictlr",		CPENC (2,1,0,0,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcviiectlr",	CPENC (2,1,0,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvipcssctlr",	CPENC (2,1,0,3,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvissctlr",	CPENC (2,1,0,2,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcctlr0",	CPENC (2,1,3,2,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcctlr1",	CPENC (2,1,3,3,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr0",	CPENC (2,1,3,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr1",	CPENC (2,1,3,2,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr2",	CPENC (2,1,3,4,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr3",	CPENC (2,1,3,6,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr4",	CPENC (2,1,3,8,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr5",	CPENC (2,1,3,10,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr6",	CPENC (2,1,3,12,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trcvmidcvr7",	CPENC (2,1,3,14,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("trfcr_el1",		CPENC (3,0,1,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("trfcr_el12",		CPENC (3,5,1,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("trfcr_el2",		CPENC (3,4,1,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("ttbr0_el1",		CPENC (3,0,2,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ttbr0_el12",		CPENC (3,5,2,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("ttbr0_el2",		CPENC (3,4,2,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8A)
> +  SYSREG ("ttbr0_el3",		CPENC (3,6,2,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ttbr1_el1",		CPENC (3,0,2,0,1),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("ttbr1_el12",		CPENC (3,5,2,0,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("ttbr1_el2",		CPENC (3,4,2,0,1),       F_ARCHEXT,		AARCH64_FEATURE_V8A|AARCH64_FEATURE_V8_1A)
> +  SYSREG ("uao",		CPENC (3,0,4,2,4),       F_ARCHEXT,		AARCH64_FEATURE_V8_2A)
> +  SYSREG ("vbar_el1",		CPENC (3,0,12,0,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vbar_el12",		CPENC (3,5,12,0,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
> +  SYSREG ("vbar_el2",		CPENC (3,4,12,0,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vbar_el3",		CPENC (3,6,12,0,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vdisr_el2",		CPENC (3,4,12,1,1),      F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("vmecid_a_el2",	CPENC (3,4,10,9,1),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vmecid_p_el2",	CPENC (3,4,10,9,0),      0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vmpidr_el2",		CPENC (3,4,0,0,5),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vncr_el2",		CPENC (3,4,2,2,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("vpidr_el2",		CPENC (3,4,0,0,0),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vsctlr_el2",		CPENC (3,4,2,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
> +  SYSREG ("vsesr_el2",		CPENC (3,4,5,2,3),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
> +  SYSREG ("vstcr_el2",		CPENC (3,4,2,6,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
> +  SYSREG ("vsttbr_el2",		CPENC (3,4,2,6,0),       F_ARCHEXT,		AARCH64_FEATURE_V8A|AARCH64_FEATURE_V8_4A)
> +  SYSREG ("vtcr_el2",		CPENC (3,4,2,1,2),       0,			AARCH64_FEATURE_CORE)
> +  SYSREG ("vttbr_el2",		CPENC (3,4,2,1,0),       F_ARCHEXT,		AARCH64_FEATURE_V8A)
> +  SYSREG ("zcr_el1",		CPENC (3,0,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
> +  SYSREG ("zcr_el12",		CPENC (3,5,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
> +  SYSREG ("zcr_el2",		CPENC (3,4,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
> +  SYSREG ("zcr_el3",		CPENC (3,6,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
> 
> 2.41.0
>
  
Nick Clifton Sept. 27, 2023, 3:26 p.m. UTC | #2
Hi Victor,

> Gentle reminder of review request for this patch, together with parts 2 & 3.

Oops - sorry about that.

> https://sourceware.org/pipermail/binutils/2023-September/129426.html
> https://sourceware.org/pipermail/binutils/2023-September/129427.html
> https://sourceware.org/pipermail/binutils/2023-September/129428.html
> 
> Patch series tested and regression-free.

Patch series approved - please apply.

Cheers
   Nick
  

Patch

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 381934ab39b..4cd0ac70a13 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -39,6 +39,7 @@  extern "C" {
 typedef uint32_t aarch64_insn;
 
 /* The following bitmasks control CPU features.  */
+#define AARCH64_FEATURE_CORE	     (0ULL << 0) /*All processors.  */
 #define AARCH64_FEATURE_V8	     (1ULL << 0) /* All processors.  */
 #define AARCH64_FEATURE_V8_6A	     (1ULL << 1) /* ARMv8.6 processors.  */
 #define AARCH64_FEATURE_BFLOAT16     (1ULL << 2) /* Bfloat16 insns.  */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 41dec5cdc04..e3f0ed13de0 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4674,67 +4674,6 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 #define C14 14
 #define C15 15
 
-#define SYSREG(name, encoding, flags, features) \
-  { name, encoding, flags, features }
-
-#define SR_CORE(n,e,f) SYSREG (n,e,f,0)
-
-#define SR_FEAT(n,e,f,feat) \
-  SYSREG ((n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE_##feat)
-
-#define SR_FEAT2(n,e,f,fe1,fe2) \
-  SYSREG ((n), (e), (f) | F_ARCHEXT, \
-	  AARCH64_FEATURE_##fe1 | AARCH64_FEATURE_##fe2)
-
-#define SR_V8_1_A(n,e,f) SR_FEAT2(n,e,f,V8A,V8_1A)
-#define SR_V8_4_A(n,e,f) SR_FEAT2(n,e,f,V8A,V8_4A)
-
-#define SR_V8A(n,e,f)	  SR_FEAT (n,e,f,V8A)
-#define SR_V8R(n,e,f)	  SR_FEAT (n,e,f,V8R)
-#define SR_V8_1A(n,e,f)	  SR_FEAT (n,e,f,V8_1A)
-#define SR_V8_2A(n,e,f)	  SR_FEAT (n,e,f,V8_2A)
-#define SR_V8_3A(n,e,f)	  SR_FEAT (n,e,f,V8_3A)
-#define SR_V8_4A(n,e,f)	  SR_FEAT (n,e,f,V8_4A)
-#define SR_V8_6A(n,e,f)	  SR_FEAT (n,e,f,V8_6A)
-#define SR_V8_7A(n,e,f)	  SR_FEAT (n,e,f,V8_7A)
-#define SR_V8_8A(n,e,f)	  SR_FEAT (n,e,f,V8_8A)
-/* Has no separate libopcodes feature flag, but separated out for clarity.  */
-#define SR_GIC(n,e,f)	  SR_CORE (n,e,f)
-/* Has no separate libopcodes feature flag, but separated out for clarity.  */
-#define SR_AMU(n,e,f)	  SR_FEAT (n,e,f,V8_4A)
-#define SR_LOR(n,e,f)	  SR_FEAT (n,e,f,LOR)
-#define SR_PAN(n,e,f)	  SR_FEAT (n,e,f,PAN)
-#define SR_RAS(n,e,f)	  SR_FEAT (n,e,f,RAS)
-#define SR_RNG(n,e,f)	  SR_FEAT (n,e,f,RNG)
-#define SR_SME(n,e,f)	  SR_FEAT (n,e,f,SME)
-#define SR_SSBS(n,e,f)	  SR_FEAT (n,e,f,SSBS)
-#define SR_SVE(n,e,f)	  SR_FEAT (n,e,f,SVE)
-#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2)
-#define SR_PROFILE(n,e,f) SR_FEAT (n,e,f,PROFILE)
-#define SR_MEMTAG(n,e,f)  SR_FEAT (n,e,f,MEMTAG)
-#define SR_SCXTNUM(n,e,f) SR_FEAT (n,e,f,SCXTNUM)
-
-#define SR_EXPAND_ELx(f,x) \
-  f (x, 1),  \
-  f (x, 2),  \
-  f (x, 3),  \
-  f (x, 4),  \
-  f (x, 5),  \
-  f (x, 6),  \
-  f (x, 7),  \
-  f (x, 8),  \
-  f (x, 9),  \
-  f (x, 10), \
-  f (x, 11), \
-  f (x, 12), \
-  f (x, 13), \
-  f (x, 14), \
-  f (x, 15),
-
-#define SR_EXPAND_EL12(f) \
-  SR_EXPAND_ELx (f,1) \
-  SR_EXPAND_ELx (f,2)
-
 /* TODO there is one more issues need to be resolved
    1. handle cpu-implementation-defined system registers.
 
@@ -4742,1001 +4681,11 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
    respectively.  If neither of these are set then the register is read-write.  */
 const aarch64_sys_reg aarch64_sys_regs [] =
 {
-  SR_CORE ("spsr_el1",		CPEN_ (0,C0,0),		0), /* = spsr_svc.  */
-  SR_V8_1A ("spsr_el12",		CPEN_ (5,C0,0),		0),
-  SR_CORE ("elr_el1",		CPEN_ (0,C0,1),		0),
-  SR_V8_1A ("elr_el12",		CPEN_ (5,C0,1),		0),
-  SR_CORE ("sp_el0",		CPEN_ (0,C1,0),		0),
-  SR_CORE ("spsel",		CPEN_ (0,C2,0),		0),
-  SR_CORE ("daif",		CPEN_ (3,C2,1),		0),
-  SR_CORE ("currentel",		CPEN_ (0,C2,2),		F_REG_READ),
-  SR_PAN  ("pan",		CPEN_ (0,C2,3),		0),
-  SR_V8_2A ("uao",		CPEN_ (0,C2,4),		0),
-  SR_CORE ("nzcv",		CPEN_ (3,C2,0),		0),
-  SR_SSBS ("ssbs",		CPEN_ (3,C2,6),		0),
-  SR_CORE ("fpcr",		CPEN_ (3,C4,0),		0),
-  SR_CORE ("fpsr",		CPEN_ (3,C4,1),		0),
-  SR_CORE ("dspsr_el0",		CPEN_ (3,C5,0),		0),
-  SR_CORE ("dlr_el0",		CPEN_ (3,C5,1),		0),
-  SR_CORE ("spsr_el2",		CPEN_ (4,C0,0),		0), /* = spsr_hyp.  */
-  SR_CORE ("elr_el2",		CPEN_ (4,C0,1),		0),
-  SR_CORE ("sp_el1",		CPEN_ (4,C1,0),		0),
-  SR_CORE ("spsr_irq",		CPEN_ (4,C3,0),		0),
-  SR_CORE ("spsr_abt",		CPEN_ (4,C3,1),		0),
-  SR_CORE ("spsr_und",		CPEN_ (4,C3,2),		0),
-  SR_CORE ("spsr_fiq",		CPEN_ (4,C3,3),		0),
-  SR_CORE ("spsr_el3",		CPEN_ (6,C0,0),		0),
-  SR_CORE ("elr_el3",		CPEN_ (6,C0,1),		0),
-  SR_CORE ("sp_el2",		CPEN_ (6,C1,0),		0),
-  SR_CORE ("spsr_svc",		CPEN_ (0,C0,0),		F_DEPRECATED), /* = spsr_el1.  */
-  SR_CORE ("spsr_hyp",		CPEN_ (4,C0,0),		F_DEPRECATED), /* = spsr_el2.  */
-  SR_CORE ("midr_el1",		CPENC (3,0,C0,C0,0),	F_REG_READ),
-  SR_CORE ("ctr_el0",		CPENC (3,3,C0,C0,1),	F_REG_READ),
-  SR_CORE ("mpidr_el1",		CPENC (3,0,C0,C0,5),	F_REG_READ),
-  SR_CORE ("revidr_el1",	CPENC (3,0,C0,C0,6),	F_REG_READ),
-  SR_CORE ("aidr_el1",		CPENC (3,1,C0,C0,7),	F_REG_READ),
-  SR_CORE ("dczid_el0",		CPENC (3,3,C0,C0,7),	F_REG_READ),
-  SR_CORE ("id_dfr0_el1",	CPENC (3,0,C0,C1,2),	F_REG_READ),
-  SR_CORE ("id_dfr1_el1",	CPENC (3,0,C0,C3,5),	F_REG_READ),
-  SR_CORE ("id_pfr0_el1",	CPENC (3,0,C0,C1,0),	F_REG_READ),
-  SR_CORE ("id_pfr1_el1",	CPENC (3,0,C0,C1,1),	F_REG_READ),
-  SR_ID_PFR2 ("id_pfr2_el1",	CPENC (3,0,C0,C3,4),	F_REG_READ),
-  SR_CORE ("id_afr0_el1",	CPENC (3,0,C0,C1,3),	F_REG_READ),
-  SR_CORE ("id_mmfr0_el1",	CPENC (3,0,C0,C1,4),	F_REG_READ),
-  SR_CORE ("id_mmfr1_el1",	CPENC (3,0,C0,C1,5),	F_REG_READ),
-  SR_CORE ("id_mmfr2_el1",	CPENC (3,0,C0,C1,6),	F_REG_READ),
-  SR_CORE ("id_mmfr3_el1",	CPENC (3,0,C0,C1,7),	F_REG_READ),
-  SR_CORE ("id_mmfr4_el1",	CPENC (3,0,C0,C2,6),	F_REG_READ),
-  SR_CORE ("id_mmfr5_el1",	CPENC (3,0,C0,C3,6),	F_REG_READ),
-  SR_CORE ("id_isar0_el1",	CPENC (3,0,C0,C2,0),	F_REG_READ),
-  SR_CORE ("id_isar1_el1",	CPENC (3,0,C0,C2,1),	F_REG_READ),
-  SR_CORE ("id_isar2_el1",	CPENC (3,0,C0,C2,2),	F_REG_READ),
-  SR_CORE ("id_isar3_el1",	CPENC (3,0,C0,C2,3),	F_REG_READ),
-  SR_CORE ("id_isar4_el1",	CPENC (3,0,C0,C2,4),	F_REG_READ),
-  SR_CORE ("id_isar5_el1",	CPENC (3,0,C0,C2,5),	F_REG_READ),
-  SR_CORE ("id_isar6_el1",	CPENC (3,0,C0,C2,7),	F_REG_READ),
-  SR_CORE ("mvfr0_el1",		CPENC (3,0,C0,C3,0),	F_REG_READ),
-  SR_CORE ("mvfr1_el1",		CPENC (3,0,C0,C3,1),	F_REG_READ),
-  SR_CORE ("mvfr2_el1",		CPENC (3,0,C0,C3,2),	F_REG_READ),
-  SR_CORE ("ccsidr_el1",	CPENC (3,1,C0,C0,0),	F_REG_READ),
-  SR_V8_3A ("ccsidr2_el1",       CPENC (3,1,C0,C0,2),    F_REG_READ),
-  SR_CORE ("id_aa64pfr0_el1",	CPENC (3,0,C0,C4,0),	F_REG_READ),
-  SR_CORE ("id_aa64pfr1_el1",	CPENC (3,0,C0,C4,1),	F_REG_READ),
-  SR_CORE ("id_aa64dfr0_el1",	CPENC (3,0,C0,C5,0),	F_REG_READ),
-  SR_CORE ("id_aa64dfr1_el1",	CPENC (3,0,C0,C5,1),	F_REG_READ),
-  SR_CORE ("id_aa64isar0_el1",	CPENC (3,0,C0,C6,0),	F_REG_READ),
-  SR_CORE ("id_aa64isar1_el1",	CPENC (3,0,C0,C6,1),	F_REG_READ),
-  SR_CORE ("id_aa64isar2_el1",	CPENC (3,0,C0,C6,2),	F_REG_READ),
-  SR_CORE ("id_aa64mmfr0_el1",	CPENC (3,0,C0,C7,0),	F_REG_READ),
-  SR_CORE ("id_aa64mmfr1_el1",	CPENC (3,0,C0,C7,1),	F_REG_READ),
-  SR_CORE ("id_aa64mmfr2_el1",	CPENC (3,0,C0,C7,2),	F_REG_READ),
-  SR_CORE ("id_aa64afr0_el1",	CPENC (3,0,C0,C5,4),	F_REG_READ),
-  SR_CORE ("id_aa64afr1_el1",	CPENC (3,0,C0,C5,5),	F_REG_READ),
-  SR_SVE  ("id_aa64zfr0_el1",	CPENC (3,0,C0,C4,4),	F_REG_READ),
-  SR_CORE ("clidr_el1",		CPENC (3,1,C0,C0,1),	F_REG_READ),
-  SR_CORE ("csselr_el1",	CPENC (3,2,C0,C0,0),	0),
-  SR_CORE ("vpidr_el2",		CPENC (3,4,C0,C0,0),	0),
-  SR_CORE ("vmpidr_el2",	CPENC (3,4,C0,C0,5),	0),
-  SR_CORE ("sctlr_el1",		CPENC (3,0,C1,C0,0),	0),
-  SR_CORE ("sctlr_el2",		CPENC (3,4,C1,C0,0),	0),
-  SR_CORE ("sctlr_el3",		CPENC (3,6,C1,C0,0),	0),
-  SR_V8_1A ("sctlr_el12",	CPENC (3,5,C1,C0,0),	0),
-  SR_CORE ("actlr_el1",		CPENC (3,0,C1,C0,1),	0),
-  SR_CORE ("actlr_el2",		CPENC (3,4,C1,C0,1),	0),
-  SR_CORE ("actlr_el3",		CPENC (3,6,C1,C0,1),	0),
-  SR_CORE ("cpacr_el1",		CPENC (3,0,C1,C0,2),	0),
-  SR_V8_1A ("cpacr_el12",	CPENC (3,5,C1,C0,2),	0),
-  SR_CORE ("cptr_el2",		CPENC (3,4,C1,C1,2),	0),
-  SR_CORE ("cptr_el3",		CPENC (3,6,C1,C1,2),	0),
-  SR_CORE ("scr_el3",		CPENC (3,6,C1,C1,0),	0),
-  SR_CORE ("hcr_el2",		CPENC (3,4,C1,C1,0),	0),
-  SR_CORE ("mdcr_el2",		CPENC (3,4,C1,C1,1),	0),
-  SR_CORE ("mdcr_el3",		CPENC (3,6,C1,C3,1),	0),
-  SR_CORE ("hstr_el2",		CPENC (3,4,C1,C1,3),	0),
-  SR_CORE ("hacr_el2",		CPENC (3,4,C1,C1,7),	0),
-  SR_SVE  ("zcr_el1",		CPENC (3,0,C1,C2,0),	0),
-  SR_SVE  ("zcr_el12",		CPENC (3,5,C1,C2,0),	0),
-  SR_SVE  ("zcr_el2",		CPENC (3,4,C1,C2,0),	0),
-  SR_SVE  ("zcr_el3",		CPENC (3,6,C1,C2,0),	0),
-  SR_CORE ("ttbr0_el1",		CPENC (3,0,C2,C0,0),	0),
-  SR_CORE ("ttbr1_el1",		CPENC (3,0,C2,C0,1),	0),
-  SR_V8A ("ttbr0_el2",		CPENC (3,4,C2,C0,0),	0),
-  SR_V8_1_A ("ttbr1_el2",	CPENC (3,4,C2,C0,1),	0),
-  SR_CORE ("ttbr0_el3",		CPENC (3,6,C2,C0,0),	0),
-  SR_V8_1A ("ttbr0_el12",	CPENC (3,5,C2,C0,0),	0),
-  SR_V8_1A ("ttbr1_el12",	CPENC (3,5,C2,C0,1),	0),
-  SR_V8A ("vttbr_el2",		CPENC (3,4,C2,C1,0),	0),
-  SR_CORE ("tcr_el1",		CPENC (3,0,C2,C0,2),	0),
-  SR_CORE ("tcr_el2",		CPENC (3,4,C2,C0,2),	0),
-  SR_CORE ("tcr_el3",		CPENC (3,6,C2,C0,2),	0),
-  SR_V8_1A ("tcr_el12",		CPENC (3,5,C2,C0,2),	0),
-  SR_CORE ("vtcr_el2",		CPENC (3,4,C2,C1,2),	0),
-  SR_V8_3A ("apiakeylo_el1",	CPENC (3,0,C2,C1,0),	0),
-  SR_V8_3A ("apiakeyhi_el1",	CPENC (3,0,C2,C1,1),	0),
-  SR_V8_3A ("apibkeylo_el1",	CPENC (3,0,C2,C1,2),	0),
-  SR_V8_3A ("apibkeyhi_el1",	CPENC (3,0,C2,C1,3),	0),
-  SR_V8_3A ("apdakeylo_el1",	CPENC (3,0,C2,C2,0),	0),
-  SR_V8_3A ("apdakeyhi_el1",	CPENC (3,0,C2,C2,1),	0),
-  SR_V8_3A ("apdbkeylo_el1",	CPENC (3,0,C2,C2,2),	0),
-  SR_V8_3A ("apdbkeyhi_el1",	CPENC (3,0,C2,C2,3),	0),
-  SR_V8_3A ("apgakeylo_el1",	CPENC (3,0,C2,C3,0),	0),
-  SR_V8_3A ("apgakeyhi_el1",	CPENC (3,0,C2,C3,1),	0),
-  SR_CORE ("afsr0_el1",		CPENC (3,0,C5,C1,0),	0),
-  SR_CORE ("afsr1_el1",		CPENC (3,0,C5,C1,1),	0),
-  SR_CORE ("afsr0_el2",		CPENC (3,4,C5,C1,0),	0),
-  SR_CORE ("afsr1_el2",		CPENC (3,4,C5,C1,1),	0),
-  SR_CORE ("afsr0_el3",		CPENC (3,6,C5,C1,0),	0),
-  SR_V8_1A ("afsr0_el12",	CPENC (3,5,C5,C1,0),	0),
-  SR_CORE ("afsr1_el3",		CPENC (3,6,C5,C1,1),	0),
-  SR_V8_1A ("afsr1_el12",	CPENC (3,5,C5,C1,1),	0),
-  SR_CORE ("esr_el1",		CPENC (3,0,C5,C2,0),	0),
-  SR_CORE ("esr_el2",		CPENC (3,4,C5,C2,0),	0),
-  SR_CORE ("esr_el3",		CPENC (3,6,C5,C2,0),	0),
-  SR_V8_1A ("esr_el12",		CPENC (3,5,C5,C2,0),	0),
-  SR_RAS  ("vsesr_el2",		CPENC (3,4,C5,C2,3),	0),
-  SR_CORE ("fpexc32_el2",	CPENC (3,4,C5,C3,0),	0),
-  SR_RAS  ("erridr_el1",	CPENC (3,0,C5,C3,0),	F_REG_READ),
-  SR_RAS  ("errselr_el1",	CPENC (3,0,C5,C3,1),	0),
-  SR_RAS  ("erxfr_el1",		CPENC (3,0,C5,C4,0),	F_REG_READ),
-  SR_RAS  ("erxctlr_el1",	CPENC (3,0,C5,C4,1),	0),
-  SR_RAS  ("erxstatus_el1",	CPENC (3,0,C5,C4,2),	0),
-  SR_RAS  ("erxaddr_el1",	CPENC (3,0,C5,C4,3),	0),
-  SR_RAS  ("erxmisc0_el1",	CPENC (3,0,C5,C5,0),	0),
-  SR_RAS  ("erxmisc1_el1",	CPENC (3,0,C5,C5,1),	0),
-  SR_RAS  ("erxmisc2_el1",	CPENC (3,0,C5,C5,2),	0),
-  SR_RAS  ("erxmisc3_el1",	CPENC (3,0,C5,C5,3),	0),
-  SR_RAS  ("erxpfgcdn_el1",	CPENC (3,0,C5,C4,6),	0),
-  SR_RAS  ("erxpfgctl_el1",	CPENC (3,0,C5,C4,5),	0),
-  SR_RAS  ("erxpfgf_el1",	CPENC (3,0,C5,C4,4),	F_REG_READ),
-  SR_CORE ("far_el1",		CPENC (3,0,C6,C0,0),	0),
-  SR_CORE ("far_el2",		CPENC (3,4,C6,C0,0),	0),
-  SR_CORE ("far_el3",		CPENC (3,6,C6,C0,0),	0),
-  SR_V8_1A ("far_el12",		CPENC (3,5,C6,C0,0),	0),
-  SR_CORE ("hpfar_el2",		CPENC (3,4,C6,C0,4),	0),
-  SR_CORE ("par_el1",		CPENC (3,0,C7,C4,0),	0),
-  SR_CORE ("mair_el1",		CPENC (3,0,C10,C2,0),	0),
-  SR_CORE ("mair_el2",		CPENC (3,4,C10,C2,0),	0),
-  SR_CORE ("mair_el3",		CPENC (3,6,C10,C2,0),	0),
-  SR_V8_1A ("mair_el12",		CPENC (3,5,C10,C2,0),	0),
-  SR_CORE ("amair_el1",		CPENC (3,0,C10,C3,0),	0),
-  SR_CORE ("amair_el2",		CPENC (3,4,C10,C3,0),	0),
-  SR_CORE ("amair_el3",		CPENC (3,6,C10,C3,0),	0),
-  SR_V8_1A ("amair_el12",	CPENC (3,5,C10,C3,0),	0),
-  SR_CORE ("vbar_el1",		CPENC (3,0,C12,C0,0),	0),
-  SR_CORE ("vbar_el2",		CPENC (3,4,C12,C0,0),	0),
-  SR_CORE ("vbar_el3",		CPENC (3,6,C12,C0,0),	0),
-  SR_V8_1A ("vbar_el12",		CPENC (3,5,C12,C0,0),	0),
-  SR_CORE ("rvbar_el1",		CPENC (3,0,C12,C0,1),	F_REG_READ),
-  SR_CORE ("rvbar_el2",		CPENC (3,4,C12,C0,1),	F_REG_READ),
-  SR_CORE ("rvbar_el3",		CPENC (3,6,C12,C0,1),	F_REG_READ),
-  SR_CORE ("rmr_el1",		CPENC (3,0,C12,C0,2),	0),
-  SR_CORE ("rmr_el2",		CPENC (3,4,C12,C0,2),	0),
-  SR_CORE ("rmr_el3",		CPENC (3,6,C12,C0,2),	0),
-  SR_CORE ("isr_el1",		CPENC (3,0,C12,C1,0),	F_REG_READ),
-  SR_RAS  ("disr_el1",		CPENC (3,0,C12,C1,1),	0),
-  SR_RAS  ("vdisr_el2",		CPENC (3,4,C12,C1,1),	0),
-  SR_CORE ("contextidr_el1",	CPENC (3,0,C13,C0,1),	0),
-  SR_V8_1A ("contextidr_el2",	CPENC (3,4,C13,C0,1),	0),
-  SR_V8_1A ("contextidr_el12",	CPENC (3,5,C13,C0,1),	0),
-  SR_RNG  ("rndr",		CPENC (3,3,C2,C4,0),	F_REG_READ),
-  SR_RNG  ("rndrrs",		CPENC (3,3,C2,C4,1),	F_REG_READ),
-  SR_MEMTAG ("tco",		CPENC (3,3,C4,C2,7),	0),
-  SR_MEMTAG ("tfsre0_el1",	CPENC (3,0,C5,C6,1),	0),
-  SR_MEMTAG ("tfsr_el1",	CPENC (3,0,C5,C6,0),	0),
-  SR_MEMTAG ("tfsr_el2",	CPENC (3,4,C5,C6,0),	0),
-  SR_MEMTAG ("tfsr_el3",	CPENC (3,6,C5,C6,0),	0),
-  SR_MEMTAG ("tfsr_el12",	CPENC (3,5,C5,C6,0),	0),
-  SR_MEMTAG ("rgsr_el1",	CPENC (3,0,C1,C0,5),	0),
-  SR_MEMTAG ("gcr_el1",		CPENC (3,0,C1,C0,6),	0),
-  SR_MEMTAG ("gmid_el1",	CPENC (3,1,C0,C0,4),	F_REG_READ),
-  SR_CORE ("tpidr_el0",		CPENC (3,3,C13,C0,2),	0),
-  SR_CORE ("tpidrro_el0",       CPENC (3,3,C13,C0,3),	0),
-  SR_CORE ("tpidr_el1",		CPENC (3,0,C13,C0,4),	0),
-  SR_CORE ("tpidr_el2",		CPENC (3,4,C13,C0,2),	0),
-  SR_CORE ("tpidr_el3",		CPENC (3,6,C13,C0,2),	0),
-  SR_SCXTNUM ("scxtnum_el0",	CPENC (3,3,C13,C0,7),	0),
-  SR_SCXTNUM ("scxtnum_el1",	CPENC (3,0,C13,C0,7),	0),
-  SR_SCXTNUM ("scxtnum_el2",	CPENC (3,4,C13,C0,7),	0),
-  SR_SCXTNUM ("scxtnum_el12",   CPENC (3,5,C13,C0,7),	0),
-  SR_SCXTNUM ("scxtnum_el3",    CPENC (3,6,C13,C0,7),	0),
-  SR_CORE ("teecr32_el1",       CPENC (2,2,C0, C0,0),	0), /* See section 3.9.7.1.  */
-  SR_CORE ("cntfrq_el0",	CPENC (3,3,C14,C0,0),	0),
-  SR_CORE ("cntpct_el0",	CPENC (3,3,C14,C0,1),	F_REG_READ),
-  SR_CORE ("cntvct_el0",	CPENC (3,3,C14,C0,2),	F_REG_READ),
-  SR_CORE ("cntvoff_el2",       CPENC (3,4,C14,C0,3),	0),
-  SR_CORE ("cntkctl_el1",       CPENC (3,0,C14,C1,0),	0),
-  SR_V8_1A ("cntkctl_el12",	CPENC (3,5,C14,C1,0),	0),
-  SR_CORE ("cnthctl_el2",	CPENC (3,4,C14,C1,0),	0),
-  SR_CORE ("cntp_tval_el0",	CPENC (3,3,C14,C2,0),	0),
-  SR_V8_1A ("cntp_tval_el02",	CPENC (3,5,C14,C2,0),	0),
-  SR_CORE ("cntp_ctl_el0",      CPENC (3,3,C14,C2,1),	0),
-  SR_V8_1A ("cntp_ctl_el02",	CPENC (3,5,C14,C2,1),	0),
-  SR_CORE ("cntp_cval_el0",     CPENC (3,3,C14,C2,2),	0),
-  SR_V8_1A ("cntp_cval_el02",	CPENC (3,5,C14,C2,2),	0),
-  SR_CORE ("cntv_tval_el0",     CPENC (3,3,C14,C3,0),	0),
-  SR_V8_1A ("cntv_tval_el02",	CPENC (3,5,C14,C3,0),	0),
-  SR_CORE ("cntv_ctl_el0",      CPENC (3,3,C14,C3,1),	0),
-  SR_V8_1A ("cntv_ctl_el02",	CPENC (3,5,C14,C3,1),	0),
-  SR_CORE ("cntv_cval_el0",     CPENC (3,3,C14,C3,2),	0),
-  SR_V8_1A ("cntv_cval_el02",	CPENC (3,5,C14,C3,2),	0),
-  SR_CORE ("cnthp_tval_el2",	CPENC (3,4,C14,C2,0),	0),
-  SR_CORE ("cnthp_ctl_el2",	CPENC (3,4,C14,C2,1),	0),
-  SR_CORE ("cnthp_cval_el2",	CPENC (3,4,C14,C2,2),	0),
-  SR_CORE ("cntps_tval_el1",	CPENC (3,7,C14,C2,0),	0),
-  SR_CORE ("cntps_ctl_el1",	CPENC (3,7,C14,C2,1),	0),
-  SR_CORE ("cntps_cval_el1",	CPENC (3,7,C14,C2,2),	0),
-  SR_V8_1A ("cnthv_tval_el2",	CPENC (3,4,C14,C3,0),	0),
-  SR_V8_1A ("cnthv_ctl_el2",	CPENC (3,4,C14,C3,1),	0),
-  SR_V8_1A ("cnthv_cval_el2",	CPENC (3,4,C14,C3,2),	0),
-  SR_CORE ("dacr32_el2",	CPENC (3,4,C3,C0,0),	0),
-  SR_CORE ("ifsr32_el2",	CPENC (3,4,C5,C0,1),	0),
-  SR_CORE ("teehbr32_el1",	CPENC (2,2,C1,C0,0),	0),
-  SR_CORE ("sder32_el3",	CPENC (3,6,C1,C1,1),	0),
-  SR_CORE ("mdscr_el1",		CPENC (2,0,C0,C2,2),	0),
-  SR_CORE ("mdccsr_el0",	CPENC (2,3,C0,C1,0),	F_REG_READ),
-  SR_CORE ("mdccint_el1",       CPENC (2,0,C0,C2,0),	0),
-  SR_CORE ("dbgdtr_el0",	CPENC (2,3,C0,C4,0),	0),
-  SR_CORE ("dbgdtrrx_el0",	CPENC (2,3,C0,C5,0),	F_REG_READ),
-  SR_CORE ("dbgdtrtx_el0",	CPENC (2,3,C0,C5,0),	F_REG_WRITE),
-  SR_CORE ("osdtrrx_el1",	CPENC (2,0,C0,C0,2),	0),
-  SR_CORE ("osdtrtx_el1",	CPENC (2,0,C0,C3,2),	0),
-  SR_CORE ("oseccr_el1",	CPENC (2,0,C0,C6,2),	0),
-  SR_CORE ("dbgvcr32_el2",      CPENC (2,4,C0,C7,0),	0),
-  SR_CORE ("dbgbvr0_el1",       CPENC (2,0,C0,C0,4),	0),
-  SR_CORE ("dbgbvr1_el1",       CPENC (2,0,C0,C1,4),	0),
-  SR_CORE ("dbgbvr2_el1",       CPENC (2,0,C0,C2,4),	0),
-  SR_CORE ("dbgbvr3_el1",       CPENC (2,0,C0,C3,4),	0),
-  SR_CORE ("dbgbvr4_el1",       CPENC (2,0,C0,C4,4),	0),
-  SR_CORE ("dbgbvr5_el1",       CPENC (2,0,C0,C5,4),	0),
-  SR_CORE ("dbgbvr6_el1",       CPENC (2,0,C0,C6,4),	0),
-  SR_CORE ("dbgbvr7_el1",       CPENC (2,0,C0,C7,4),	0),
-  SR_CORE ("dbgbvr8_el1",       CPENC (2,0,C0,C8,4),	0),
-  SR_CORE ("dbgbvr9_el1",       CPENC (2,0,C0,C9,4),	0),
-  SR_CORE ("dbgbvr10_el1",      CPENC (2,0,C0,C10,4),	0),
-  SR_CORE ("dbgbvr11_el1",      CPENC (2,0,C0,C11,4),	0),
-  SR_CORE ("dbgbvr12_el1",      CPENC (2,0,C0,C12,4),	0),
-  SR_CORE ("dbgbvr13_el1",      CPENC (2,0,C0,C13,4),	0),
-  SR_CORE ("dbgbvr14_el1",      CPENC (2,0,C0,C14,4),	0),
-  SR_CORE ("dbgbvr15_el1",      CPENC (2,0,C0,C15,4),	0),
-  SR_CORE ("dbgbcr0_el1",       CPENC (2,0,C0,C0,5),	0),
-  SR_CORE ("dbgbcr1_el1",       CPENC (2,0,C0,C1,5),	0),
-  SR_CORE ("dbgbcr2_el1",       CPENC (2,0,C0,C2,5),	0),
-  SR_CORE ("dbgbcr3_el1",       CPENC (2,0,C0,C3,5),	0),
-  SR_CORE ("dbgbcr4_el1",       CPENC (2,0,C0,C4,5),	0),
-  SR_CORE ("dbgbcr5_el1",       CPENC (2,0,C0,C5,5),	0),
-  SR_CORE ("dbgbcr6_el1",       CPENC (2,0,C0,C6,5),	0),
-  SR_CORE ("dbgbcr7_el1",       CPENC (2,0,C0,C7,5),	0),
-  SR_CORE ("dbgbcr8_el1",       CPENC (2,0,C0,C8,5),	0),
-  SR_CORE ("dbgbcr9_el1",       CPENC (2,0,C0,C9,5),	0),
-  SR_CORE ("dbgbcr10_el1",      CPENC (2,0,C0,C10,5),	0),
-  SR_CORE ("dbgbcr11_el1",      CPENC (2,0,C0,C11,5),	0),
-  SR_CORE ("dbgbcr12_el1",      CPENC (2,0,C0,C12,5),	0),
-  SR_CORE ("dbgbcr13_el1",      CPENC (2,0,C0,C13,5),	0),
-  SR_CORE ("dbgbcr14_el1",      CPENC (2,0,C0,C14,5),	0),
-  SR_CORE ("dbgbcr15_el1",      CPENC (2,0,C0,C15,5),	0),
-  SR_CORE ("dbgwvr0_el1",       CPENC (2,0,C0,C0,6),	0),
-  SR_CORE ("dbgwvr1_el1",       CPENC (2,0,C0,C1,6),	0),
-  SR_CORE ("dbgwvr2_el1",       CPENC (2,0,C0,C2,6),	0),
-  SR_CORE ("dbgwvr3_el1",       CPENC (2,0,C0,C3,6),	0),
-  SR_CORE ("dbgwvr4_el1",       CPENC (2,0,C0,C4,6),	0),
-  SR_CORE ("dbgwvr5_el1",       CPENC (2,0,C0,C5,6),	0),
-  SR_CORE ("dbgwvr6_el1",       CPENC (2,0,C0,C6,6),	0),
-  SR_CORE ("dbgwvr7_el1",       CPENC (2,0,C0,C7,6),	0),
-  SR_CORE ("dbgwvr8_el1",       CPENC (2,0,C0,C8,6),	0),
-  SR_CORE ("dbgwvr9_el1",       CPENC (2,0,C0,C9,6),	0),
-  SR_CORE ("dbgwvr10_el1",      CPENC (2,0,C0,C10,6),	0),
-  SR_CORE ("dbgwvr11_el1",      CPENC (2,0,C0,C11,6),	0),
-  SR_CORE ("dbgwvr12_el1",      CPENC (2,0,C0,C12,6),	0),
-  SR_CORE ("dbgwvr13_el1",      CPENC (2,0,C0,C13,6),	0),
-  SR_CORE ("dbgwvr14_el1",      CPENC (2,0,C0,C14,6),	0),
-  SR_CORE ("dbgwvr15_el1",      CPENC (2,0,C0,C15,6),	0),
-  SR_CORE ("dbgwcr0_el1",       CPENC (2,0,C0,C0,7),	0),
-  SR_CORE ("dbgwcr1_el1",       CPENC (2,0,C0,C1,7),	0),
-  SR_CORE ("dbgwcr2_el1",       CPENC (2,0,C0,C2,7),	0),
-  SR_CORE ("dbgwcr3_el1",       CPENC (2,0,C0,C3,7),	0),
-  SR_CORE ("dbgwcr4_el1",       CPENC (2,0,C0,C4,7),	0),
-  SR_CORE ("dbgwcr5_el1",       CPENC (2,0,C0,C5,7),	0),
-  SR_CORE ("dbgwcr6_el1",       CPENC (2,0,C0,C6,7),	0),
-  SR_CORE ("dbgwcr7_el1",       CPENC (2,0,C0,C7,7),	0),
-  SR_CORE ("dbgwcr8_el1",       CPENC (2,0,C0,C8,7),	0),
-  SR_CORE ("dbgwcr9_el1",       CPENC (2,0,C0,C9,7),	0),
-  SR_CORE ("dbgwcr10_el1",      CPENC (2,0,C0,C10,7),	0),
-  SR_CORE ("dbgwcr11_el1",      CPENC (2,0,C0,C11,7),	0),
-  SR_CORE ("dbgwcr12_el1",      CPENC (2,0,C0,C12,7),	0),
-  SR_CORE ("dbgwcr13_el1",      CPENC (2,0,C0,C13,7),	0),
-  SR_CORE ("dbgwcr14_el1",      CPENC (2,0,C0,C14,7),	0),
-  SR_CORE ("dbgwcr15_el1",      CPENC (2,0,C0,C15,7),	0),
-  SR_CORE ("mdrar_el1",		CPENC (2,0,C1,C0,0),	F_REG_READ),
-  SR_CORE ("oslar_el1",		CPENC (2,0,C1,C0,4),	F_REG_WRITE),
-  SR_CORE ("oslsr_el1",		CPENC (2,0,C1,C1,4),	F_REG_READ),
-  SR_CORE ("osdlr_el1",		CPENC (2,0,C1,C3,4),	0),
-  SR_CORE ("dbgprcr_el1",       CPENC (2,0,C1,C4,4),	0),
-  SR_CORE ("dbgclaimset_el1",   CPENC (2,0,C7,C8,6),	0),
-  SR_CORE ("dbgclaimclr_el1",   CPENC (2,0,C7,C9,6),	0),
-  SR_CORE ("dbgauthstatus_el1", CPENC (2,0,C7,C14,6),	F_REG_READ),
-  SR_PROFILE ("pmblimitr_el1",	CPENC (3,0,C9,C10,0),	0),
-  SR_PROFILE ("pmbptr_el1",	CPENC (3,0,C9,C10,1),	0),
-  SR_PROFILE ("pmbsr_el1",	CPENC (3,0,C9,C10,3),	0),
-  SR_PROFILE ("pmbidr_el1",	CPENC (3,0,C9,C10,7),	F_REG_READ),
-  SR_PROFILE ("pmscr_el1",	CPENC (3,0,C9,C9,0),	0),
-  SR_PROFILE ("pmsicr_el1",	CPENC (3,0,C9,C9,2),	0),
-  SR_PROFILE ("pmsirr_el1",	CPENC (3,0,C9,C9,3),	0),
-  SR_PROFILE ("pmsfcr_el1",	CPENC (3,0,C9,C9,4),	0),
-  SR_PROFILE ("pmsevfr_el1",	CPENC (3,0,C9,C9,5),	0),
-  SR_PROFILE ("pmslatfr_el1",	CPENC (3,0,C9,C9,6),	0),
-  SR_PROFILE ("pmsidr_el1",	CPENC (3,0,C9,C9,7),	F_REG_READ),
-  SR_PROFILE ("pmscr_el2",	CPENC (3,4,C9,C9,0),	0),
-  SR_PROFILE ("pmscr_el12",	CPENC (3,5,C9,C9,0),	0),
-  SR_CORE ("pmcr_el0",		CPENC (3,3,C9,C12,0),	0),
-  SR_CORE ("pmcntenset_el0",    CPENC (3,3,C9,C12,1),	0),
-  SR_CORE ("pmcntenclr_el0",    CPENC (3,3,C9,C12,2),	0),
-  SR_CORE ("pmovsclr_el0",      CPENC (3,3,C9,C12,3),	0),
-  SR_CORE ("pmswinc_el0",       CPENC (3,3,C9,C12,4),	F_REG_WRITE),
-  SR_CORE ("pmselr_el0",	CPENC (3,3,C9,C12,5),	0),
-  SR_CORE ("pmceid0_el0",       CPENC (3,3,C9,C12,6),	F_REG_READ),
-  SR_CORE ("pmceid1_el0",       CPENC (3,3,C9,C12,7),	F_REG_READ),
-  SR_CORE ("pmccntr_el0",       CPENC (3,3,C9,C13,0),	0),
-  SR_CORE ("pmxevtyper_el0",    CPENC (3,3,C9,C13,1),	0),
-  SR_CORE ("pmxevcntr_el0",     CPENC (3,3,C9,C13,2),	0),
-  SR_CORE ("pmuserenr_el0",     CPENC (3,3,C9,C14,0),	0),
-  SR_CORE ("pmintenset_el1",    CPENC (3,0,C9,C14,1),	0),
-  SR_CORE ("pmintenclr_el1",    CPENC (3,0,C9,C14,2),	0),
-  SR_CORE ("pmovsset_el0",      CPENC (3,3,C9,C14,3),	0),
-  SR_CORE ("pmevcntr0_el0",     CPENC (3,3,C14,C8,0),	0),
-  SR_CORE ("pmevcntr1_el0",     CPENC (3,3,C14,C8,1),	0),
-  SR_CORE ("pmevcntr2_el0",     CPENC (3,3,C14,C8,2),	0),
-  SR_CORE ("pmevcntr3_el0",     CPENC (3,3,C14,C8,3),	0),
-  SR_CORE ("pmevcntr4_el0",     CPENC (3,3,C14,C8,4),	0),
-  SR_CORE ("pmevcntr5_el0",     CPENC (3,3,C14,C8,5),	0),
-  SR_CORE ("pmevcntr6_el0",     CPENC (3,3,C14,C8,6),	0),
-  SR_CORE ("pmevcntr7_el0",     CPENC (3,3,C14,C8,7),	0),
-  SR_CORE ("pmevcntr8_el0",     CPENC (3,3,C14,C9,0),	0),
-  SR_CORE ("pmevcntr9_el0",     CPENC (3,3,C14,C9,1),	0),
-  SR_CORE ("pmevcntr10_el0",    CPENC (3,3,C14,C9,2),	0),
-  SR_CORE ("pmevcntr11_el0",    CPENC (3,3,C14,C9,3),	0),
-  SR_CORE ("pmevcntr12_el0",    CPENC (3,3,C14,C9,4),	0),
-  SR_CORE ("pmevcntr13_el0",    CPENC (3,3,C14,C9,5),	0),
-  SR_CORE ("pmevcntr14_el0",    CPENC (3,3,C14,C9,6),	0),
-  SR_CORE ("pmevcntr15_el0",    CPENC (3,3,C14,C9,7),	0),
-  SR_CORE ("pmevcntr16_el0",    CPENC (3,3,C14,C10,0),	0),
-  SR_CORE ("pmevcntr17_el0",    CPENC (3,3,C14,C10,1),	0),
-  SR_CORE ("pmevcntr18_el0",    CPENC (3,3,C14,C10,2),	0),
-  SR_CORE ("pmevcntr19_el0",    CPENC (3,3,C14,C10,3),	0),
-  SR_CORE ("pmevcntr20_el0",    CPENC (3,3,C14,C10,4),	0),
-  SR_CORE ("pmevcntr21_el0",    CPENC (3,3,C14,C10,5),	0),
-  SR_CORE ("pmevcntr22_el0",    CPENC (3,3,C14,C10,6),	0),
-  SR_CORE ("pmevcntr23_el0",    CPENC (3,3,C14,C10,7),	0),
-  SR_CORE ("pmevcntr24_el0",    CPENC (3,3,C14,C11,0),	0),
-  SR_CORE ("pmevcntr25_el0",    CPENC (3,3,C14,C11,1),	0),
-  SR_CORE ("pmevcntr26_el0",    CPENC (3,3,C14,C11,2),	0),
-  SR_CORE ("pmevcntr27_el0",    CPENC (3,3,C14,C11,3),	0),
-  SR_CORE ("pmevcntr28_el0",    CPENC (3,3,C14,C11,4),	0),
-  SR_CORE ("pmevcntr29_el0",    CPENC (3,3,C14,C11,5),	0),
-  SR_CORE ("pmevcntr30_el0",    CPENC (3,3,C14,C11,6),	0),
-  SR_CORE ("pmevtyper0_el0",    CPENC (3,3,C14,C12,0),	0),
-  SR_CORE ("pmevtyper1_el0",    CPENC (3,3,C14,C12,1),	0),
-  SR_CORE ("pmevtyper2_el0",    CPENC (3,3,C14,C12,2),	0),
-  SR_CORE ("pmevtyper3_el0",    CPENC (3,3,C14,C12,3),	0),
-  SR_CORE ("pmevtyper4_el0",    CPENC (3,3,C14,C12,4),	0),
-  SR_CORE ("pmevtyper5_el0",    CPENC (3,3,C14,C12,5),	0),
-  SR_CORE ("pmevtyper6_el0",    CPENC (3,3,C14,C12,6),	0),
-  SR_CORE ("pmevtyper7_el0",    CPENC (3,3,C14,C12,7),	0),
-  SR_CORE ("pmevtyper8_el0",    CPENC (3,3,C14,C13,0),	0),
-  SR_CORE ("pmevtyper9_el0",    CPENC (3,3,C14,C13,1),	0),
-  SR_CORE ("pmevtyper10_el0",   CPENC (3,3,C14,C13,2),	0),
-  SR_CORE ("pmevtyper11_el0",   CPENC (3,3,C14,C13,3),	0),
-  SR_CORE ("pmevtyper12_el0",   CPENC (3,3,C14,C13,4),	0),
-  SR_CORE ("pmevtyper13_el0",   CPENC (3,3,C14,C13,5),	0),
-  SR_CORE ("pmevtyper14_el0",   CPENC (3,3,C14,C13,6),	0),
-  SR_CORE ("pmevtyper15_el0",   CPENC (3,3,C14,C13,7),	0),
-  SR_CORE ("pmevtyper16_el0",   CPENC (3,3,C14,C14,0),	0),
-  SR_CORE ("pmevtyper17_el0",   CPENC (3,3,C14,C14,1),	0),
-  SR_CORE ("pmevtyper18_el0",   CPENC (3,3,C14,C14,2),	0),
-  SR_CORE ("pmevtyper19_el0",   CPENC (3,3,C14,C14,3),	0),
-  SR_CORE ("pmevtyper20_el0",   CPENC (3,3,C14,C14,4),	0),
-  SR_CORE ("pmevtyper21_el0",   CPENC (3,3,C14,C14,5),	0),
-  SR_CORE ("pmevtyper22_el0",   CPENC (3,3,C14,C14,6),	0),
-  SR_CORE ("pmevtyper23_el0",   CPENC (3,3,C14,C14,7),	0),
-  SR_CORE ("pmevtyper24_el0",   CPENC (3,3,C14,C15,0),	0),
-  SR_CORE ("pmevtyper25_el0",   CPENC (3,3,C14,C15,1),	0),
-  SR_CORE ("pmevtyper26_el0",   CPENC (3,3,C14,C15,2),	0),
-  SR_CORE ("pmevtyper27_el0",   CPENC (3,3,C14,C15,3),	0),
-  SR_CORE ("pmevtyper28_el0",   CPENC (3,3,C14,C15,4),	0),
-  SR_CORE ("pmevtyper29_el0",   CPENC (3,3,C14,C15,5),	0),
-  SR_CORE ("pmevtyper30_el0",   CPENC (3,3,C14,C15,6),	0),
-  SR_CORE ("pmccfiltr_el0",     CPENC (3,3,C14,C15,7),	0),
-
-  SR_V8_4A ("dit",		CPEN_ (3,C2,5),		0),
-  SR_V8_4A ("trfcr_el1",		CPENC (3,0,C1,C2,1),	0),
-  SR_V8_4A ("pmmir_el1",		CPENC (3,0,C9,C14,6),	F_REG_READ),
-  SR_V8_4A ("trfcr_el2",		CPENC (3,4,C1,C2,1),	0),
-  SR_V8_4A ("vstcr_el2",		CPENC (3,4,C2,C6,2),	0),
-  SR_V8_4_A ("vsttbr_el2",	CPENC (3,4,C2,C6,0),	0),
-  SR_V8_4A ("cnthvs_tval_el2",	CPENC (3,4,C14,C4,0),	0),
-  SR_V8_4A ("cnthvs_cval_el2",	CPENC (3,4,C14,C4,2),	0),
-  SR_V8_4A ("cnthvs_ctl_el2",	CPENC (3,4,C14,C4,1),	0),
-  SR_V8_4A ("cnthps_tval_el2",	CPENC (3,4,C14,C5,0),	0),
-  SR_V8_4A ("cnthps_cval_el2",	CPENC (3,4,C14,C5,2),	0),
-  SR_V8_4A ("cnthps_ctl_el2",	CPENC (3,4,C14,C5,1),	0),
-  SR_V8_4A ("sder32_el2",	CPENC (3,4,C1,C3,1),	0),
-  SR_V8_4A ("vncr_el2",		CPENC (3,4,C2,C2,0),	0),
-  SR_V8_4A ("trfcr_el12",	CPENC (3,5,C1,C2,1),	0),
-
-  SR_CORE ("mpam0_el1",		CPENC (3,0,C10,C5,1),	0),
-  SR_CORE ("mpam1_el1",		CPENC (3,0,C10,C5,0),	0),
-  SR_CORE ("mpam1_el12",	CPENC (3,5,C10,C5,0),	0),
-  SR_CORE ("mpam2_el2",		CPENC (3,4,C10,C5,0),	0),
-  SR_CORE ("mpam3_el3",		CPENC (3,6,C10,C5,0),	0),
-  SR_CORE ("mpamhcr_el2",	CPENC (3,4,C10,C4,0),	0),
-  SR_CORE ("mpamidr_el1",	CPENC (3,0,C10,C4,4),	F_REG_READ),
-  SR_CORE ("mpamvpm0_el2",	CPENC (3,4,C10,C6,0),	0),
-  SR_CORE ("mpamvpm1_el2",	CPENC (3,4,C10,C6,1),	0),
-  SR_CORE ("mpamvpm2_el2",	CPENC (3,4,C10,C6,2),	0),
-  SR_CORE ("mpamvpm3_el2",	CPENC (3,4,C10,C6,3),	0),
-  SR_CORE ("mpamvpm4_el2",	CPENC (3,4,C10,C6,4),	0),
-  SR_CORE ("mpamvpm5_el2",	CPENC (3,4,C10,C6,5),	0),
-  SR_CORE ("mpamvpm6_el2",	CPENC (3,4,C10,C6,6),	0),
-  SR_CORE ("mpamvpm7_el2",	CPENC (3,4,C10,C6,7),	0),
-  SR_CORE ("mpamvpmv_el2",	CPENC (3,4,C10,C4,1),	0),
-
-  SR_V8R ("mpuir_el1",		CPENC (3,0,C0,C0,4),	F_REG_READ),
-  SR_V8R ("mpuir_el2",		CPENC (3,4,C0,C0,4),	F_REG_READ),
-  SR_V8R ("prbar_el1",		CPENC (3,0,C6,C8,0),	0),
-  SR_V8R ("prbar_el2",		CPENC (3,4,C6,C8,0),	0),
-
-#define ENC_BARLAR(x,n,lar) \
-  CPENC (3, (x-1) << 2, C6, 8 | (n >> 1), ((n & 1) << 2) | lar)
-
-#define PRBARn_ELx(x,n) SR_V8R ("prbar" #n "_el" #x, ENC_BARLAR (x,n,0), 0)
-#define PRLARn_ELx(x,n) SR_V8R ("prlar" #n "_el" #x, ENC_BARLAR (x,n,1), 0)
-
-  SR_EXPAND_EL12 (PRBARn_ELx)
-  SR_V8R ("prenr_el1",		CPENC (3,0,C6,C1,1),	0),
-  SR_V8R ("prenr_el2",		CPENC (3,4,C6,C1,1),	0),
-  SR_V8R ("prlar_el1",		CPENC (3,0,C6,C8,1),	0),
-  SR_V8R ("prlar_el2",		CPENC (3,4,C6,C8,1),	0),
-  SR_EXPAND_EL12 (PRLARn_ELx)
-  SR_V8R ("prselr_el1",	CPENC (3,0,C6,C2,1),	0),
-  SR_V8R ("prselr_el2",	CPENC (3,4,C6,C2,1),	0),
-  SR_V8R ("vsctlr_el2",	CPENC (3,4,C2,C0,0),	0),
-
-  SR_CORE("trbbaser_el1", 	CPENC (3,0,C9,C11,2),	0),
-  SR_CORE("trbidr_el1", 	CPENC (3,0,C9,C11,7),	F_REG_READ),
-  SR_CORE("trblimitr_el1", 	CPENC (3,0,C9,C11,0),	0),
-  SR_CORE("trbmar_el1", 	CPENC (3,0,C9,C11,4),	0),
-  SR_CORE("trbptr_el1", 	CPENC (3,0,C9,C11,1),	0),
-  SR_CORE("trbsr_el1",  	CPENC (3,0,C9,C11,3),	0),
-  SR_CORE("trbtrg_el1", 	CPENC (3,0,C9,C11,6),	0),
-
-  SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ),
-  SR_CORE ("trccidr0",      CPENC (2,1,C7,C12,7), F_REG_READ),
-  SR_CORE ("trccidr1",      CPENC (2,1,C7,C13,7), F_REG_READ),
-  SR_CORE ("trccidr2",      CPENC (2,1,C7,C14,7), F_REG_READ),
-  SR_CORE ("trccidr3",      CPENC (2,1,C7,C15,7), F_REG_READ),
-  SR_CORE ("trcdevaff0",    CPENC (2,1,C7,C10,6), F_REG_READ),
-  SR_CORE ("trcdevaff1",    CPENC (2,1,C7,C11,6), F_REG_READ),
-  SR_CORE ("trcdevarch",    CPENC (2,1,C7,C15,6), F_REG_READ),
-  SR_CORE ("trcdevid",      CPENC (2,1,C7,C2,7),  F_REG_READ),
-  SR_CORE ("trcdevtype",    CPENC (2,1,C7,C3,7),  F_REG_READ),
-  SR_CORE ("trcidr0",       CPENC (2,1,C0,C8,7),  F_REG_READ),
-  SR_CORE ("trcidr1",       CPENC (2,1,C0,C9,7),  F_REG_READ),
-  SR_CORE ("trcidr2",       CPENC (2,1,C0,C10,7), F_REG_READ),
-  SR_CORE ("trcidr3",       CPENC (2,1,C0,C11,7), F_REG_READ),
-  SR_CORE ("trcidr4",       CPENC (2,1,C0,C12,7), F_REG_READ),
-  SR_CORE ("trcidr5",       CPENC (2,1,C0,C13,7), F_REG_READ),
-  SR_CORE ("trcidr6",       CPENC (2,1,C0,C14,7), F_REG_READ),
-  SR_CORE ("trcidr7",       CPENC (2,1,C0,C15,7), F_REG_READ),
-  SR_CORE ("trcidr8",       CPENC (2,1,C0,C0,6),  F_REG_READ),
-  SR_CORE ("trcidr9",       CPENC (2,1,C0,C1,6),  F_REG_READ),
-  SR_CORE ("trcidr10",      CPENC (2,1,C0,C2,6),  F_REG_READ),
-  SR_CORE ("trcidr11",      CPENC (2,1,C0,C3,6),  F_REG_READ),
-  SR_CORE ("trcidr12",      CPENC (2,1,C0,C4,6),  F_REG_READ),
-  SR_CORE ("trcidr13",      CPENC (2,1,C0,C5,6),  F_REG_READ),
-  SR_CORE ("trclsr",        CPENC (2,1,C7,C13,6), F_REG_READ),
-  SR_CORE ("trcoslsr",      CPENC (2,1,C1,C1,4),  F_REG_READ),
-  SR_CORE ("trcpdsr",       CPENC (2,1,C1,C5,4),  F_REG_READ),
-  SR_CORE ("trcpidr0",      CPENC (2,1,C7,C8,7),  F_REG_READ),
-  SR_CORE ("trcpidr1",      CPENC (2,1,C7,C9,7),  F_REG_READ),
-  SR_CORE ("trcpidr2",      CPENC (2,1,C7,C10,7), F_REG_READ),
-  SR_CORE ("trcpidr3",      CPENC (2,1,C7,C11,7), F_REG_READ),
-  SR_CORE ("trcpidr4",      CPENC (2,1,C7,C4,7),  F_REG_READ),
-  SR_CORE ("trcpidr5",      CPENC (2,1,C7,C5,7),  F_REG_READ),
-  SR_CORE ("trcpidr6",      CPENC (2,1,C7,C6,7),  F_REG_READ),
-  SR_CORE ("trcpidr7",      CPENC (2,1,C7,C7,7),  F_REG_READ),
-  SR_CORE ("trcstatr",      CPENC (2,1,C0,C3,0),  F_REG_READ),
-  SR_CORE ("trcacatr0",     CPENC (2,1,C2,C0,2),  0),
-  SR_CORE ("trcacatr1",     CPENC (2,1,C2,C2,2),  0),
-  SR_CORE ("trcacatr2",     CPENC (2,1,C2,C4,2),  0),
-  SR_CORE ("trcacatr3",     CPENC (2,1,C2,C6,2),  0),
-  SR_CORE ("trcacatr4",     CPENC (2,1,C2,C8,2),  0),
-  SR_CORE ("trcacatr5",     CPENC (2,1,C2,C10,2), 0),
-  SR_CORE ("trcacatr6",     CPENC (2,1,C2,C12,2), 0),
-  SR_CORE ("trcacatr7",     CPENC (2,1,C2,C14,2), 0),
-  SR_CORE ("trcacatr8",     CPENC (2,1,C2,C0,3),  0),
-  SR_CORE ("trcacatr9",     CPENC (2,1,C2,C2,3),  0),
-  SR_CORE ("trcacatr10",    CPENC (2,1,C2,C4,3),  0),
-  SR_CORE ("trcacatr11",    CPENC (2,1,C2,C6,3),  0),
-  SR_CORE ("trcacatr12",    CPENC (2,1,C2,C8,3),  0),
-  SR_CORE ("trcacatr13",    CPENC (2,1,C2,C10,3), 0),
-  SR_CORE ("trcacatr14",    CPENC (2,1,C2,C12,3), 0),
-  SR_CORE ("trcacatr15",    CPENC (2,1,C2,C14,3), 0),
-  SR_CORE ("trcacvr0",      CPENC (2,1,C2,C0,0),  0),
-  SR_CORE ("trcacvr1",      CPENC (2,1,C2,C2,0),  0),
-  SR_CORE ("trcacvr2",      CPENC (2,1,C2,C4,0),  0),
-  SR_CORE ("trcacvr3",      CPENC (2,1,C2,C6,0),  0),
-  SR_CORE ("trcacvr4",      CPENC (2,1,C2,C8,0),  0),
-  SR_CORE ("trcacvr5",      CPENC (2,1,C2,C10,0), 0),
-  SR_CORE ("trcacvr6",      CPENC (2,1,C2,C12,0), 0),
-  SR_CORE ("trcacvr7",      CPENC (2,1,C2,C14,0), 0),
-  SR_CORE ("trcacvr8",      CPENC (2,1,C2,C0,1),  0),
-  SR_CORE ("trcacvr9",      CPENC (2,1,C2,C2,1),  0),
-  SR_CORE ("trcacvr10",     CPENC (2,1,C2,C4,1),  0),
-  SR_CORE ("trcacvr11",     CPENC (2,1,C2,C6,1),  0),
-  SR_CORE ("trcacvr12",     CPENC (2,1,C2,C8,1),  0),
-  SR_CORE ("trcacvr13",     CPENC (2,1,C2,C10,1), 0),
-  SR_CORE ("trcacvr14",     CPENC (2,1,C2,C12,1), 0),
-  SR_CORE ("trcacvr15",     CPENC (2,1,C2,C14,1), 0),
-  SR_CORE ("trcauxctlr",    CPENC (2,1,C0,C6,0),  0),
-  SR_CORE ("trcbbctlr",     CPENC (2,1,C0,C15,0), 0),
-  SR_CORE ("trcccctlr",     CPENC (2,1,C0,C14,0), 0),
-  SR_CORE ("trccidcctlr0",  CPENC (2,1,C3,C0,2),  0),
-  SR_CORE ("trccidcctlr1",  CPENC (2,1,C3,C1,2),  0),
-  SR_CORE ("trccidcvr0",    CPENC (2,1,C3,C0,0),  0),
-  SR_CORE ("trccidcvr1",    CPENC (2,1,C3,C2,0),  0),
-  SR_CORE ("trccidcvr2",    CPENC (2,1,C3,C4,0),  0),
-  SR_CORE ("trccidcvr3",    CPENC (2,1,C3,C6,0),  0),
-  SR_CORE ("trccidcvr4",    CPENC (2,1,C3,C8,0),  0),
-  SR_CORE ("trccidcvr5",    CPENC (2,1,C3,C10,0), 0),
-  SR_CORE ("trccidcvr6",    CPENC (2,1,C3,C12,0), 0),
-  SR_CORE ("trccidcvr7",    CPENC (2,1,C3,C14,0), 0),
-  SR_CORE ("trcclaimclr",   CPENC (2,1,C7,C9,6),  0),
-  SR_CORE ("trcclaimset",   CPENC (2,1,C7,C8,6),  0),
-  SR_CORE ("trccntctlr0",   CPENC (2,1,C0,C4,5),  0),
-  SR_CORE ("trccntctlr1",   CPENC (2,1,C0,C5,5),  0),
-  SR_CORE ("trccntctlr2",   CPENC (2,1,C0,C6,5),  0),
-  SR_CORE ("trccntctlr3",   CPENC (2,1,C0,C7,5),  0),
-  SR_CORE ("trccntrldvr0",  CPENC (2,1,C0,C0,5),  0),
-  SR_CORE ("trccntrldvr1",  CPENC (2,1,C0,C1,5),  0),
-  SR_CORE ("trccntrldvr2",  CPENC (2,1,C0,C2,5),  0),
-  SR_CORE ("trccntrldvr3",  CPENC (2,1,C0,C3,5),  0),
-  SR_CORE ("trccntvr0",     CPENC (2,1,C0,C8,5),  0),
-  SR_CORE ("trccntvr1",     CPENC (2,1,C0,C9,5),  0),
-  SR_CORE ("trccntvr2",     CPENC (2,1,C0,C10,5), 0),
-  SR_CORE ("trccntvr3",     CPENC (2,1,C0,C11,5), 0),
-  SR_CORE ("trcconfigr",    CPENC (2,1,C0,C4,0),  0),
-  SR_CORE ("trcdvcmr0",     CPENC (2,1,C2,C0,6),  0),
-  SR_CORE ("trcdvcmr1",     CPENC (2,1,C2,C4,6),  0),
-  SR_CORE ("trcdvcmr2",     CPENC (2,1,C2,C8,6),  0),
-  SR_CORE ("trcdvcmr3",     CPENC (2,1,C2,C12,6), 0),
-  SR_CORE ("trcdvcmr4",     CPENC (2,1,C2,C0,7),  0),
-  SR_CORE ("trcdvcmr5",     CPENC (2,1,C2,C4,7),  0),
-  SR_CORE ("trcdvcmr6",     CPENC (2,1,C2,C8,7),  0),
-  SR_CORE ("trcdvcmr7",     CPENC (2,1,C2,C12,7), 0),
-  SR_CORE ("trcdvcvr0",     CPENC (2,1,C2,C0,4),  0),
-  SR_CORE ("trcdvcvr1",     CPENC (2,1,C2,C4,4),  0),
-  SR_CORE ("trcdvcvr2",     CPENC (2,1,C2,C8,4),  0),
-  SR_CORE ("trcdvcvr3",     CPENC (2,1,C2,C12,4), 0),
-  SR_CORE ("trcdvcvr4",     CPENC (2,1,C2,C0,5),  0),
-  SR_CORE ("trcdvcvr5",     CPENC (2,1,C2,C4,5),  0),
-  SR_CORE ("trcdvcvr6",     CPENC (2,1,C2,C8,5),  0),
-  SR_CORE ("trcdvcvr7",     CPENC (2,1,C2,C12,5), 0),
-  SR_CORE ("trceventctl0r", CPENC (2,1,C0,C8,0),  0),
-  SR_CORE ("trceventctl1r", CPENC (2,1,C0,C9,0),  0),
-  SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4),  0),
-  SR_CORE ("trcextinselr",  CPENC (2,1,C0,C8,4),  0),
-  SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4),  0),
-  SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
-  SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
-  SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0),
-  SR_CORE ("trcimspec1",    CPENC (2,1,C0,C1,7),  0),
-  SR_CORE ("trcimspec2",    CPENC (2,1,C0,C2,7),  0),
-  SR_CORE ("trcimspec3",    CPENC (2,1,C0,C3,7),  0),
-  SR_CORE ("trcimspec4",    CPENC (2,1,C0,C4,7),  0),
-  SR_CORE ("trcimspec5",    CPENC (2,1,C0,C5,7),  0),
-  SR_CORE ("trcimspec6",    CPENC (2,1,C0,C6,7),  0),
-  SR_CORE ("trcimspec7",    CPENC (2,1,C0,C7,7),  0),
-  SR_CORE ("trcitctrl",     CPENC (2,1,C7,C0,4),  0),
-  SR_CORE ("trcpdcr",       CPENC (2,1,C1,C4,4),  0),
-  SR_CORE ("trcprgctlr",    CPENC (2,1,C0,C1,0),  0),
-  SR_CORE ("trcprocselr",   CPENC (2,1,C0,C2,0),  0),
-  SR_CORE ("trcqctlr",      CPENC (2,1,C0,C1,1),  0),
-  SR_CORE ("trcrsr",        CPENC (2,1,C0,C10,0), 0),
-  SR_CORE ("trcrsctlr2",    CPENC (2,1,C1,C2,0),  0),
-  SR_CORE ("trcrsctlr3",    CPENC (2,1,C1,C3,0),  0),
-  SR_CORE ("trcrsctlr4",    CPENC (2,1,C1,C4,0),  0),
-  SR_CORE ("trcrsctlr5",    CPENC (2,1,C1,C5,0),  0),
-  SR_CORE ("trcrsctlr6",    CPENC (2,1,C1,C6,0),  0),
-  SR_CORE ("trcrsctlr7",    CPENC (2,1,C1,C7,0),  0),
-  SR_CORE ("trcrsctlr8",    CPENC (2,1,C1,C8,0),  0),
-  SR_CORE ("trcrsctlr9",    CPENC (2,1,C1,C9,0),  0),
-  SR_CORE ("trcrsctlr10",   CPENC (2,1,C1,C10,0), 0),
-  SR_CORE ("trcrsctlr11",   CPENC (2,1,C1,C11,0), 0),
-  SR_CORE ("trcrsctlr12",   CPENC (2,1,C1,C12,0), 0),
-  SR_CORE ("trcrsctlr13",   CPENC (2,1,C1,C13,0), 0),
-  SR_CORE ("trcrsctlr14",   CPENC (2,1,C1,C14,0), 0),
-  SR_CORE ("trcrsctlr15",   CPENC (2,1,C1,C15,0), 0),
-  SR_CORE ("trcrsctlr16",   CPENC (2,1,C1,C0,1),  0),
-  SR_CORE ("trcrsctlr17",   CPENC (2,1,C1,C1,1),  0),
-  SR_CORE ("trcrsctlr18",   CPENC (2,1,C1,C2,1),  0),
-  SR_CORE ("trcrsctlr19",   CPENC (2,1,C1,C3,1),  0),
-  SR_CORE ("trcrsctlr20",   CPENC (2,1,C1,C4,1),  0),
-  SR_CORE ("trcrsctlr21",   CPENC (2,1,C1,C5,1),  0),
-  SR_CORE ("trcrsctlr22",   CPENC (2,1,C1,C6,1),  0),
-  SR_CORE ("trcrsctlr23",   CPENC (2,1,C1,C7,1),  0),
-  SR_CORE ("trcrsctlr24",   CPENC (2,1,C1,C8,1),  0),
-  SR_CORE ("trcrsctlr25",   CPENC (2,1,C1,C9,1),  0),
-  SR_CORE ("trcrsctlr26",   CPENC (2,1,C1,C10,1), 0),
-  SR_CORE ("trcrsctlr27",   CPENC (2,1,C1,C11,1), 0),
-  SR_CORE ("trcrsctlr28",   CPENC (2,1,C1,C12,1), 0),
-  SR_CORE ("trcrsctlr29",   CPENC (2,1,C1,C13,1), 0),
-  SR_CORE ("trcrsctlr30",   CPENC (2,1,C1,C14,1), 0),
-  SR_CORE ("trcrsctlr31",   CPENC (2,1,C1,C15,1), 0),
-  SR_CORE ("trcseqevr0",    CPENC (2,1,C0,C0,4),  0),
-  SR_CORE ("trcseqevr1",    CPENC (2,1,C0,C1,4),  0),
-  SR_CORE ("trcseqevr2",    CPENC (2,1,C0,C2,4),  0),
-  SR_CORE ("trcseqrstevr",  CPENC (2,1,C0,C6,4),  0),
-  SR_CORE ("trcseqstr",     CPENC (2,1,C0,C7,4),  0),
-  SR_CORE ("trcssccr0",     CPENC (2,1,C1,C0,2),  0),
-  SR_CORE ("trcssccr1",     CPENC (2,1,C1,C1,2),  0),
-  SR_CORE ("trcssccr2",     CPENC (2,1,C1,C2,2),  0),
-  SR_CORE ("trcssccr3",     CPENC (2,1,C1,C3,2),  0),
-  SR_CORE ("trcssccr4",     CPENC (2,1,C1,C4,2),  0),
-  SR_CORE ("trcssccr5",     CPENC (2,1,C1,C5,2),  0),
-  SR_CORE ("trcssccr6",     CPENC (2,1,C1,C6,2),  0),
-  SR_CORE ("trcssccr7",     CPENC (2,1,C1,C7,2),  0),
-  SR_CORE ("trcsscsr0",     CPENC (2,1,C1,C8,2),  0),
-  SR_CORE ("trcsscsr1",     CPENC (2,1,C1,C9,2),  0),
-  SR_CORE ("trcsscsr2",     CPENC (2,1,C1,C10,2), 0),
-  SR_CORE ("trcsscsr3",     CPENC (2,1,C1,C11,2), 0),
-  SR_CORE ("trcsscsr4",     CPENC (2,1,C1,C12,2), 0),
-  SR_CORE ("trcsscsr5",     CPENC (2,1,C1,C13,2), 0),
-  SR_CORE ("trcsscsr6",     CPENC (2,1,C1,C14,2), 0),
-  SR_CORE ("trcsscsr7",     CPENC (2,1,C1,C15,2), 0),
-  SR_CORE ("trcsspcicr0",   CPENC (2,1,C1,C0,3),  0),
-  SR_CORE ("trcsspcicr1",   CPENC (2,1,C1,C1,3),  0),
-  SR_CORE ("trcsspcicr2",   CPENC (2,1,C1,C2,3),  0),
-  SR_CORE ("trcsspcicr3",   CPENC (2,1,C1,C3,3),  0),
-  SR_CORE ("trcsspcicr4",   CPENC (2,1,C1,C4,3),  0),
-  SR_CORE ("trcsspcicr5",   CPENC (2,1,C1,C5,3),  0),
-  SR_CORE ("trcsspcicr6",   CPENC (2,1,C1,C6,3),  0),
-  SR_CORE ("trcsspcicr7",   CPENC (2,1,C1,C7,3),  0),
-  SR_CORE ("trcstallctlr",  CPENC (2,1,C0,C11,0), 0),
-  SR_CORE ("trcsyncpr",     CPENC (2,1,C0,C13,0), 0),
-  SR_CORE ("trctraceidr",   CPENC (2,1,C0,C0,1),  0),
-  SR_CORE ("trctsctlr",     CPENC (2,1,C0,C12,0), 0),
-  SR_CORE ("trcvdarcctlr",  CPENC (2,1,C0,C10,2), 0),
-  SR_CORE ("trcvdctlr",     CPENC (2,1,C0,C8,2),  0),
-  SR_CORE ("trcvdsacctlr",  CPENC (2,1,C0,C9,2),  0),
-  SR_CORE ("trcvictlr",     CPENC (2,1,C0,C0,2),  0),
-  SR_CORE ("trcviiectlr",   CPENC (2,1,C0,C1,2),  0),
-  SR_CORE ("trcvipcssctlr", CPENC (2,1,C0,C3,2),  0),
-  SR_CORE ("trcvissctlr",   CPENC (2,1,C0,C2,2),  0),
-  SR_CORE ("trcvmidcctlr0", CPENC (2,1,C3,C2,2),  0),
-  SR_CORE ("trcvmidcctlr1", CPENC (2,1,C3,C3,2),  0),
-  SR_CORE ("trcvmidcvr0",   CPENC (2,1,C3,C0,1),  0),
-  SR_CORE ("trcvmidcvr1",   CPENC (2,1,C3,C2,1),  0),
-  SR_CORE ("trcvmidcvr2",   CPENC (2,1,C3,C4,1),  0),
-  SR_CORE ("trcvmidcvr3",   CPENC (2,1,C3,C6,1),  0),
-  SR_CORE ("trcvmidcvr4",   CPENC (2,1,C3,C8,1),  0),
-  SR_CORE ("trcvmidcvr5",   CPENC (2,1,C3,C10,1), 0),
-  SR_CORE ("trcvmidcvr6",   CPENC (2,1,C3,C12,1), 0),
-  SR_CORE ("trcvmidcvr7",   CPENC (2,1,C3,C14,1), 0),
-  SR_CORE ("trclar",        CPENC (2,1,C7,C12,6), F_REG_WRITE),
-  SR_CORE ("trcoslar",      CPENC (2,1,C1,C0,4),  F_REG_WRITE),
-
-  SR_CORE ("csrcr_el0",     CPENC (2,3,C8,C0,0),  0),
-  SR_CORE ("csrptr_el0",    CPENC (2,3,C8,C0,1),  0),
-  SR_CORE ("csridr_el0",    CPENC (2,3,C8,C0,2),  F_REG_READ),
-  SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3),  F_REG_READ),
-  SR_CORE ("csrcr_el1",     CPENC (2,0,C8,C0,0),  0),
-  SR_CORE ("csrcr_el12",    CPENC (2,5,C8,C0,0),  0),
-  SR_CORE ("csrptr_el1",    CPENC (2,0,C8,C0,1),  0),
-  SR_CORE ("csrptr_el12",   CPENC (2,5,C8,C0,1),  0),
-  SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3),  F_REG_READ),
-  SR_CORE ("csrcr_el2",     CPENC (2,4,C8,C0,0),  0),
-  SR_CORE ("csrptr_el2",    CPENC (2,4,C8,C0,1),  0),
-  SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3),  F_REG_READ),
-
-  SR_LOR ("lorid_el1",      CPENC (3,0,C10,C4,7),  F_REG_READ),
-  SR_LOR ("lorc_el1",       CPENC (3,0,C10,C4,3),  0),
-  SR_LOR ("lorea_el1",      CPENC (3,0,C10,C4,1),  0),
-  SR_LOR ("lorn_el1",       CPENC (3,0,C10,C4,2),  0),
-  SR_LOR ("lorsa_el1",      CPENC (3,0,C10,C4,0),  0),
-
-  SR_CORE ("icc_ctlr_el3",  CPENC (3,6,C12,C12,4), 0),
-  SR_CORE ("icc_sre_el1",   CPENC (3,0,C12,C12,5), 0),
-  SR_CORE ("icc_sre_el2",   CPENC (3,4,C12,C9,5),  0),
-  SR_CORE ("icc_sre_el3",   CPENC (3,6,C12,C12,5), 0),
-  SR_CORE ("ich_vtr_el2",   CPENC (3,4,C12,C11,1), F_REG_READ),
-
-  SR_CORE ("brbcr_el1",     CPENC (2,1,C9,C0,0),  0),
-  SR_CORE ("brbcr_el12",    CPENC (2,5,C9,C0,0),  0),
-  SR_CORE ("brbfcr_el1",    CPENC (2,1,C9,C0,1),  0),
-  SR_CORE ("brbts_el1",     CPENC (2,1,C9,C0,2),  0),
-  SR_CORE ("brbinfinj_el1", CPENC (2,1,C9,C1,0),  0),
-  SR_CORE ("brbsrcinj_el1", CPENC (2,1,C9,C1,1),  0),
-  SR_CORE ("brbtgtinj_el1", CPENC (2,1,C9,C1,2),  0),
-  SR_CORE ("brbidr0_el1",   CPENC (2,1,C9,C2,0),  F_REG_READ),
-  SR_CORE ("brbcr_el2",     CPENC (2,4,C9,C0,0),  0),
-  SR_CORE ("brbsrc0_el1",   CPENC (2,1,C8,C0,1),  F_REG_READ),
-  SR_CORE ("brbsrc1_el1",   CPENC (2,1,C8,C1,1),  F_REG_READ),
-  SR_CORE ("brbsrc2_el1",   CPENC (2,1,C8,C2,1),  F_REG_READ),
-  SR_CORE ("brbsrc3_el1",   CPENC (2,1,C8,C3,1),  F_REG_READ),
-  SR_CORE ("brbsrc4_el1",   CPENC (2,1,C8,C4,1),  F_REG_READ),
-  SR_CORE ("brbsrc5_el1",   CPENC (2,1,C8,C5,1),  F_REG_READ),
-  SR_CORE ("brbsrc6_el1",   CPENC (2,1,C8,C6,1),  F_REG_READ),
-  SR_CORE ("brbsrc7_el1",   CPENC (2,1,C8,C7,1),  F_REG_READ),
-  SR_CORE ("brbsrc8_el1",   CPENC (2,1,C8,C8,1),  F_REG_READ),
-  SR_CORE ("brbsrc9_el1",   CPENC (2,1,C8,C9,1),  F_REG_READ),
-  SR_CORE ("brbsrc10_el1",  CPENC (2,1,C8,C10,1), F_REG_READ),
-  SR_CORE ("brbsrc11_el1",  CPENC (2,1,C8,C11,1), F_REG_READ),
-  SR_CORE ("brbsrc12_el1",  CPENC (2,1,C8,C12,1), F_REG_READ),
-  SR_CORE ("brbsrc13_el1",  CPENC (2,1,C8,C13,1), F_REG_READ),
-  SR_CORE ("brbsrc14_el1",  CPENC (2,1,C8,C14,1), F_REG_READ),
-  SR_CORE ("brbsrc15_el1",  CPENC (2,1,C8,C15,1), F_REG_READ),
-  SR_CORE ("brbsrc16_el1",  CPENC (2,1,C8,C0,5),  F_REG_READ),
-  SR_CORE ("brbsrc17_el1",  CPENC (2,1,C8,C1,5),  F_REG_READ),
-  SR_CORE ("brbsrc18_el1",  CPENC (2,1,C8,C2,5),  F_REG_READ),
-  SR_CORE ("brbsrc19_el1",  CPENC (2,1,C8,C3,5),  F_REG_READ),
-  SR_CORE ("brbsrc20_el1",  CPENC (2,1,C8,C4,5),  F_REG_READ),
-  SR_CORE ("brbsrc21_el1",  CPENC (2,1,C8,C5,5),  F_REG_READ),
-  SR_CORE ("brbsrc22_el1",  CPENC (2,1,C8,C6,5),  F_REG_READ),
-  SR_CORE ("brbsrc23_el1",  CPENC (2,1,C8,C7,5),  F_REG_READ),
-  SR_CORE ("brbsrc24_el1",  CPENC (2,1,C8,C8,5),  F_REG_READ),
-  SR_CORE ("brbsrc25_el1",  CPENC (2,1,C8,C9,5),  F_REG_READ),
-  SR_CORE ("brbsrc26_el1",  CPENC (2,1,C8,C10,5), F_REG_READ),
-  SR_CORE ("brbsrc27_el1",  CPENC (2,1,C8,C11,5), F_REG_READ),
-  SR_CORE ("brbsrc28_el1",  CPENC (2,1,C8,C12,5), F_REG_READ),
-  SR_CORE ("brbsrc29_el1",  CPENC (2,1,C8,C13,5), F_REG_READ),
-  SR_CORE ("brbsrc30_el1",  CPENC (2,1,C8,C14,5), F_REG_READ),
-  SR_CORE ("brbsrc31_el1",  CPENC (2,1,C8,C15,5), F_REG_READ),
-  SR_CORE ("brbtgt0_el1",   CPENC (2,1,C8,C0,2),  F_REG_READ),
-  SR_CORE ("brbtgt1_el1",   CPENC (2,1,C8,C1,2),  F_REG_READ),
-  SR_CORE ("brbtgt2_el1",   CPENC (2,1,C8,C2,2),  F_REG_READ),
-  SR_CORE ("brbtgt3_el1",   CPENC (2,1,C8,C3,2),  F_REG_READ),
-  SR_CORE ("brbtgt4_el1",   CPENC (2,1,C8,C4,2),  F_REG_READ),
-  SR_CORE ("brbtgt5_el1",   CPENC (2,1,C8,C5,2),  F_REG_READ),
-  SR_CORE ("brbtgt6_el1",   CPENC (2,1,C8,C6,2),  F_REG_READ),
-  SR_CORE ("brbtgt7_el1",   CPENC (2,1,C8,C7,2),  F_REG_READ),
-  SR_CORE ("brbtgt8_el1",   CPENC (2,1,C8,C8,2),  F_REG_READ),
-  SR_CORE ("brbtgt9_el1",   CPENC (2,1,C8,C9,2),  F_REG_READ),
-  SR_CORE ("brbtgt10_el1",  CPENC (2,1,C8,C10,2), F_REG_READ),
-  SR_CORE ("brbtgt11_el1",  CPENC (2,1,C8,C11,2), F_REG_READ),
-  SR_CORE ("brbtgt12_el1",  CPENC (2,1,C8,C12,2), F_REG_READ),
-  SR_CORE ("brbtgt13_el1",  CPENC (2,1,C8,C13,2), F_REG_READ),
-  SR_CORE ("brbtgt14_el1",  CPENC (2,1,C8,C14,2), F_REG_READ),
-  SR_CORE ("brbtgt15_el1",  CPENC (2,1,C8,C15,2), F_REG_READ),
-  SR_CORE ("brbtgt16_el1",  CPENC (2,1,C8,C0,6),  F_REG_READ),
-  SR_CORE ("brbtgt17_el1",  CPENC (2,1,C8,C1,6),  F_REG_READ),
-  SR_CORE ("brbtgt18_el1",  CPENC (2,1,C8,C2,6),  F_REG_READ),
-  SR_CORE ("brbtgt19_el1",  CPENC (2,1,C8,C3,6),  F_REG_READ),
-  SR_CORE ("brbtgt20_el1",  CPENC (2,1,C8,C4,6),  F_REG_READ),
-  SR_CORE ("brbtgt21_el1",  CPENC (2,1,C8,C5,6),  F_REG_READ),
-  SR_CORE ("brbtgt22_el1",  CPENC (2,1,C8,C6,6),  F_REG_READ),
-  SR_CORE ("brbtgt23_el1",  CPENC (2,1,C8,C7,6),  F_REG_READ),
-  SR_CORE ("brbtgt24_el1",  CPENC (2,1,C8,C8,6),  F_REG_READ),
-  SR_CORE ("brbtgt25_el1",  CPENC (2,1,C8,C9,6),  F_REG_READ),
-  SR_CORE ("brbtgt26_el1",  CPENC (2,1,C8,C10,6), F_REG_READ),
-  SR_CORE ("brbtgt27_el1",  CPENC (2,1,C8,C11,6), F_REG_READ),
-  SR_CORE ("brbtgt28_el1",  CPENC (2,1,C8,C12,6), F_REG_READ),
-  SR_CORE ("brbtgt29_el1",  CPENC (2,1,C8,C13,6), F_REG_READ),
-  SR_CORE ("brbtgt30_el1",  CPENC (2,1,C8,C14,6), F_REG_READ),
-  SR_CORE ("brbtgt31_el1",  CPENC (2,1,C8,C15,6), F_REG_READ),
-  SR_CORE ("brbinf0_el1",   CPENC (2,1,C8,C0,0),  F_REG_READ),
-  SR_CORE ("brbinf1_el1",   CPENC (2,1,C8,C1,0),  F_REG_READ),
-  SR_CORE ("brbinf2_el1",   CPENC (2,1,C8,C2,0),  F_REG_READ),
-  SR_CORE ("brbinf3_el1",   CPENC (2,1,C8,C3,0),  F_REG_READ),
-  SR_CORE ("brbinf4_el1",   CPENC (2,1,C8,C4,0),  F_REG_READ),
-  SR_CORE ("brbinf5_el1",   CPENC (2,1,C8,C5,0),  F_REG_READ),
-  SR_CORE ("brbinf6_el1",   CPENC (2,1,C8,C6,0),  F_REG_READ),
-  SR_CORE ("brbinf7_el1",   CPENC (2,1,C8,C7,0),  F_REG_READ),
-  SR_CORE ("brbinf8_el1",   CPENC (2,1,C8,C8,0),  F_REG_READ),
-  SR_CORE ("brbinf9_el1",   CPENC (2,1,C8,C9,0),  F_REG_READ),
-  SR_CORE ("brbinf10_el1",  CPENC (2,1,C8,C10,0), F_REG_READ),
-  SR_CORE ("brbinf11_el1",  CPENC (2,1,C8,C11,0), F_REG_READ),
-  SR_CORE ("brbinf12_el1",  CPENC (2,1,C8,C12,0), F_REG_READ),
-  SR_CORE ("brbinf13_el1",  CPENC (2,1,C8,C13,0), F_REG_READ),
-  SR_CORE ("brbinf14_el1",  CPENC (2,1,C8,C14,0), F_REG_READ),
-  SR_CORE ("brbinf15_el1",  CPENC (2,1,C8,C15,0), F_REG_READ),
-  SR_CORE ("brbinf16_el1",  CPENC (2,1,C8,C0,4),  F_REG_READ),
-  SR_CORE ("brbinf17_el1",  CPENC (2,1,C8,C1,4),  F_REG_READ),
-  SR_CORE ("brbinf18_el1",  CPENC (2,1,C8,C2,4),  F_REG_READ),
-  SR_CORE ("brbinf19_el1",  CPENC (2,1,C8,C3,4),  F_REG_READ),
-  SR_CORE ("brbinf20_el1",  CPENC (2,1,C8,C4,4),  F_REG_READ),
-  SR_CORE ("brbinf21_el1",  CPENC (2,1,C8,C5,4),  F_REG_READ),
-  SR_CORE ("brbinf22_el1",  CPENC (2,1,C8,C6,4),  F_REG_READ),
-  SR_CORE ("brbinf23_el1",  CPENC (2,1,C8,C7,4),  F_REG_READ),
-  SR_CORE ("brbinf24_el1",  CPENC (2,1,C8,C8,4),  F_REG_READ),
-  SR_CORE ("brbinf25_el1",  CPENC (2,1,C8,C9,4),  F_REG_READ),
-  SR_CORE ("brbinf26_el1",  CPENC (2,1,C8,C10,4), F_REG_READ),
-  SR_CORE ("brbinf27_el1",  CPENC (2,1,C8,C11,4), F_REG_READ),
-  SR_CORE ("brbinf28_el1",  CPENC (2,1,C8,C12,4), F_REG_READ),
-  SR_CORE ("brbinf29_el1",  CPENC (2,1,C8,C13,4), F_REG_READ),
-  SR_CORE ("brbinf30_el1",  CPENC (2,1,C8,C14,4), F_REG_READ),
-  SR_CORE ("brbinf31_el1",  CPENC (2,1,C8,C15,4), F_REG_READ),
-
-  SR_CORE ("accdata_el1",   CPENC (3,0,C13,C0,5), 0),
-
-  SR_CORE ("mfar_el3",      CPENC (3,6,C6,C0,5), 0),
-  SR_CORE ("gpccr_el3",     CPENC (3,6,C2,C1,6), 0),
-  SR_CORE ("gptbr_el3",     CPENC (3,6,C2,C1,4), 0),
-
-  SR_CORE ("mecidr_el2",    CPENC (3,4,C10,C8,7),  F_REG_READ),
-  SR_CORE ("mecid_p0_el2",  CPENC (3,4,C10,C8,0),  0),
-  SR_CORE ("mecid_a0_el2",  CPENC (3,4,C10,C8,1),  0),
-  SR_CORE ("mecid_p1_el2",  CPENC (3,4,C10,C8,2),  0),
-  SR_CORE ("mecid_a1_el2",  CPENC (3,4,C10,C8,3),  0),
-  SR_CORE ("vmecid_p_el2",  CPENC (3,4,C10,C9,0),  0),
-  SR_CORE ("vmecid_a_el2",  CPENC (3,4,C10,C9,1),  0),
-  SR_CORE ("mecid_rl_a_el3",CPENC (3,6,C10,C10,1), 0),
-
-  SR_SME ("svcr",             CPENC (3,3,C4,C2,2),  0),
-  SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5),  F_REG_READ),
-  SR_SME ("smcr_el1",         CPENC (3,0,C1,C2,6),  0),
-  SR_SME ("smcr_el12",        CPENC (3,5,C1,C2,6),  0),
-  SR_SME ("smcr_el2",         CPENC (3,4,C1,C2,6),  0),
-  SR_SME ("smcr_el3",         CPENC (3,6,C1,C2,6),  0),
-  SR_SME ("smpri_el1",        CPENC (3,0,C1,C2,4),  0),
-  SR_SME ("smprimap_el2",     CPENC (3,4,C1,C2,5),  0),
-  SR_SME ("smidr_el1",        CPENC (3,1,C0,C0,6),  F_REG_READ),
-  SR_SME ("tpidr2_el0",       CPENC (3,3,C13,C0,5), 0),
-  SR_SME ("mpamsm_el1",       CPENC (3,0,C10,C5,3), 0),
-
-  SR_AMU ("amcr_el0",           CPENC (3,3,C13,C2,0),   0),
-  SR_AMU ("amcfgr_el0",         CPENC (3,3,C13,C2,1),   F_REG_READ),
-  SR_AMU ("amcgcr_el0",         CPENC (3,3,C13,C2,2),   F_REG_READ),
-  SR_AMU ("amuserenr_el0",      CPENC (3,3,C13,C2,3),   0),
-  SR_AMU ("amcntenclr0_el0",    CPENC (3,3,C13,C2,4),   0),
-  SR_AMU ("amcntenset0_el0",    CPENC (3,3,C13,C2,5),   0),
-  SR_AMU ("amcntenclr1_el0",    CPENC (3,3,C13,C3,0),   0),
-  SR_AMU ("amcntenset1_el0",    CPENC (3,3,C13,C3,1),   0),
-  SR_AMU ("amevcntr00_el0",     CPENC (3,3,C13,C4,0),   0),
-  SR_AMU ("amevcntr01_el0",     CPENC (3,3,C13,C4,1),   0),
-  SR_AMU ("amevcntr02_el0",     CPENC (3,3,C13,C4,2),   0),
-  SR_AMU ("amevcntr03_el0",     CPENC (3,3,C13,C4,3),   0),
-  SR_AMU ("amevtyper00_el0",    CPENC (3,3,C13,C6,0),   F_REG_READ),
-  SR_AMU ("amevtyper01_el0",    CPENC (3,3,C13,C6,1),   F_REG_READ),
-  SR_AMU ("amevtyper02_el0",    CPENC (3,3,C13,C6,2),   F_REG_READ),
-  SR_AMU ("amevtyper03_el0",    CPENC (3,3,C13,C6,3),   F_REG_READ),
-  SR_AMU ("amevcntr10_el0",     CPENC (3,3,C13,C12,0),  0),
-  SR_AMU ("amevcntr11_el0",     CPENC (3,3,C13,C12,1),  0),
-  SR_AMU ("amevcntr12_el0",     CPENC (3,3,C13,C12,2),  0),
-  SR_AMU ("amevcntr13_el0",     CPENC (3,3,C13,C12,3),  0),
-  SR_AMU ("amevcntr14_el0",     CPENC (3,3,C13,C12,4),  0),
-  SR_AMU ("amevcntr15_el0",     CPENC (3,3,C13,C12,5),  0),
-  SR_AMU ("amevcntr16_el0",     CPENC (3,3,C13,C12,6),  0),
-  SR_AMU ("amevcntr17_el0",     CPENC (3,3,C13,C12,7),  0),
-  SR_AMU ("amevcntr18_el0",     CPENC (3,3,C13,C13,0),  0),
-  SR_AMU ("amevcntr19_el0",     CPENC (3,3,C13,C13,1),  0),
-  SR_AMU ("amevcntr110_el0",    CPENC (3,3,C13,C13,2),  0),
-  SR_AMU ("amevcntr111_el0",    CPENC (3,3,C13,C13,3),  0),
-  SR_AMU ("amevcntr112_el0",    CPENC (3,3,C13,C13,4),  0),
-  SR_AMU ("amevcntr113_el0",    CPENC (3,3,C13,C13,5),  0),
-  SR_AMU ("amevcntr114_el0",    CPENC (3,3,C13,C13,6),  0),
-  SR_AMU ("amevcntr115_el0",    CPENC (3,3,C13,C13,7),  0),
-  SR_AMU ("amevtyper10_el0",    CPENC (3,3,C13,C14,0),  0),
-  SR_AMU ("amevtyper11_el0",    CPENC (3,3,C13,C14,1),  0),
-  SR_AMU ("amevtyper12_el0",    CPENC (3,3,C13,C14,2),  0),
-  SR_AMU ("amevtyper13_el0",    CPENC (3,3,C13,C14,3),  0),
-  SR_AMU ("amevtyper14_el0",    CPENC (3,3,C13,C14,4),  0),
-  SR_AMU ("amevtyper15_el0",    CPENC (3,3,C13,C14,5),  0),
-  SR_AMU ("amevtyper16_el0",    CPENC (3,3,C13,C14,6),  0),
-  SR_AMU ("amevtyper17_el0",    CPENC (3,3,C13,C14,7),  0),
-  SR_AMU ("amevtyper18_el0",    CPENC (3,3,C13,C15,0),  0),
-  SR_AMU ("amevtyper19_el0",    CPENC (3,3,C13,C15,1),  0),
-  SR_AMU ("amevtyper110_el0",   CPENC (3,3,C13,C15,2),  0),
-  SR_AMU ("amevtyper111_el0",   CPENC (3,3,C13,C15,3),  0),
-  SR_AMU ("amevtyper112_el0",   CPENC (3,3,C13,C15,4),  0),
-  SR_AMU ("amevtyper113_el0",   CPENC (3,3,C13,C15,5),  0),
-  SR_AMU ("amevtyper114_el0",   CPENC (3,3,C13,C15,6),  0),
-  SR_AMU ("amevtyper115_el0",   CPENC (3,3,C13,C15,7),  0),
-
-  SR_GIC ("icc_pmr_el1",        CPENC (3,0,C4,C6,0),    0),
-  SR_GIC ("icc_iar0_el1",       CPENC (3,0,C12,C8,0),   F_REG_READ),
-  SR_GIC ("icc_eoir0_el1",      CPENC (3,0,C12,C8,1),   F_REG_WRITE),
-  SR_GIC ("icc_hppir0_el1",     CPENC (3,0,C12,C8,2),   F_REG_READ),
-  SR_GIC ("icc_bpr0_el1",       CPENC (3,0,C12,C8,3),   0),
-  SR_GIC ("icc_ap0r0_el1",      CPENC (3,0,C12,C8,4),   0),
-  SR_GIC ("icc_ap0r1_el1",      CPENC (3,0,C12,C8,5),   0),
-  SR_GIC ("icc_ap0r2_el1",      CPENC (3,0,C12,C8,6),   0),
-  SR_GIC ("icc_ap0r3_el1",      CPENC (3,0,C12,C8,7),   0),
-  SR_GIC ("icc_ap1r0_el1",      CPENC (3,0,C12,C9,0),   0),
-  SR_GIC ("icc_ap1r1_el1",      CPENC (3,0,C12,C9,1),   0),
-  SR_GIC ("icc_ap1r2_el1",      CPENC (3,0,C12,C9,2),   0),
-  SR_GIC ("icc_ap1r3_el1",      CPENC (3,0,C12,C9,3),   0),
-  SR_GIC ("icc_dir_el1",        CPENC (3,0,C12,C11,1),  F_REG_WRITE),
-  SR_GIC ("icc_rpr_el1",        CPENC (3,0,C12,C11,3),  F_REG_READ),
-  SR_GIC ("icc_sgi1r_el1",      CPENC (3,0,C12,C11,5),  F_REG_WRITE),
-  SR_GIC ("icc_asgi1r_el1",     CPENC (3,0,C12,C11,6),  F_REG_WRITE),
-  SR_GIC ("icc_sgi0r_el1",      CPENC (3,0,C12,C11,7),  F_REG_WRITE),
-  SR_GIC ("icc_iar1_el1",       CPENC (3,0,C12,C12,0),  F_REG_READ),
-  SR_GIC ("icc_eoir1_el1",      CPENC (3,0,C12,C12,1),  F_REG_WRITE),
-  SR_GIC ("icc_hppir1_el1",     CPENC (3,0,C12,C12,2),  F_REG_READ),
-  SR_GIC ("icc_bpr1_el1",       CPENC (3,0,C12,C12,3),  0),
-  SR_GIC ("icc_ctlr_el1",       CPENC (3,0,C12,C12,4),  0),
-  SR_GIC ("icc_igrpen0_el1",    CPENC (3,0,C12,C12,6),  0),
-  SR_GIC ("icc_igrpen1_el1",    CPENC (3,0,C12,C12,7),  0),
-  SR_GIC ("ich_ap0r0_el2",      CPENC (3,4,C12,C8,0),   0),
-  SR_GIC ("ich_ap0r1_el2",      CPENC (3,4,C12,C8,1),   0),
-  SR_GIC ("ich_ap0r2_el2",      CPENC (3,4,C12,C8,2),   0),
-  SR_GIC ("ich_ap0r3_el2",      CPENC (3,4,C12,C8,3),   0),
-  SR_GIC ("ich_ap1r0_el2",      CPENC (3,4,C12,C9,0),   0),
-  SR_GIC ("ich_ap1r1_el2",      CPENC (3,4,C12,C9,1),   0),
-  SR_GIC ("ich_ap1r2_el2",      CPENC (3,4,C12,C9,2),   0),
-  SR_GIC ("ich_ap1r3_el2",      CPENC (3,4,C12,C9,3),   0),
-  SR_GIC ("ich_hcr_el2",        CPENC (3,4,C12,C11,0),  0),
-  SR_GIC ("ich_misr_el2",       CPENC (3,4,C12,C11,2),  F_REG_READ),
-  SR_GIC ("ich_eisr_el2",       CPENC (3,4,C12,C11,3),  F_REG_READ),
-  SR_GIC ("ich_elrsr_el2",      CPENC (3,4,C12,C11,5),  F_REG_READ),
-  SR_GIC ("ich_vmcr_el2",       CPENC (3,4,C12,C11,7),  0),
-  SR_GIC ("ich_lr0_el2",        CPENC (3,4,C12,C12,0),  0),
-  SR_GIC ("ich_lr1_el2",        CPENC (3,4,C12,C12,1),  0),
-  SR_GIC ("ich_lr2_el2",        CPENC (3,4,C12,C12,2),  0),
-  SR_GIC ("ich_lr3_el2",        CPENC (3,4,C12,C12,3),  0),
-  SR_GIC ("ich_lr4_el2",        CPENC (3,4,C12,C12,4),  0),
-  SR_GIC ("ich_lr5_el2",        CPENC (3,4,C12,C12,5),  0),
-  SR_GIC ("ich_lr6_el2",        CPENC (3,4,C12,C12,6),  0),
-  SR_GIC ("ich_lr7_el2",        CPENC (3,4,C12,C12,7),  0),
-  SR_GIC ("ich_lr8_el2",        CPENC (3,4,C12,C13,0),  0),
-  SR_GIC ("ich_lr9_el2",        CPENC (3,4,C12,C13,1),  0),
-  SR_GIC ("ich_lr10_el2",       CPENC (3,4,C12,C13,2),  0),
-  SR_GIC ("ich_lr11_el2",       CPENC (3,4,C12,C13,3),  0),
-  SR_GIC ("ich_lr12_el2",       CPENC (3,4,C12,C13,4),  0),
-  SR_GIC ("ich_lr13_el2",       CPENC (3,4,C12,C13,5),  0),
-  SR_GIC ("ich_lr14_el2",       CPENC (3,4,C12,C13,6),  0),
-  SR_GIC ("ich_lr15_el2",       CPENC (3,4,C12,C13,7),  0),
-  SR_GIC ("icc_igrpen1_el3",    CPENC (3,6,C12,C12,7),  0),
-
-  SR_V8_6A ("amcg1idr_el0",      CPENC (3,3,C13,C2,6),   F_REG_READ),
-  SR_V8_6A ("cntpctss_el0",      CPENC (3,3,C14,C0,5),   F_REG_READ),
-  SR_V8_6A ("cntvctss_el0",      CPENC (3,3,C14,C0,6),   F_REG_READ),
-  SR_V8_6A ("hfgrtr_el2",        CPENC (3,4,C1,C1,4),    0),
-  SR_V8_6A ("hfgwtr_el2",        CPENC (3,4,C1,C1,5),    0),
-  SR_V8_6A ("hfgitr_el2",        CPENC (3,4,C1,C1,6),    0),
-  SR_V8_6A ("hdfgrtr_el2",       CPENC (3,4,C3,C1,4),    0),
-  SR_V8_6A ("hdfgwtr_el2",       CPENC (3,4,C3,C1,5),    0),
-  SR_V8_6A ("hafgrtr_el2",       CPENC (3,4,C3,C1,6),    0),
-  SR_V8_6A ("amevcntvoff00_el2", CPENC (3,4,C13,C8,0),   0),
-  SR_V8_6A ("amevcntvoff01_el2", CPENC (3,4,C13,C8,1),   0),
-  SR_V8_6A ("amevcntvoff02_el2", CPENC (3,4,C13,C8,2),   0),
-  SR_V8_6A ("amevcntvoff03_el2", CPENC (3,4,C13,C8,3),   0),
-  SR_V8_6A ("amevcntvoff04_el2", CPENC (3,4,C13,C8,4),   0),
-  SR_V8_6A ("amevcntvoff05_el2", CPENC (3,4,C13,C8,5),   0),
-  SR_V8_6A ("amevcntvoff06_el2", CPENC (3,4,C13,C8,6),   0),
-  SR_V8_6A ("amevcntvoff07_el2", CPENC (3,4,C13,C8,7),   0),
-  SR_V8_6A ("amevcntvoff08_el2", CPENC (3,4,C13,C9,0),   0),
-  SR_V8_6A ("amevcntvoff09_el2", CPENC (3,4,C13,C9,1),   0),
-  SR_V8_6A ("amevcntvoff010_el2", CPENC (3,4,C13,C9,2),  0),
-  SR_V8_6A ("amevcntvoff011_el2", CPENC (3,4,C13,C9,3),  0),
-  SR_V8_6A ("amevcntvoff012_el2", CPENC (3,4,C13,C9,4),  0),
-  SR_V8_6A ("amevcntvoff013_el2", CPENC (3,4,C13,C9,5),  0),
-  SR_V8_6A ("amevcntvoff014_el2", CPENC (3,4,C13,C9,6),  0),
-  SR_V8_6A ("amevcntvoff015_el2", CPENC (3,4,C13,C9,7),  0),
-  SR_V8_6A ("amevcntvoff10_el2", CPENC (3,4,C13,C10,0),  0),
-  SR_V8_6A ("amevcntvoff11_el2", CPENC (3,4,C13,C10,1),  0),
-  SR_V8_6A ("amevcntvoff12_el2", CPENC (3,4,C13,C10,2),  0),
-  SR_V8_6A ("amevcntvoff13_el2", CPENC (3,4,C13,C10,3),  0),
-  SR_V8_6A ("amevcntvoff14_el2", CPENC (3,4,C13,C10,4),  0),
-  SR_V8_6A ("amevcntvoff15_el2", CPENC (3,4,C13,C10,5),  0),
-  SR_V8_6A ("amevcntvoff16_el2", CPENC (3,4,C13,C10,6),  0),
-  SR_V8_6A ("amevcntvoff17_el2", CPENC (3,4,C13,C10,7),  0),
-  SR_V8_6A ("amevcntvoff18_el2", CPENC (3,4,C13,C11,0),  0),
-  SR_V8_6A ("amevcntvoff19_el2", CPENC (3,4,C13,C11,1),  0),
-  SR_V8_6A ("amevcntvoff110_el2", CPENC (3,4,C13,C11,2), 0),
-  SR_V8_6A ("amevcntvoff111_el2", CPENC (3,4,C13,C11,3), 0),
-  SR_V8_6A ("amevcntvoff112_el2", CPENC (3,4,C13,C11,4), 0),
-  SR_V8_6A ("amevcntvoff113_el2", CPENC (3,4,C13,C11,5), 0),
-  SR_V8_6A ("amevcntvoff114_el2", CPENC (3,4,C13,C11,6), 0),
-  SR_V8_6A ("amevcntvoff115_el2", CPENC (3,4,C13,C11,7), 0),
-  SR_V8_6A ("cntpoff_el2",       CPENC (3,4,C14,C0,6),   0),
-
-  SR_V8_7A ("pmsnevfr_el1",      CPENC (3,0,C9,C9,1),    0),
-  SR_V8_7A ("hcrx_el2",          CPENC (3,4,C1,C2,2),    0),
-
-  SR_V8_8A ("allint",            CPENC (3,0,C4,C3,0),    0),
-  SR_V8_8A ("icc_nmiar1_el1",    CPENC (3,0,C12,C9,5),   F_REG_READ),
-
+#define SYSREG(name, encoding, flags, features) \
+  { name, encoding, flags, features },
+#include "aarch64-system-regs.def"
   { 0, CPENC (0,0,0,0,0), 0, 0 }
+#undef SYSREG
 };
 
 bool
@@ -5754,22 +4703,22 @@  aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
    0b011010 (0x1a).  */
 const aarch64_sys_reg aarch64_pstatefields [] =
 {
-  SR_CORE ("spsel",	  0x05,	F_REG_MAX_VALUE (1)),
-  SR_CORE ("daifset",	  0x1e,	F_REG_MAX_VALUE (15)),
-  SR_CORE ("daifclr",	  0x1f,	F_REG_MAX_VALUE (15)),
-  SR_PAN  ("pan",	  0x04, F_REG_MAX_VALUE (1)),
-  SR_V8_2A ("uao",	  0x03, F_REG_MAX_VALUE (1)),
-  SR_SSBS ("ssbs",	  0x19, F_REG_MAX_VALUE (1)),
-  SR_V8_4A ("dit",	  0x1a,	F_REG_MAX_VALUE (1)),
-  SR_MEMTAG ("tco",	  0x1c,	F_REG_MAX_VALUE (1)),
-  SR_SME  ("svcrsm",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x2,0x1)
-				| F_REG_MAX_VALUE (1)),
-  SR_SME  ("svcrza",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x4,0x1)
-				| F_REG_MAX_VALUE (1)),
-  SR_SME  ("svcrsmza",	  0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1)
-				| F_REG_MAX_VALUE (1)),
-  SR_V8_8A ("allint",	  0x08,	F_REG_MAX_VALUE (1)),
-  { 0,	  CPENC (0,0,0,0,0), 0, 0 },
+  { "spsel",	 0x05, F_REG_MAX_VALUE (1), AARCH64_FEATURE_CORE },
+  { "daifset",	 0x1e, F_REG_MAX_VALUE (15), AARCH64_FEATURE_CORE },
+  { "daifclr",	 0x1f, F_REG_MAX_VALUE (15), AARCH64_FEATURE_CORE },
+  { "pan",	 0x04, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_PAN },
+  { "uao",	 0x03, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_V8_2A },
+  { "ssbs",	 0x19, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_SSBS },
+  { "dit",	 0x1a, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_V8_4A },
+  { "tco",	 0x1c, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_MEMTAG },
+  { "svcrsm",	 0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x2,0x1) | F_REG_MAX_VALUE (1)
+		       | F_ARCHEXT, AARCH64_FEATURE_SME },
+  { "svcrza",	 0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x4,0x1) | F_REG_MAX_VALUE (1)
+		       | F_ARCHEXT, AARCH64_FEATURE_SME },
+  { "svcrsmza",	 0x1b, PSTATE_ENCODE_CRM_AND_IMM (0x6,0x1) | F_REG_MAX_VALUE (1)
+		       | F_ARCHEXT, AARCH64_FEATURE_SME },
+  { "allint",	 0x08, F_REG_MAX_VALUE (1) | F_ARCHEXT, AARCH64_FEATURE_V8_8A },
+  { 0,	  CPENC (0,0,0,0,0), 0, 0 }
 };
 
 bool
diff --git a/opcodes/aarch64-system-regs.def b/opcodes/aarch64-system-regs.def
new file mode 100644
index 00000000000..bf8c488472a
--- /dev/null
+++ b/opcodes/aarch64-system-regs.def
@@ -0,0 +1,1059 @@ 
+/* aarch64-system-regs.def -- AArch64 opcode support.
+   Copyright (C) 2009-2023 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3.  If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+/* Array of system registers and their associated arch features.
+
+   Before using #include to read this file, define a macro:
+
+     SYSREG (name, encoding, flags, features)
+
+  The NAME is the system register name, as recognized by the
+  assembler.  CPENC provides the necessay information for the binary
+  encoding of the system register.  The FLAGS field is a bitmask of
+  operations supported by the particular register.  The ARCH is one of
+  the ISA flags recognized by the compiler and specifies the
+  architectural requirements of the system register.  */
+
+  SYSREG ("accdata_el1",	CPENC (3,0,13,0,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("actlr_el1",		CPENC (3,0,1,0,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("actlr_el2",		CPENC (3,4,1,0,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("actlr_el3",		CPENC (3,6,1,0,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("afsr0_el1",		CPENC (3,0,5,1,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("afsr0_el12",		CPENC (3,5,5,1,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("afsr0_el2",		CPENC (3,4,5,1,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("afsr0_el3",		CPENC (3,6,5,1,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("afsr1_el1",		CPENC (3,0,5,1,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("afsr1_el12",		CPENC (3,5,5,1,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("afsr1_el2",		CPENC (3,4,5,1,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("afsr1_el3",		CPENC (3,6,5,1,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("aidr_el1",		CPENC (3,1,0,0,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("allint",		CPENC (3,0,4,3,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_8A)
+  SYSREG ("amair_el1",		CPENC (3,0,10,3,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("amair_el12",		CPENC (3,5,10,3,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("amair_el2",		CPENC (3,4,10,3,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("amair_el3",		CPENC (3,6,10,3,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("amcfgr_el0",		CPENC (3,3,13,2,1),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("amcg1idr_el0",	CPENC (3,3,13,2,6),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_6A)
+  SYSREG ("amcgcr_el0",		CPENC (3,3,13,2,2),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("amcntenclr0_el0",	CPENC (3,3,13,2,4),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amcntenclr1_el0",	CPENC (3,3,13,3,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amcntenset0_el0",	CPENC (3,3,13,2,5),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amcntenset1_el0",	CPENC (3,3,13,3,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amcr_el0",		CPENC (3,3,13,2,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr00_el0",	CPENC (3,3,13,4,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr01_el0",	CPENC (3,3,13,4,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr02_el0",	CPENC (3,3,13,4,2),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr03_el0",	CPENC (3,3,13,4,3),     F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr10_el0",	CPENC (3,3,13,12,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr110_el0",	CPENC (3,3,13,13,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr111_el0",	CPENC (3,3,13,13,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr112_el0",	CPENC (3,3,13,13,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr113_el0",	CPENC (3,3,13,13,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr114_el0",	CPENC (3,3,13,13,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr115_el0",	CPENC (3,3,13,13,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr11_el0",	CPENC (3,3,13,12,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr12_el0",	CPENC (3,3,13,12,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr13_el0",	CPENC (3,3,13,12,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr14_el0",	CPENC (3,3,13,12,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr15_el0",	CPENC (3,3,13,12,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr16_el0",	CPENC (3,3,13,12,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr17_el0",	CPENC (3,3,13,12,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr18_el0",	CPENC (3,3,13,13,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntr19_el0",	CPENC (3,3,13,13,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevcntvoff00_el2",	CPENC (3,4,13,8,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff010_el2",	CPENC (3,4,13,9,2),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff011_el2",	CPENC (3,4,13,9,3),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff012_el2",	CPENC (3,4,13,9,4),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff013_el2",	CPENC (3,4,13,9,5),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff014_el2",	CPENC (3,4,13,9,6),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff015_el2",	CPENC (3,4,13,9,7),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff01_el2",	CPENC (3,4,13,8,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff02_el2",	CPENC (3,4,13,8,2),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff03_el2",	CPENC (3,4,13,8,3),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff04_el2",	CPENC (3,4,13,8,4),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff05_el2",	CPENC (3,4,13,8,5),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff06_el2",	CPENC (3,4,13,8,6),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff07_el2",	CPENC (3,4,13,8,7),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff08_el2",	CPENC (3,4,13,9,0),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff09_el2",	CPENC (3,4,13,9,1),     F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff10_el2",	CPENC (3,4,13,10,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff110_el2",	CPENC (3,4,13,11,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff111_el2",	CPENC (3,4,13,11,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff112_el2",	CPENC (3,4,13,11,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff113_el2",	CPENC (3,4,13,11,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff114_el2",	CPENC (3,4,13,11,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff115_el2",	CPENC (3,4,13,11,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff11_el2",	CPENC (3,4,13,10,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff12_el2",	CPENC (3,4,13,10,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff13_el2",	CPENC (3,4,13,10,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff14_el2",	CPENC (3,4,13,10,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff15_el2",	CPENC (3,4,13,10,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff16_el2",	CPENC (3,4,13,10,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff17_el2",	CPENC (3,4,13,10,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff18_el2",	CPENC (3,4,13,11,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevcntvoff19_el2",	CPENC (3,4,13,11,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("amevtyper00_el0",	CPENC (3,3,13,6,0),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper01_el0",	CPENC (3,3,13,6,1),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper02_el0",	CPENC (3,3,13,6,2),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper03_el0",	CPENC (3,3,13,6,3),     F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper10_el0",	CPENC (3,3,13,14,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper110_el0",	CPENC (3,3,13,15,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper111_el0",	CPENC (3,3,13,15,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper112_el0",	CPENC (3,3,13,15,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper113_el0",	CPENC (3,3,13,15,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper114_el0",	CPENC (3,3,13,15,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper115_el0",	CPENC (3,3,13,15,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper11_el0",	CPENC (3,3,13,14,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper12_el0",	CPENC (3,3,13,14,2),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper13_el0",	CPENC (3,3,13,14,3),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper14_el0",	CPENC (3,3,13,14,4),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper15_el0",	CPENC (3,3,13,14,5),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper16_el0",	CPENC (3,3,13,14,6),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper17_el0",	CPENC (3,3,13,14,7),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper18_el0",	CPENC (3,3,13,15,0),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amevtyper19_el0",	CPENC (3,3,13,15,1),    F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("amuserenr_el0",	CPENC (3,3,13,2,3),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("apdakeyhi_el1",	CPENC (3,0,2,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apdakeylo_el1",	CPENC (3,0,2,2,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apdbkeyhi_el1",	CPENC (3,0,2,2,3),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apdbkeylo_el1",	CPENC (3,0,2,2,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apgakeyhi_el1",	CPENC (3,0,2,3,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apgakeylo_el1",	CPENC (3,0,2,3,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apiakeyhi_el1",	CPENC (3,0,2,1,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apiakeylo_el1",	CPENC (3,0,2,1,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apibkeyhi_el1",	CPENC (3,0,2,1,3),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("apibkeylo_el1",	CPENC (3,0,2,1,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_3A)
+  SYSREG ("brbcr_el1",		CPENC (2,1,9,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbcr_el12",		CPENC (2,5,9,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbcr_el2",		CPENC (2,4,9,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbfcr_el1",		CPENC (2,1,9,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbidr0_el1",	CPENC (2,1,9,2,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf0_el1",	CPENC (2,1,8,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf10_el1",	CPENC (2,1,8,10,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf11_el1",	CPENC (2,1,8,11,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf12_el1",	CPENC (2,1,8,12,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf13_el1",	CPENC (2,1,8,13,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf14_el1",	CPENC (2,1,8,14,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf15_el1",	CPENC (2,1,8,15,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf16_el1",	CPENC (2,1,8,0,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf17_el1",	CPENC (2,1,8,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf18_el1",	CPENC (2,1,8,2,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf19_el1",	CPENC (2,1,8,3,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf1_el1",	CPENC (2,1,8,1,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf20_el1",	CPENC (2,1,8,4,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf21_el1",	CPENC (2,1,8,5,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf22_el1",	CPENC (2,1,8,6,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf23_el1",	CPENC (2,1,8,7,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf24_el1",	CPENC (2,1,8,8,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf25_el1",	CPENC (2,1,8,9,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf26_el1",	CPENC (2,1,8,10,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf27_el1",	CPENC (2,1,8,11,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf28_el1",	CPENC (2,1,8,12,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf29_el1",	CPENC (2,1,8,13,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf2_el1",	CPENC (2,1,8,2,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf30_el1",	CPENC (2,1,8,14,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf31_el1",	CPENC (2,1,8,15,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf3_el1",	CPENC (2,1,8,3,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf4_el1",	CPENC (2,1,8,4,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf5_el1",	CPENC (2,1,8,5,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf6_el1",	CPENC (2,1,8,6,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf7_el1",	CPENC (2,1,8,7,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf8_el1",	CPENC (2,1,8,8,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinf9_el1",	CPENC (2,1,8,9,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbinfinj_el1",	CPENC (2,1,9,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc0_el1",	CPENC (2,1,8,0,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc10_el1",	CPENC (2,1,8,10,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc11_el1",	CPENC (2,1,8,11,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc12_el1",	CPENC (2,1,8,12,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc13_el1",	CPENC (2,1,8,13,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc14_el1",	CPENC (2,1,8,14,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc15_el1",	CPENC (2,1,8,15,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc16_el1",	CPENC (2,1,8,0,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc17_el1",	CPENC (2,1,8,1,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc18_el1",	CPENC (2,1,8,2,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc19_el1",	CPENC (2,1,8,3,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc1_el1",	CPENC (2,1,8,1,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc20_el1",	CPENC (2,1,8,4,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc21_el1",	CPENC (2,1,8,5,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc22_el1",	CPENC (2,1,8,6,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc23_el1",	CPENC (2,1,8,7,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc24_el1",	CPENC (2,1,8,8,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc25_el1",	CPENC (2,1,8,9,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc26_el1",	CPENC (2,1,8,10,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc27_el1",	CPENC (2,1,8,11,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc28_el1",	CPENC (2,1,8,12,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc29_el1",	CPENC (2,1,8,13,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc2_el1",	CPENC (2,1,8,2,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc30_el1",	CPENC (2,1,8,14,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc31_el1",	CPENC (2,1,8,15,5),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc3_el1",	CPENC (2,1,8,3,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc4_el1",	CPENC (2,1,8,4,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc5_el1",	CPENC (2,1,8,5,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc6_el1",	CPENC (2,1,8,6,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc7_el1",	CPENC (2,1,8,7,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc8_el1",	CPENC (2,1,8,8,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrc9_el1",	CPENC (2,1,8,9,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbsrcinj_el1",	CPENC (2,1,9,1,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt0_el1",	CPENC (2,1,8,0,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt10_el1",	CPENC (2,1,8,10,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt11_el1",	CPENC (2,1,8,11,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt12_el1",	CPENC (2,1,8,12,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt13_el1",	CPENC (2,1,8,13,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt14_el1",	CPENC (2,1,8,14,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt15_el1",	CPENC (2,1,8,15,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt16_el1",	CPENC (2,1,8,0,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt17_el1",	CPENC (2,1,8,1,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt18_el1",	CPENC (2,1,8,2,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt19_el1",	CPENC (2,1,8,3,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt1_el1",	CPENC (2,1,8,1,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt20_el1",	CPENC (2,1,8,4,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt21_el1",	CPENC (2,1,8,5,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt22_el1",	CPENC (2,1,8,6,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt23_el1",	CPENC (2,1,8,7,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt24_el1",	CPENC (2,1,8,8,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt25_el1",	CPENC (2,1,8,9,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt26_el1",	CPENC (2,1,8,10,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt27_el1",	CPENC (2,1,8,11,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt28_el1",	CPENC (2,1,8,12,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt29_el1",	CPENC (2,1,8,13,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt2_el1",	CPENC (2,1,8,2,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt30_el1",	CPENC (2,1,8,14,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt31_el1",	CPENC (2,1,8,15,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt3_el1",	CPENC (2,1,8,3,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt4_el1",	CPENC (2,1,8,4,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt5_el1",	CPENC (2,1,8,5,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt6_el1",	CPENC (2,1,8,6,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt7_el1",	CPENC (2,1,8,7,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt8_el1",	CPENC (2,1,8,8,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgt9_el1",	CPENC (2,1,8,9,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("brbtgtinj_el1",	CPENC (2,1,9,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("brbts_el1",		CPENC (2,1,9,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ccsidr2_el1",	CPENC (3,1,0,0,2),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_3A)
+  SYSREG ("ccsidr_el1",		CPENC (3,1,0,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("clidr_el1",		CPENC (3,1,0,0,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("cntfrq_el0",		CPENC (3,3,14,0,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cnthctl_el2",	CPENC (3,4,14,1,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cnthp_ctl_el2",	CPENC (3,4,14,2,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cnthp_cval_el2",	CPENC (3,4,14,2,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cnthp_tval_el2",	CPENC (3,4,14,2,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cnthps_ctl_el2",	CPENC (3,4,14,5,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("cnthps_cval_el2",	CPENC (3,4,14,5,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("cnthps_tval_el2",	CPENC (3,4,14,5,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("cnthv_ctl_el2",	CPENC (3,4,14,3,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cnthv_cval_el2",	CPENC (3,4,14,3,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cnthv_tval_el2",	CPENC (3,4,14,3,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cnthvs_ctl_el2",	CPENC (3,4,14,4,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("cnthvs_cval_el2",	CPENC (3,4,14,4,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("cnthvs_tval_el2",	CPENC (3,4,14,4,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("cntkctl_el1",	CPENC (3,0,14,1,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntkctl_el12",	CPENC (3,5,14,1,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntp_ctl_el0",	CPENC (3,3,14,2,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntp_ctl_el02",	CPENC (3,5,14,2,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntp_cval_el0",	CPENC (3,3,14,2,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntp_cval_el02",	CPENC (3,5,14,2,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntp_tval_el0",	CPENC (3,3,14,2,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntp_tval_el02",	CPENC (3,5,14,2,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntpct_el0",		CPENC (3,3,14,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("cntpctss_el0",	CPENC (3,3,14,0,5),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_6A)
+  SYSREG ("cntpoff_el2",	CPENC (3,4,14,0,6),      F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("cntps_ctl_el1",	CPENC (3,7,14,2,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntps_cval_el1",	CPENC (3,7,14,2,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntps_tval_el1",	CPENC (3,7,14,2,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntv_ctl_el0",	CPENC (3,3,14,3,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntv_ctl_el02",	CPENC (3,5,14,3,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntv_cval_el0",	CPENC (3,3,14,3,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntv_cval_el02",	CPENC (3,5,14,3,2),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntv_tval_el0",	CPENC (3,3,14,3,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cntv_tval_el02",	CPENC (3,5,14,3,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cntvct_el0",		CPENC (3,3,14,0,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("cntvctss_el0",	CPENC (3,3,14,0,6),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_6A)
+  SYSREG ("cntvoff_el2",	CPENC (3,4,14,0,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("contextidr_el1",	CPENC (3,0,13,0,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("contextidr_el12",	CPENC (3,5,13,0,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("contextidr_el2",	CPENC (3,4,13,0,1),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cpacr_el1",		CPENC (3,0,1,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cpacr_el12",		CPENC (3,5,1,0,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("cptr_el2",		CPENC (3,4,1,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("cptr_el3",		CPENC (3,6,1,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrcr_el0",		CPENC (2,3,8,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrcr_el1",		CPENC (2,0,8,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrcr_el12",		CPENC (2,5,8,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrcr_el2",		CPENC (2,4,8,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csridr_el0",		CPENC (2,3,8,0,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("csrptr_el0",		CPENC (2,3,8,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrptr_el1",		CPENC (2,0,8,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrptr_el12",	CPENC (2,5,8,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrptr_el2",		CPENC (2,4,8,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("csrptridx_el0",	CPENC (2,3,8,0,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("csrptridx_el1",	CPENC (2,0,8,0,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("csrptridx_el2",	CPENC (2,4,8,0,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("csselr_el1",		CPENC (3,2,0,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ctr_el0",		CPENC (3,3,0,0,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("currentel",		CPENC (3,0,4,2,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("dacr32_el2",		CPENC (3,4,3,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("daif",		CPENC (3,3,4,2,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgauthstatus_el1",	CPENC (2,0,7,14,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr0_el1",	CPENC (2,0,0,0,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr10_el1",	CPENC (2,0,0,10,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr11_el1",	CPENC (2,0,0,11,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr12_el1",	CPENC (2,0,0,12,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr13_el1",	CPENC (2,0,0,13,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr14_el1",	CPENC (2,0,0,14,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr15_el1",	CPENC (2,0,0,15,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr1_el1",	CPENC (2,0,0,1,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr2_el1",	CPENC (2,0,0,2,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr3_el1",	CPENC (2,0,0,3,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr4_el1",	CPENC (2,0,0,4,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr5_el1",	CPENC (2,0,0,5,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr6_el1",	CPENC (2,0,0,6,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr7_el1",	CPENC (2,0,0,7,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr8_el1",	CPENC (2,0,0,8,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbcr9_el1",	CPENC (2,0,0,9,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr0_el1",	CPENC (2,0,0,0,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr10_el1",	CPENC (2,0,0,10,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr11_el1",	CPENC (2,0,0,11,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr12_el1",	CPENC (2,0,0,12,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr13_el1",	CPENC (2,0,0,13,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr14_el1",	CPENC (2,0,0,14,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr15_el1",	CPENC (2,0,0,15,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr1_el1",	CPENC (2,0,0,1,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr2_el1",	CPENC (2,0,0,2,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr3_el1",	CPENC (2,0,0,3,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr4_el1",	CPENC (2,0,0,4,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr5_el1",	CPENC (2,0,0,5,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr6_el1",	CPENC (2,0,0,6,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr7_el1",	CPENC (2,0,0,7,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr8_el1",	CPENC (2,0,0,8,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgbvr9_el1",	CPENC (2,0,0,9,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgclaimclr_el1",	CPENC (2,0,7,9,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgclaimset_el1",	CPENC (2,0,7,8,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgdtr_el0",		CPENC (2,3,0,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgdtrrx_el0",	CPENC (2,3,0,5,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("dbgdtrtx_el0",	CPENC (2,3,0,5,0),       F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("dbgprcr_el1",	CPENC (2,0,1,4,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgvcr32_el2",	CPENC (2,4,0,7,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr0_el1",	CPENC (2,0,0,0,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr10_el1",	CPENC (2,0,0,10,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr11_el1",	CPENC (2,0,0,11,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr12_el1",	CPENC (2,0,0,12,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr13_el1",	CPENC (2,0,0,13,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr14_el1",	CPENC (2,0,0,14,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr15_el1",	CPENC (2,0,0,15,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr1_el1",	CPENC (2,0,0,1,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr2_el1",	CPENC (2,0,0,2,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr3_el1",	CPENC (2,0,0,3,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr4_el1",	CPENC (2,0,0,4,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr5_el1",	CPENC (2,0,0,5,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr6_el1",	CPENC (2,0,0,6,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr7_el1",	CPENC (2,0,0,7,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr8_el1",	CPENC (2,0,0,8,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwcr9_el1",	CPENC (2,0,0,9,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr0_el1",	CPENC (2,0,0,0,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr10_el1",	CPENC (2,0,0,10,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr11_el1",	CPENC (2,0,0,11,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr12_el1",	CPENC (2,0,0,12,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr13_el1",	CPENC (2,0,0,13,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr14_el1",	CPENC (2,0,0,14,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr15_el1",	CPENC (2,0,0,15,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr1_el1",	CPENC (2,0,0,1,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr2_el1",	CPENC (2,0,0,2,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr3_el1",	CPENC (2,0,0,3,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr4_el1",	CPENC (2,0,0,4,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr5_el1",	CPENC (2,0,0,5,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr6_el1",	CPENC (2,0,0,6,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr7_el1",	CPENC (2,0,0,7,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr8_el1",	CPENC (2,0,0,8,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dbgwvr9_el1",	CPENC (2,0,0,9,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dczid_el0",		CPENC (3,3,0,0,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("disr_el1",		CPENC (3,0,12,1,1),      F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("dit",		CPENC (3,3,4,2,5),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("dlr_el0",		CPENC (3,3,4,5,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("dspsr_el0",		CPENC (3,3,4,5,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("elr_el1",		CPENC (3,0,4,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("elr_el12",		CPENC (3,5,4,0,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("elr_el2",		CPENC (3,4,4,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("elr_el3",		CPENC (3,6,4,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("erridr_el1",		CPENC (3,0,5,3,0),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RAS)
+  SYSREG ("errselr_el1",	CPENC (3,0,5,3,1),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxaddr_el1",	CPENC (3,0,5,4,3),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxctlr_el1",	CPENC (3,0,5,4,1),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxfr_el1",		CPENC (3,0,5,4,0),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RAS)
+  SYSREG ("erxmisc0_el1",	CPENC (3,0,5,5,0),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxmisc1_el1",	CPENC (3,0,5,5,1),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxmisc2_el1",	CPENC (3,0,5,5,2),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxmisc3_el1",	CPENC (3,0,5,5,3),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxpfgcdn_el1",	CPENC (3,0,5,4,6),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxpfgctl_el1",	CPENC (3,0,5,4,5),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("erxpfgf_el1",	CPENC (3,0,5,4,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RAS)
+  SYSREG ("erxstatus_el1",	CPENC (3,0,5,4,2),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("esr_el1",		CPENC (3,0,5,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("esr_el12",		CPENC (3,5,5,2,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("esr_el2",		CPENC (3,4,5,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("esr_el3",		CPENC (3,6,5,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("far_el1",		CPENC (3,0,6,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("far_el12",		CPENC (3,5,6,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("far_el2",		CPENC (3,4,6,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("far_el3",		CPENC (3,6,6,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("fpcr",		CPENC (3,3,4,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("fpexc32_el2",	CPENC (3,4,5,3,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("fpsr",		CPENC (3,3,4,4,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("gcr_el1",		CPENC (3,0,1,0,6),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("gmid_el1",		CPENC (3,1,0,0,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_MEMTAG)
+  SYSREG ("gpccr_el3",		CPENC (3,6,2,1,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("gptbr_el3",		CPENC (3,6,2,1,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("hacr_el2",		CPENC (3,4,1,1,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("hafgrtr_el2",	CPENC (3,4,3,1,6),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("hcr_el2",		CPENC (3,4,1,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("hcrx_el2",		CPENC (3,4,1,2,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_7A)
+  SYSREG ("hdfgrtr_el2",	CPENC (3,4,3,1,4),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("hdfgwtr_el2",	CPENC (3,4,3,1,5),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("hfgitr_el2",		CPENC (3,4,1,1,6),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("hfgrtr_el2",		CPENC (3,4,1,1,4),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("hfgwtr_el2",		CPENC (3,4,1,1,5),       F_ARCHEXT,		AARCH64_FEATURE_V8_6A)
+  SYSREG ("hpfar_el2",		CPENC (3,4,6,0,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("hstr_el2",		CPENC (3,4,1,1,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap0r0_el1",	CPENC (3,0,12,8,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap0r1_el1",	CPENC (3,0,12,8,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap0r2_el1",	CPENC (3,0,12,8,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap0r3_el1",	CPENC (3,0,12,8,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap1r0_el1",	CPENC (3,0,12,9,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap1r1_el1",	CPENC (3,0,12,9,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap1r2_el1",	CPENC (3,0,12,9,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ap1r3_el1",	CPENC (3,0,12,9,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_asgi1r_el1",	CPENC (3,0,12,11,6),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_bpr0_el1",	CPENC (3,0,12,8,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_bpr1_el1",	CPENC (3,0,12,12,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ctlr_el1",	CPENC (3,0,12,12,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_ctlr_el3",	CPENC (3,6,12,12,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_dir_el1",	CPENC (3,0,12,11,1),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_eoir0_el1",	CPENC (3,0,12,8,1),      F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_eoir1_el1",	CPENC (3,0,12,12,1),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_hppir0_el1",	CPENC (3,0,12,8,2),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_hppir1_el1",	CPENC (3,0,12,12,2),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_iar0_el1",	CPENC (3,0,12,8,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_iar1_el1",	CPENC (3,0,12,12,0),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_igrpen0_el1",	CPENC (3,0,12,12,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_igrpen1_el1",	CPENC (3,0,12,12,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_igrpen1_el3",	CPENC (3,6,12,12,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_nmiar1_el1",	CPENC (3,0,12,9,5),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_8A)
+  SYSREG ("icc_pmr_el1",	CPENC (3,0,4,6,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_rpr_el1",	CPENC (3,0,12,11,3),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_sgi0r_el1",	CPENC (3,0,12,11,7),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_sgi1r_el1",	CPENC (3,0,12,11,5),     F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("icc_sre_el1",	CPENC (3,0,12,12,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_sre_el2",	CPENC (3,4,12,9,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("icc_sre_el3",	CPENC (3,6,12,12,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap0r0_el2",	CPENC (3,4,12,8,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap0r1_el2",	CPENC (3,4,12,8,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap0r2_el2",	CPENC (3,4,12,8,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap0r3_el2",	CPENC (3,4,12,8,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap1r0_el2",	CPENC (3,4,12,9,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap1r1_el2",	CPENC (3,4,12,9,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap1r2_el2",	CPENC (3,4,12,9,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_ap1r3_el2",	CPENC (3,4,12,9,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_eisr_el2",	CPENC (3,4,12,11,3),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("ich_elrsr_el2",	CPENC (3,4,12,11,5),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("ich_hcr_el2",	CPENC (3,4,12,11,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr0_el2",	CPENC (3,4,12,12,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr10_el2",	CPENC (3,4,12,13,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr11_el2",	CPENC (3,4,12,13,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr12_el2",	CPENC (3,4,12,13,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr13_el2",	CPENC (3,4,12,13,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr14_el2",	CPENC (3,4,12,13,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr15_el2",	CPENC (3,4,12,13,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr1_el2",	CPENC (3,4,12,12,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr2_el2",	CPENC (3,4,12,12,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr3_el2",	CPENC (3,4,12,12,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr4_el2",	CPENC (3,4,12,12,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr5_el2",	CPENC (3,4,12,12,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr6_el2",	CPENC (3,4,12,12,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr7_el2",	CPENC (3,4,12,12,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr8_el2",	CPENC (3,4,12,13,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_lr9_el2",	CPENC (3,4,12,13,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_misr_el2",	CPENC (3,4,12,11,2),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("ich_vmcr_el2",	CPENC (3,4,12,11,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ich_vtr_el2",	CPENC (3,4,12,11,1),     F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64afr0_el1",	CPENC (3,0,0,5,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64afr1_el1",	CPENC (3,0,0,5,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64dfr0_el1",	CPENC (3,0,0,5,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64dfr1_el1",	CPENC (3,0,0,5,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64isar0_el1",	CPENC (3,0,0,6,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64isar1_el1",	CPENC (3,0,0,6,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64isar2_el1",	CPENC (3,0,0,6,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64mmfr0_el1",	CPENC (3,0,0,7,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64mmfr1_el1",	CPENC (3,0,0,7,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64mmfr2_el1",	CPENC (3,0,0,7,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64pfr0_el1",	CPENC (3,0,0,4,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64pfr1_el1",	CPENC (3,0,0,4,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_aa64smfr0_el1",	CPENC (3,0,0,4,5),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_SME)
+  SYSREG ("id_aa64zfr0_el1",	CPENC (3,0,0,4,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_SVE)
+  SYSREG ("id_afr0_el1",	CPENC (3,0,0,1,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_dfr0_el1",	CPENC (3,0,0,1,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_dfr1_el1",	CPENC (3,0,0,3,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar0_el1",	CPENC (3,0,0,2,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar1_el1",	CPENC (3,0,0,2,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar2_el1",	CPENC (3,0,0,2,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar3_el1",	CPENC (3,0,0,2,3),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar4_el1",	CPENC (3,0,0,2,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar5_el1",	CPENC (3,0,0,2,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_isar6_el1",	CPENC (3,0,0,2,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_mmfr0_el1",	CPENC (3,0,0,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_mmfr1_el1",	CPENC (3,0,0,1,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_mmfr2_el1",	CPENC (3,0,0,1,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_mmfr3_el1",	CPENC (3,0,0,1,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_mmfr4_el1",	CPENC (3,0,0,2,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_mmfr5_el1",	CPENC (3,0,0,3,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_pfr0_el1",	CPENC (3,0,0,1,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_pfr1_el1",	CPENC (3,0,0,1,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("id_pfr2_el1",	CPENC (3,0,0,3,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_ID_PFR2)
+  SYSREG ("ifsr32_el2",		CPENC (3,4,5,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("isr_el1",		CPENC (3,0,12,1,0),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("lorc_el1",		CPENC (3,0,10,4,3),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
+  SYSREG ("lorea_el1",		CPENC (3,0,10,4,1),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
+  SYSREG ("lorid_el1",		CPENC (3,0,10,4,7),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_LOR)
+  SYSREG ("lorn_el1",		CPENC (3,0,10,4,2),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
+  SYSREG ("lorsa_el1",		CPENC (3,0,10,4,0),      F_ARCHEXT,		AARCH64_FEATURE_LOR)
+  SYSREG ("mair_el1",		CPENC (3,0,10,2,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mair_el12",		CPENC (3,5,10,2,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("mair_el2",		CPENC (3,4,10,2,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mair_el3",		CPENC (3,6,10,2,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mdccint_el1",	CPENC (2,0,0,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mdccsr_el0",		CPENC (2,3,0,1,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mdcr_el2",		CPENC (3,4,1,1,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mdcr_el3",		CPENC (3,6,1,3,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mdrar_el1",		CPENC (2,0,1,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mdscr_el1",		CPENC (2,0,0,2,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mecid_a0_el2",	CPENC (3,4,10,8,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mecid_a1_el2",	CPENC (3,4,10,8,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mecid_p0_el2",	CPENC (3,4,10,8,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mecid_p1_el2",	CPENC (3,4,10,8,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mecid_rl_a_el3",	CPENC (3,6,10,10,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mecidr_el2",		CPENC (3,4,10,8,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mfar_el3",		CPENC (3,6,6,0,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("midr_el1",		CPENC (3,0,0,0,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mpam0_el1",		CPENC (3,0,10,5,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpam1_el1",		CPENC (3,0,10,5,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpam1_el12",		CPENC (3,5,10,5,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpam2_el2",		CPENC (3,4,10,5,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpam3_el3",		CPENC (3,6,10,5,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),      F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("mpamvpm0_el2",	CPENC (3,4,10,6,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm1_el2",	CPENC (3,4,10,6,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm2_el2",	CPENC (3,4,10,6,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm3_el2",	CPENC (3,4,10,6,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm4_el2",	CPENC (3,4,10,6,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm5_el2",	CPENC (3,4,10,6,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm6_el2",	CPENC (3,4,10,6,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpm7_el2",	CPENC (3,4,10,6,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpamvpmv_el2",	CPENC (3,4,10,4,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("mpidr_el1",		CPENC (3,0,0,0,5),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mpuir_el1",		CPENC (3,0,0,0,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8R)
+  SYSREG ("mpuir_el2",		CPENC (3,4,0,0,4),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8R)
+  SYSREG ("mvfr0_el1",		CPENC (3,0,0,3,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mvfr1_el1",		CPENC (3,0,0,3,1),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("mvfr2_el1",		CPENC (3,0,0,3,2),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("nzcv",		CPENC (3,3,4,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("osdlr_el1",		CPENC (2,0,1,3,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("osdtrrx_el1",	CPENC (2,0,0,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("osdtrtx_el1",	CPENC (2,0,0,3,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("oseccr_el1",		CPENC (2,0,0,6,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("oslar_el1",		CPENC (2,0,1,0,4),       F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("oslsr_el1",		CPENC (2,0,1,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("pan",		CPENC (3,0,4,2,3),       F_ARCHEXT,		AARCH64_FEATURE_PAN)
+  SYSREG ("par_el1",		CPENC (3,0,7,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmbidr_el1",		CPENC (3,0,9,10,7),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmblimitr_el1",	CPENC (3,0,9,10,0),      F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmbptr_el1",		CPENC (3,0,9,10,1),      F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmbsr_el1",		CPENC (3,0,9,10,3),      F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmccfiltr_el0",	CPENC (3,3,14,15,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmccntr_el0",	CPENC (3,3,9,13,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmceid0_el0",	CPENC (3,3,9,12,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("pmceid1_el0",	CPENC (3,3,9,12,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("pmcntenclr_el0",	CPENC (3,3,9,12,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmcntenset_el0",	CPENC (3,3,9,12,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmcr_el0",		CPENC (3,3,9,12,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr0_el0",	CPENC (3,3,14,8,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr10_el0",	CPENC (3,3,14,9,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr11_el0",	CPENC (3,3,14,9,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr12_el0",	CPENC (3,3,14,9,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr13_el0",	CPENC (3,3,14,9,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr14_el0",	CPENC (3,3,14,9,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr15_el0",	CPENC (3,3,14,9,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr16_el0",	CPENC (3,3,14,10,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr17_el0",	CPENC (3,3,14,10,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr18_el0",	CPENC (3,3,14,10,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr19_el0",	CPENC (3,3,14,10,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr1_el0",	CPENC (3,3,14,8,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr20_el0",	CPENC (3,3,14,10,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr21_el0",	CPENC (3,3,14,10,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr22_el0",	CPENC (3,3,14,10,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr23_el0",	CPENC (3,3,14,10,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr24_el0",	CPENC (3,3,14,11,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr25_el0",	CPENC (3,3,14,11,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr26_el0",	CPENC (3,3,14,11,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr27_el0",	CPENC (3,3,14,11,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr28_el0",	CPENC (3,3,14,11,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr29_el0",	CPENC (3,3,14,11,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr2_el0",	CPENC (3,3,14,8,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr30_el0",	CPENC (3,3,14,11,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr3_el0",	CPENC (3,3,14,8,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr4_el0",	CPENC (3,3,14,8,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr5_el0",	CPENC (3,3,14,8,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr6_el0",	CPENC (3,3,14,8,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr7_el0",	CPENC (3,3,14,8,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr8_el0",	CPENC (3,3,14,9,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevcntr9_el0",	CPENC (3,3,14,9,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper0_el0",	CPENC (3,3,14,12,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper10_el0",	CPENC (3,3,14,13,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper11_el0",	CPENC (3,3,14,13,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper12_el0",	CPENC (3,3,14,13,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper13_el0",	CPENC (3,3,14,13,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper14_el0",	CPENC (3,3,14,13,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper15_el0",	CPENC (3,3,14,13,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper16_el0",	CPENC (3,3,14,14,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper17_el0",	CPENC (3,3,14,14,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper18_el0",	CPENC (3,3,14,14,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper19_el0",	CPENC (3,3,14,14,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper1_el0",	CPENC (3,3,14,12,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper20_el0",	CPENC (3,3,14,14,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper21_el0",	CPENC (3,3,14,14,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper22_el0",	CPENC (3,3,14,14,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper23_el0",	CPENC (3,3,14,14,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper24_el0",	CPENC (3,3,14,15,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper25_el0",	CPENC (3,3,14,15,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper26_el0",	CPENC (3,3,14,15,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper27_el0",	CPENC (3,3,14,15,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper28_el0",	CPENC (3,3,14,15,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper29_el0",	CPENC (3,3,14,15,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper2_el0",	CPENC (3,3,14,12,2),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper30_el0",	CPENC (3,3,14,15,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper3_el0",	CPENC (3,3,14,12,3),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper4_el0",	CPENC (3,3,14,12,4),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper5_el0",	CPENC (3,3,14,12,5),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper6_el0",	CPENC (3,3,14,12,6),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper7_el0",	CPENC (3,3,14,12,7),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper8_el0",	CPENC (3,3,14,13,0),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmevtyper9_el0",	CPENC (3,3,14,13,1),     0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmintenclr_el1",	CPENC (3,0,9,14,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmintenset_el1",	CPENC (3,0,9,14,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmmir_el1",		CPENC (3,0,9,14,6),      F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_V8_4A)
+  SYSREG ("pmovsclr_el0",	CPENC (3,3,9,12,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmovsset_el0",	CPENC (3,3,9,14,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmscr_el12",		CPENC (3,5,9,9,0),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmscr_el2",		CPENC (3,4,9,9,0),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmscr_el1",		CPENC (3,0,9,9,0),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmselr_el0",		CPENC (3,3,9,12,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmsevfr_el1",	CPENC (3,0,9,9,5),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmsfcr_el1",		CPENC (3,0,9,9,4),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmsicr_el1",		CPENC (3,0,9,9,2),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmsidr_el1",		CPENC (3,0,9,9,7),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmsirr_el1",		CPENC (3,0,9,9,3),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmslatfr_el1",	CPENC (3,0,9,9,6),       F_ARCHEXT,		AARCH64_FEATURE_PROFILE)
+  SYSREG ("pmsnevfr_el1",	CPENC (3,0,9,9,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_7A)
+  SYSREG ("pmswinc_el0",	CPENC (3,3,9,12,4),      F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("pmuserenr_el0",	CPENC (3,3,9,14,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmxevcntr_el0",	CPENC (3,3,9,13,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("pmxevtyper_el0",	CPENC (3,3,9,13,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("prbar10_el1",	CPENC (3,0,6,13,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar10_el2",	CPENC (3,4,6,13,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar11_el1",	CPENC (3,0,6,13,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar11_el2",	CPENC (3,4,6,13,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar12_el1",	CPENC (3,0,6,14,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar12_el2",	CPENC (3,4,6,14,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar13_el1",	CPENC (3,0,6,14,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar13_el2",	CPENC (3,4,6,14,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar14_el1",	CPENC (3,0,6,15,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar14_el2",	CPENC (3,4,6,15,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar15_el1",	CPENC (3,0,6,15,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar15_el2",	CPENC (3,4,6,15,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar1_el1",		CPENC (3,0,6,8,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar1_el2",		CPENC (3,4,6,8,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar2_el1",		CPENC (3,0,6,9,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar2_el2",		CPENC (3,4,6,9,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar3_el1",		CPENC (3,0,6,9,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar3_el2",		CPENC (3,4,6,9,4),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar4_el1",		CPENC (3,0,6,10,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar4_el2",		CPENC (3,4,6,10,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar5_el1",		CPENC (3,0,6,10,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar5_el2",		CPENC (3,4,6,10,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar6_el1",		CPENC (3,0,6,11,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar6_el2",		CPENC (3,4,6,11,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar7_el1",		CPENC (3,0,6,11,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar7_el2",		CPENC (3,4,6,11,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar8_el1",		CPENC (3,0,6,12,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar8_el2",		CPENC (3,4,6,12,0),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar9_el1",		CPENC (3,0,6,12,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar9_el2",		CPENC (3,4,6,12,4),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar_el1",		CPENC (3,0,6,8,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prbar_el2",		CPENC (3,4,6,8,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prenr_el1",		CPENC (3,0,6,1,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prenr_el2",		CPENC (3,4,6,1,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar10_el1",	CPENC (3,0,6,13,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar10_el2",	CPENC (3,4,6,13,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar11_el1",	CPENC (3,0,6,13,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar11_el2",	CPENC (3,4,6,13,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar12_el1",	CPENC (3,0,6,14,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar12_el2",	CPENC (3,4,6,14,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar13_el1",	CPENC (3,0,6,14,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar13_el2",	CPENC (3,4,6,14,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar14_el1",	CPENC (3,0,6,15,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar14_el2",	CPENC (3,4,6,15,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar15_el1",	CPENC (3,0,6,15,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar15_el2",	CPENC (3,4,6,15,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar1_el1",		CPENC (3,0,6,8,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar1_el2",		CPENC (3,4,6,8,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar2_el1",		CPENC (3,0,6,9,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar2_el2",		CPENC (3,4,6,9,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar3_el1",		CPENC (3,0,6,9,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar3_el2",		CPENC (3,4,6,9,5),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar4_el1",		CPENC (3,0,6,10,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar4_el2",		CPENC (3,4,6,10,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar5_el1",		CPENC (3,0,6,10,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar5_el2",		CPENC (3,4,6,10,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar6_el1",		CPENC (3,0,6,11,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar6_el2",		CPENC (3,4,6,11,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar7_el1",		CPENC (3,0,6,11,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar7_el2",		CPENC (3,4,6,11,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar8_el1",		CPENC (3,0,6,12,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar8_el2",		CPENC (3,4,6,12,1),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar9_el1",		CPENC (3,0,6,12,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar9_el2",		CPENC (3,4,6,12,5),      F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar_el1",		CPENC (3,0,6,8,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prlar_el2",		CPENC (3,4,6,8,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prselr_el1",		CPENC (3,0,6,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("prselr_el2",		CPENC (3,4,6,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("revidr_el1",		CPENC (3,0,0,0,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("rgsr_el1",		CPENC (3,0,1,0,5),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("rmr_el1",		CPENC (3,0,12,0,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("rmr_el2",		CPENC (3,4,12,0,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("rmr_el3",		CPENC (3,6,12,0,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("rndr",		CPENC (3,3,2,4,0),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RNG)
+  SYSREG ("rndrrs",		CPENC (3,3,2,4,1),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_RNG)
+  SYSREG ("rvbar_el1",		CPENC (3,0,12,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("rvbar_el2",		CPENC (3,4,12,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("rvbar_el3",		CPENC (3,6,12,0,1),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("scr_el3",		CPENC (3,6,1,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("sctlr_el1",		CPENC (3,0,1,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("sctlr_el12",		CPENC (3,5,1,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("sctlr_el2",		CPENC (3,4,1,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("sctlr_el3",		CPENC (3,6,1,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("scxtnum_el0",	CPENC (3,3,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
+  SYSREG ("scxtnum_el1",	CPENC (3,0,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
+  SYSREG ("scxtnum_el12",	CPENC (3,5,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
+  SYSREG ("scxtnum_el2",	CPENC (3,4,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
+  SYSREG ("scxtnum_el3",	CPENC (3,6,13,0,7),      F_ARCHEXT,		AARCH64_FEATURE_SCXTNUM)
+  SYSREG ("sder32_el2",		CPENC (3,4,1,3,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("sder32_el3",		CPENC (3,6,1,1,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("smcr_el1",		CPENC (3,0,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("smcr_el12",		CPENC (3,5,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("smcr_el2",		CPENC (3,4,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("smcr_el3",		CPENC (3,6,1,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("smidr_el1",		CPENC (3,1,0,0,6),       F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE_SME)
+  SYSREG ("smpri_el1",		CPENC (3,0,1,2,4),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("smprimap_el2",	CPENC (3,4,1,2,5),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("sp_el0",		CPENC (3,0,4,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("sp_el1",		CPENC (3,4,4,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("sp_el2",		CPENC (3,6,4,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsel",		CPENC (3,0,4,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_abt",		CPENC (3,4,4,3,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_el1",		CPENC (3,0,4,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_el12",		CPENC (3,5,4,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("spsr_el2",		CPENC (3,4,4,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_el3",		CPENC (3,6,4,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_fiq",		CPENC (3,4,4,3,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_hyp",		CPENC (3,4,4,0,0),       F_DEPRECATED,		AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_irq",		CPENC (3,4,4,3,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_svc",		CPENC (3,0,4,0,0),       F_DEPRECATED,		AARCH64_FEATURE_CORE)
+  SYSREG ("spsr_und",		CPENC (3,4,4,3,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ssbs",		CPENC (3,3,4,2,6),       F_ARCHEXT,		AARCH64_FEATURE_SSBS)
+  SYSREG ("svcr",		CPENC (3,3,4,2,2),       F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("tco",		CPENC (3,3,4,2,7),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("tcr_el1",		CPENC (3,0,2,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tcr_el12",		CPENC (3,5,2,0,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("tcr_el2",		CPENC (3,4,2,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tcr_el3",		CPENC (3,6,2,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("teecr32_el1",	CPENC (2,2,0,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("teehbr32_el1",	CPENC (2,2,1,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tfsr_el1",		CPENC (3,0,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("tfsr_el12",		CPENC (3,5,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("tfsr_el2",		CPENC (3,4,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("tfsr_el3",		CPENC (3,6,5,6,0),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("tfsre0_el1",		CPENC (3,0,5,6,1),       F_ARCHEXT,		AARCH64_FEATURE_MEMTAG)
+  SYSREG ("tpidr2_el0",		CPENC (3,3,13,0,5),      F_ARCHEXT,		AARCH64_FEATURE_SME)
+  SYSREG ("tpidr_el0",		CPENC (3,3,13,0,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tpidr_el1",		CPENC (3,0,13,0,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tpidr_el2",		CPENC (3,4,13,0,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tpidr_el3",		CPENC (3,6,13,0,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("tpidrro_el0",	CPENC (3,3,13,0,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trbbaser_el1",	CPENC (3,0,9,11,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trbidr_el1",		CPENC (3,0,9,11,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trblimitr_el1",	CPENC (3,0,9,11,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trbmar_el1",		CPENC (3,0,9,11,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trbptr_el1",		CPENC (3,0,9,11,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trbsr_el1",		CPENC (3,0,9,11,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trbtrg_el1",		CPENC (3,0,9,11,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr0",		CPENC (2,1,2,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr1",		CPENC (2,1,2,2,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr10",		CPENC (2,1,2,4,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr11",		CPENC (2,1,2,6,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr12",		CPENC (2,1,2,8,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr13",		CPENC (2,1,2,10,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr14",		CPENC (2,1,2,12,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr15",		CPENC (2,1,2,14,3),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr2",		CPENC (2,1,2,4,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr3",		CPENC (2,1,2,6,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr4",		CPENC (2,1,2,8,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr5",		CPENC (2,1,2,10,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr6",		CPENC (2,1,2,12,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr7",		CPENC (2,1,2,14,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr8",		CPENC (2,1,2,0,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacatr9",		CPENC (2,1,2,2,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr0",		CPENC (2,1,2,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr1",		CPENC (2,1,2,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr10",		CPENC (2,1,2,4,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr11",		CPENC (2,1,2,6,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr12",		CPENC (2,1,2,8,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr13",		CPENC (2,1,2,10,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr14",		CPENC (2,1,2,12,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr15",		CPENC (2,1,2,14,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr2",		CPENC (2,1,2,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr3",		CPENC (2,1,2,6,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr4",		CPENC (2,1,2,8,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr5",		CPENC (2,1,2,10,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr6",		CPENC (2,1,2,12,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr7",		CPENC (2,1,2,14,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr8",		CPENC (2,1,2,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcacvr9",		CPENC (2,1,2,2,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcauthstatus",	CPENC (2,1,7,14,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcauxctlr",		CPENC (2,1,0,6,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcbbctlr",		CPENC (2,1,0,15,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcccctlr",		CPENC (2,1,0,14,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcctlr0",	CPENC (2,1,3,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcctlr1",	CPENC (2,1,3,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr0",		CPENC (2,1,3,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr1",		CPENC (2,1,3,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr2",		CPENC (2,1,3,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr3",		CPENC (2,1,3,6,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr4",		CPENC (2,1,3,8,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr5",		CPENC (2,1,3,10,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr6",		CPENC (2,1,3,12,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidcvr7",		CPENC (2,1,3,14,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccidr0",		CPENC (2,1,7,12,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trccidr1",		CPENC (2,1,7,13,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trccidr2",		CPENC (2,1,7,14,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trccidr3",		CPENC (2,1,7,15,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcclaimclr",	CPENC (2,1,7,9,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcclaimset",	CPENC (2,1,7,8,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntctlr0",	CPENC (2,1,0,4,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntctlr1",	CPENC (2,1,0,5,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntctlr2",	CPENC (2,1,0,6,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntctlr3",	CPENC (2,1,0,7,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntrldvr0",	CPENC (2,1,0,0,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntrldvr1",	CPENC (2,1,0,1,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntrldvr2",	CPENC (2,1,0,2,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntrldvr3",	CPENC (2,1,0,3,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntvr0",		CPENC (2,1,0,8,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntvr1",		CPENC (2,1,0,9,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntvr2",		CPENC (2,1,0,10,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trccntvr3",		CPENC (2,1,0,11,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcconfigr",		CPENC (2,1,0,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdevaff0",		CPENC (2,1,7,10,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcdevaff1",		CPENC (2,1,7,11,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcdevarch",		CPENC (2,1,7,15,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcdevid",		CPENC (2,1,7,2,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcdevtype",		CPENC (2,1,7,3,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr0",		CPENC (2,1,2,0,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr1",		CPENC (2,1,2,4,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr2",		CPENC (2,1,2,8,6),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr3",		CPENC (2,1,2,12,6),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr4",		CPENC (2,1,2,0,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr5",		CPENC (2,1,2,4,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr6",		CPENC (2,1,2,8,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcmr7",		CPENC (2,1,2,12,7),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr0",		CPENC (2,1,2,0,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr1",		CPENC (2,1,2,4,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr2",		CPENC (2,1,2,8,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr3",		CPENC (2,1,2,12,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr4",		CPENC (2,1,2,0,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr5",		CPENC (2,1,2,4,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr6",		CPENC (2,1,2,8,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcdvcvr7",		CPENC (2,1,2,12,5),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trceventctl0r",	CPENC (2,1,0,8,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trceventctl1r",	CPENC (2,1,0,9,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcextinselr",	CPENC (2,1,0,8,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcextinselr0",	CPENC (2,1,0,8,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcextinselr1",	CPENC (2,1,0,9,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcextinselr2",	CPENC (2,1,0,10,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcextinselr3",	CPENC (2,1,0,11,4),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr0",		CPENC (2,1,0,8,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr1",		CPENC (2,1,0,9,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr10",		CPENC (2,1,0,2,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr11",		CPENC (2,1,0,3,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr12",		CPENC (2,1,0,4,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr13",		CPENC (2,1,0,5,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr2",		CPENC (2,1,0,10,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr3",		CPENC (2,1,0,11,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr4",		CPENC (2,1,0,12,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr5",		CPENC (2,1,0,13,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr6",		CPENC (2,1,0,14,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr7",		CPENC (2,1,0,15,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr8",		CPENC (2,1,0,0,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcidr9",		CPENC (2,1,0,1,6),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec0",		CPENC (2,1,0,0,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec1",		CPENC (2,1,0,1,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec2",		CPENC (2,1,0,2,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec3",		CPENC (2,1,0,3,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec4",		CPENC (2,1,0,4,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec5",		CPENC (2,1,0,5,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec6",		CPENC (2,1,0,6,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcimspec7",		CPENC (2,1,0,7,7),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcitctrl",		CPENC (2,1,7,0,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trclar",		CPENC (2,1,7,12,6),      F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("trclsr",		CPENC (2,1,7,13,6),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcoslar",		CPENC (2,1,1,0,4),       F_REG_WRITE,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcoslsr",		CPENC (2,1,1,1,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpdcr",		CPENC (2,1,1,4,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcpdsr",		CPENC (2,1,1,5,4),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr0",		CPENC (2,1,7,8,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr1",		CPENC (2,1,7,9,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr2",		CPENC (2,1,7,10,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr3",		CPENC (2,1,7,11,7),      F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr4",		CPENC (2,1,7,4,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr5",		CPENC (2,1,7,5,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr6",		CPENC (2,1,7,6,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcpidr7",		CPENC (2,1,7,7,7),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcprgctlr",		CPENC (2,1,0,1,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcprocselr",	CPENC (2,1,0,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcqctlr",		CPENC (2,1,0,1,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr10",	CPENC (2,1,1,10,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr11",	CPENC (2,1,1,11,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr12",	CPENC (2,1,1,12,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr13",	CPENC (2,1,1,13,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr14",	CPENC (2,1,1,14,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr15",	CPENC (2,1,1,15,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr16",	CPENC (2,1,1,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr17",	CPENC (2,1,1,1,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr18",	CPENC (2,1,1,2,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr19",	CPENC (2,1,1,3,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr2",		CPENC (2,1,1,2,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr20",	CPENC (2,1,1,4,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr21",	CPENC (2,1,1,5,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr22",	CPENC (2,1,1,6,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr23",	CPENC (2,1,1,7,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr24",	CPENC (2,1,1,8,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr25",	CPENC (2,1,1,9,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr26",	CPENC (2,1,1,10,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr27",	CPENC (2,1,1,11,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr28",	CPENC (2,1,1,12,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr29",	CPENC (2,1,1,13,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr3",		CPENC (2,1,1,3,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr30",	CPENC (2,1,1,14,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr31",	CPENC (2,1,1,15,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr4",		CPENC (2,1,1,4,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr5",		CPENC (2,1,1,5,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr6",		CPENC (2,1,1,6,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr7",		CPENC (2,1,1,7,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr8",		CPENC (2,1,1,8,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsctlr9",		CPENC (2,1,1,9,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcrsr",		CPENC (2,1,0,10,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcseqevr0",		CPENC (2,1,0,0,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcseqevr1",		CPENC (2,1,0,1,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcseqevr2",		CPENC (2,1,0,2,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcseqrstevr",	CPENC (2,1,0,6,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcseqstr",		CPENC (2,1,0,7,4),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr0",		CPENC (2,1,1,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr1",		CPENC (2,1,1,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr2",		CPENC (2,1,1,2,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr3",		CPENC (2,1,1,3,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr4",		CPENC (2,1,1,4,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr5",		CPENC (2,1,1,5,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr6",		CPENC (2,1,1,6,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcssccr7",		CPENC (2,1,1,7,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr0",		CPENC (2,1,1,8,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr1",		CPENC (2,1,1,9,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr2",		CPENC (2,1,1,10,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr3",		CPENC (2,1,1,11,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr4",		CPENC (2,1,1,12,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr5",		CPENC (2,1,1,13,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr6",		CPENC (2,1,1,14,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsscsr7",		CPENC (2,1,1,15,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr0",	CPENC (2,1,1,0,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr1",	CPENC (2,1,1,1,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr2",	CPENC (2,1,1,2,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr3",	CPENC (2,1,1,3,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr4",	CPENC (2,1,1,4,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr5",	CPENC (2,1,1,5,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr6",	CPENC (2,1,1,6,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcsspcicr7",	CPENC (2,1,1,7,3),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcstallctlr",	CPENC (2,1,0,11,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcstatr",		CPENC (2,1,0,3,0),       F_REG_READ,		AARCH64_FEATURE_CORE)
+  SYSREG ("trcsyncpr",		CPENC (2,1,0,13,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trctraceidr",	CPENC (2,1,0,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trctsctlr",		CPENC (2,1,0,12,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvdarcctlr",	CPENC (2,1,0,10,2),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvdctlr",		CPENC (2,1,0,8,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvdsacctlr",	CPENC (2,1,0,9,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvictlr",		CPENC (2,1,0,0,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcviiectlr",	CPENC (2,1,0,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvipcssctlr",	CPENC (2,1,0,3,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvissctlr",	CPENC (2,1,0,2,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcctlr0",	CPENC (2,1,3,2,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcctlr1",	CPENC (2,1,3,3,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr0",	CPENC (2,1,3,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr1",	CPENC (2,1,3,2,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr2",	CPENC (2,1,3,4,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr3",	CPENC (2,1,3,6,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr4",	CPENC (2,1,3,8,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr5",	CPENC (2,1,3,10,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr6",	CPENC (2,1,3,12,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trcvmidcvr7",	CPENC (2,1,3,14,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("trfcr_el1",		CPENC (3,0,1,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("trfcr_el12",		CPENC (3,5,1,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("trfcr_el2",		CPENC (3,4,1,2,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("ttbr0_el1",		CPENC (3,0,2,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ttbr0_el12",		CPENC (3,5,2,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("ttbr0_el2",		CPENC (3,4,2,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8A)
+  SYSREG ("ttbr0_el3",		CPENC (3,6,2,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ttbr1_el1",		CPENC (3,0,2,0,1),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("ttbr1_el12",		CPENC (3,5,2,0,1),       F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("ttbr1_el2",		CPENC (3,4,2,0,1),       F_ARCHEXT,		AARCH64_FEATURE_V8A|AARCH64_FEATURE_V8_1A)
+  SYSREG ("uao",		CPENC (3,0,4,2,4),       F_ARCHEXT,		AARCH64_FEATURE_V8_2A)
+  SYSREG ("vbar_el1",		CPENC (3,0,12,0,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vbar_el12",		CPENC (3,5,12,0,0),      F_ARCHEXT,		AARCH64_FEATURE_V8_1A)
+  SYSREG ("vbar_el2",		CPENC (3,4,12,0,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vbar_el3",		CPENC (3,6,12,0,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vdisr_el2",		CPENC (3,4,12,1,1),      F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("vmecid_a_el2",	CPENC (3,4,10,9,1),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vmecid_p_el2",	CPENC (3,4,10,9,0),      0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vmpidr_el2",		CPENC (3,4,0,0,5),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vncr_el2",		CPENC (3,4,2,2,0),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("vpidr_el2",		CPENC (3,4,0,0,0),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vsctlr_el2",		CPENC (3,4,2,0,0),       F_ARCHEXT,		AARCH64_FEATURE_V8R)
+  SYSREG ("vsesr_el2",		CPENC (3,4,5,2,3),       F_ARCHEXT,		AARCH64_FEATURE_RAS)
+  SYSREG ("vstcr_el2",		CPENC (3,4,2,6,2),       F_ARCHEXT,		AARCH64_FEATURE_V8_4A)
+  SYSREG ("vsttbr_el2",		CPENC (3,4,2,6,0),       F_ARCHEXT,		AARCH64_FEATURE_V8A|AARCH64_FEATURE_V8_4A)
+  SYSREG ("vtcr_el2",		CPENC (3,4,2,1,2),       0,			AARCH64_FEATURE_CORE)
+  SYSREG ("vttbr_el2",		CPENC (3,4,2,1,0),       F_ARCHEXT,		AARCH64_FEATURE_V8A)
+  SYSREG ("zcr_el1",		CPENC (3,0,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
+  SYSREG ("zcr_el12",		CPENC (3,5,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
+  SYSREG ("zcr_el2",		CPENC (3,4,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)
+  SYSREG ("zcr_el3",		CPENC (3,6,1,2,0),       F_ARCHEXT,		AARCH64_FEATURE_SVE)