diff mbox series

[1/2] x86: generalize "implicit quad group" handling

Message ID f8489bc3-ea1f-4294-9762-ad6c912cd256@suse.com
State New
Headers
Series x86: handle register group also for VP2INTERSECT{D,Q} |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Jan Beulich Nov. 11, 2024, 2:24 p.m. UTC 
  We'll want to re-use it for VP2INTERSECT{D,Q}.

While there add a testcase for the similarly affected AVX512-4VNNIW
insns.
---
I notice that disassembler behavior for this isn't being tested at all:
Right now registers which aren't a multiple of 4 are displayed as is;
no masking of the low bits, no other annotation.
diff mbox series

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -10703,21 +10703,34 @@  process_operands (void)
       i.operands--;
       i.tm.operands--;
     }
-  else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP)
+  else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_GROUP)
     {
-      unsigned int regnum, first_reg_in_group, last_reg_in_group;
+      unsigned int op, extra;
+      const reg_entry *first;
 
-      /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
-      gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
-      regnum = register_number (i.op[1].regs);
-      first_reg_in_group = regnum & ~3;
-      last_reg_in_group = first_reg_in_group + 3;
-      if (regnum != first_reg_in_group)
-	as_warn (_("source register `%s%s' implicitly denotes"
-		   " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
-		 register_prefix, i.op[1].regs->reg_name,
-		 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
-		 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
+      /* The second operand must be {x,y,z}mmN. */
+      gas_assert (i.operands == 3 && i.types[1].bitfield.class == RegSIMD);
+
+      switch (i.types[2].bitfield.class)
+	{
+	case RegSIMD:
+	  /* AVX512-{4FMAPS,4VNNIW} operand 2: N must be a multiple of 4. */
+	  op = 1;
+	  extra = 3;
+	  break;
+
+	default:
+	  abort ();
+	}
+
+      first = i.op[op].regs - (register_number (i.op[op].regs) & extra);
+      if (i.op[op].regs != first)
+	as_warn (_("operand %u `%s%s' implicitly denotes"
+		   " `%s%s' to `%s%s' group in `%s'"),
+		 intel_syntax ? i.operands - op : op + 1,
+		 register_prefix, i.op[op].regs->reg_name,
+		 register_prefix, first[0].reg_name,
+		 register_prefix, first[extra].reg_name,
 		 insn_name (&i.tm));
     }
   else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE)
--- a/gas/testsuite/gas/i386/avx512_4fmaps-warn.l
+++ b/gas/testsuite/gas/i386/avx512_4fmaps-warn.l
@@ -1,13 +1,13 @@ 
 .*: Assembler messages:
-.*:5: Warning: source register `%zmm1' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
-.*:6: Warning: source register `%zmm2' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
-.*:7: Warning: source register `%zmm3' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
-.*:10: Warning: source register `%zmm1' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
-.*:11: Warning: source register `%zmm2' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
-.*:12: Warning: source register `%zmm3' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
-.*:15: Warning: source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddss'
-.*:16: Warning: source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddss'
-.*:17: Warning: source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fmaddss'
-.*:20: Warning: source register `%xmm1' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddss'
-.*:21: Warning: source register `%xmm2' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddss'
-.*:22: Warning: source register `%xmm3' implicitly denotes `%xmm0' to `%xmm3' source group in `v4fnmaddss'
+.*:5: Warning: operand 2 `%zmm1' implicitly denotes `%zmm0' to `%zmm3' group in `v4fmaddps'
+.*:6: Warning: operand 2 `%zmm2' implicitly denotes `%zmm0' to `%zmm3' group in `v4fmaddps'
+.*:7: Warning: operand 2 `%zmm3' implicitly denotes `%zmm0' to `%zmm3' group in `v4fmaddps'
+.*:10: Warning: operand 2 `%zmm1' implicitly denotes `%zmm0' to `%zmm3' group in `v4fnmaddps'
+.*:11: Warning: operand 2 `%zmm2' implicitly denotes `%zmm0' to `%zmm3' group in `v4fnmaddps'
+.*:12: Warning: operand 2 `%zmm3' implicitly denotes `%zmm0' to `%zmm3' group in `v4fnmaddps'
+.*:15: Warning: operand 2 `%xmm1' implicitly denotes `%xmm0' to `%xmm3' group in `v4fmaddss'
+.*:16: Warning: operand 2 `%xmm2' implicitly denotes `%xmm0' to `%xmm3' group in `v4fmaddss'
+.*:17: Warning: operand 2 `%xmm3' implicitly denotes `%xmm0' to `%xmm3' group in `v4fmaddss'
+.*:20: Warning: operand 2 `%xmm1' implicitly denotes `%xmm0' to `%xmm3' group in `v4fnmaddss'
+.*:21: Warning: operand 2 `%xmm2' implicitly denotes `%xmm0' to `%xmm3' group in `v4fnmaddss'
+.*:22: Warning: operand 2 `%xmm3' implicitly denotes `%xmm0' to `%xmm3' group in `v4fnmaddss'
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw-warn.l
@@ -0,0 +1,7 @@ 
+.*: Assembler messages:
+.*:5: Warning: operand 2 `%zmm1' implicitly denotes `%zmm0' to `%zmm3' group in `vp4dpwssd'
+.*:6: Warning: operand 2 `%zmm2' implicitly denotes `%zmm0' to `%zmm3' group in `vp4dpwssd'
+.*:7: Warning: operand 2 `%zmm3' implicitly denotes `%zmm0' to `%zmm3' group in `vp4dpwssd'
+.*:10: Warning: operand 2 `%zmm1' implicitly denotes `%zmm0' to `%zmm3' group in `vp4dpwssds'
+.*:11: Warning: operand 2 `%zmm2' implicitly denotes `%zmm0' to `%zmm3' group in `vp4dpwssds'
+.*:12: Warning: operand 2 `%zmm3' implicitly denotes `%zmm0' to `%zmm3' group in `vp4dpwssds'
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_4vnniw-warn.s
@@ -0,0 +1,13 @@ 
+# Check warnings for invalid usage of register group
+
+.text
+	vp4dpwssd (%eax), %zmm0, %zmm6
+	vp4dpwssd (%eax), %zmm1, %zmm6
+	vp4dpwssd (%eax), %zmm2, %zmm6
+	vp4dpwssd (%eax), %zmm3, %zmm6
+	vp4dpwssd (%eax), %zmm4, %zmm6
+	vp4dpwssds (%eax), %zmm0, %zmm6
+	vp4dpwssds (%eax), %zmm1, %zmm6
+	vp4dpwssds (%eax), %zmm2, %zmm6
+	vp4dpwssds (%eax), %zmm3, %zmm6
+	vp4dpwssds (%eax), %zmm4, %zmm6
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -457,6 +457,7 @@  if [gas_32_check] then {
     run_list_test "avx512_4fmaps-warn"
     run_dump_test "avx512_4vnniw"
     run_dump_test "avx512_4vnniw-intel"
+    run_list_test "avx512_4vnniw-warn"
     run_dump_test "avx512_vpopcntdq"
     run_dump_test "avx512_vpopcntdq-intel"
     run_dump_test "avx512_vpopcntdq_vl"
--- a/gas/testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l
+++ b/gas/testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l
@@ -1,7 +1,7 @@ 
 .*: Assembler messages:
-.*:5: Warning: source register `%zmm1' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
-.*:6: Warning: source register `%zmm2' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
-.*:7: Warning: source register `%zmm3' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fmaddps'
-.*:10: Warning: source register `%zmm1' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
-.*:11: Warning: source register `%zmm2' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
-.*:12: Warning: source register `%zmm3' implicitly denotes `%zmm0' to `%zmm3' source group in `v4fnmaddps'
+.*:5: Warning: operand 2 `%zmm1' implicitly denotes `%zmm0' to `%zmm3' group in `v4fmaddps'
+.*:6: Warning: operand 2 `%zmm2' implicitly denotes `%zmm0' to `%zmm3' group in `v4fmaddps'
+.*:7: Warning: operand 2 `%zmm3' implicitly denotes `%zmm0' to `%zmm3' group in `v4fmaddps'
+.*:10: Warning: operand 2 `%zmm1' implicitly denotes `%zmm0' to `%zmm3' group in `v4fnmaddps'
+.*:11: Warning: operand 2 `%zmm2' implicitly denotes `%zmm0' to `%zmm3' group in `v4fnmaddps'
+.*:12: Warning: operand 2 `%zmm3' implicitly denotes `%zmm0' to `%zmm3' group in `v4fnmaddps'
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -572,10 +572,12 @@  enum
 #define UGH 3
   /* An implicit xmm0 as the first operand */
 #define IMPLICIT_1ST_XMM0 4
-  /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
-     It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
+  /* One of the operands denotes a sequence of registers, with insn-dependent
+     constraint on the first register number.  It implicitly denotes e.g. the
+     register group of {x,y,z}mmN - {x,y,z}mm(N + 3), in which case N ought to
+     be a multiple of 4.
    */
-#define IMPLICIT_QUAD_GROUP 5
+#define IMPLICIT_GROUP 5
   /* Default mask isn't allowed.  */
 #define NO_DEFAULT_MASK 6
   /* Address prefix changes register operand */
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -80,7 +80,7 @@ 
 #define Anysize           OperandConstraint=ANY_SIZE
 #define DistinctDest      OperandConstraint=DISTINCT_DEST
 #define Implicit1stXmm0   OperandConstraint=IMPLICIT_1ST_XMM0
-#define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP
+#define ImplicitGroup     OperandConstraint=IMPLICIT_GROUP
 #define NoDefMask         OperandConstraint=NO_DEFAULT_MASK
 #define RegKludge         OperandConstraint=REG_KLUDGE
 #define Ugh               OperandConstraint=UGH
@@ -2879,17 +2879,17 @@  vpmultishiftqb, 0x6683, AVX512VBMI, Modr
 
 // AVX512_4FMAPS instructions
 
-v4fmaddps, 0xf29a, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-v4fnmaddps, 0xf2aa, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-v4fmaddss, 0xf29b, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
-v4fnmaddss, 0xf2ab, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
+v4fmaddps, 0xf29a, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
+v4fnmaddps, 0xf2aa, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
+v4fmaddss, 0xf29b, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
+v4fnmaddss, 0xf2ab, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
 // AVX512_4FMAPS instructions end
 
 // AVX512_4VNNIW instructions
 
-vp4dpwssd, 0xf252, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
-vp4dpwssds, 0xf253, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
+vp4dpwssd, 0xf252, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
+vp4dpwssds, 0xf253, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
 
 // AVX512_4VNNIW instructions end