diff mbox series

[v4,04/12] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand

Message ID e790534c-6de5-4595-bcd3-34ab3c243cab@suse.com
State New
Headers
Series RISC-V: assorted fixes and (hopefully) improvements |

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Commit Message

Jan Beulich July 24, 2026, 10:03 a.m. UTC 
  Like FCVT.D.W{,U} and FCVT.Q.W{,U} these also are unaffected by rounding
mode, and hence allowing for a respective operand is bogus. (Otherwise
MASK_RM should also be used in the match field for the respectively other
forms.)

Comments

Nelson Chu July 27, 2026, 1:26 a.m. UTC | #1 
On Fri, Jul 24, 2026 at 6:03 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> Like FCVT.D.W{,U} and FCVT.Q.W{,U} these also are unaffected by rounding
> mode, and hence allowing for a respective operand is bogus. (Otherwise
> MASK_RM should also be used in the match field for the respectively other
> forms.)

I checked the spec,
https://docs.riscv.org/reference/isa/v20260120/unpriv/q-st-ext.html#quad-compute,
the fcvt.q.l/lu always produce an exact result and are unaffected by
rounding mode.  You are right, allowing RM operands for them is
unnecessary.

> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1189,9 +1189,7 @@ const struct riscv_opcode riscv_opcodes[
>  {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
>  {"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
>  {"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
>
>  /* Compressed instructions.  */
>  {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU,  match_opcode, 0 },

Since gas/testcase/gas/riscv/zqinx don't use rm operand for them (of
course since that's illegal), so removing them from the opcode table
should be enough.  Looks good, thanks.

Nelson
diff mbox series

Patch

--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1189,9 +1189,7 @@  const struct riscv_opcode riscv_opcodes[
 {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
 {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
 {"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
 {"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
 
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU,  match_opcode, 0 },