From patchwork Mon Aug 12 15:08:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 95690 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 349FD3858432 for ; Mon, 12 Aug 2024 15:09:36 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by sourceware.org (Postfix) with ESMTPS id 74E7D385840B for ; Mon, 12 Aug 2024 15:08:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 74E7D385840B Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 74E7D385840B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::12b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723475290; cv=none; b=mG88OZzddun8iFEyhdj1za96RVZdSnQfEuJ5X0EOEixbft2fE+Oyq1K8SJzsdL4OvrJZV9YOU6z4Pv+PjTVzLbeJaLdQVnXjPhGLGAAi8+gOIXTQtfNkXJn2qP2MwNWm7vG/XjDvvfi7RvgCaAh2Mz+O3Ay/AfJBZ586YYsMTCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723475290; c=relaxed/simple; bh=IdGWiwX5358uF8Qbi6/7QLccce+7NPMnFqUEZxyZd5A=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:From:To; b=vYe6AQJeOxO1iE/wdZGB39j1JoTGQ0Sbo5eE5/V/4cnvPyAiOq3W28hmRrwsTwhU91FijqaFNnPRUlIbXPxHvYnYxvEM6E3gcuPpAvnACBHEltPaRogQ2kFoOpddexcstRK1OKaVXE1cGCZc/2uQNUvbV9x7bQJpTvado0C7TO0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-5314c6dbaa5so3467407e87.2 for ; Mon, 12 Aug 2024 08:08:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1723475286; x=1724080086; darn=sourceware.org; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=/v7BUAEgYr8GlWGbE7BhY3aAeG180w5SKev0iotZyGA=; b=YBzX8MliH90sQB0sIw4l9+NzjSgE1ssp6edLZl/3ZJRBMCzLChHX1Z5z9cqN9DVcq+ CCG7s1tV7+5LKJnm8URDqY8dNX1RM4QvF470F3d+Mtsedd2y9aY0dOfmMgTrgfPbXOPZ N36kVpgvZfLYulI1IkYb7iNDVywj+vmGWg4oCQbdqjXFeuh+RTQDsYpb9ifXI9aMy+/J y2k8Lx4vgHNFqI/REujQ9uAXMfb0E+S0cUz798XaRnt/2clazkZMmQ9jdXJjXNBrK/sq j+PmlVqtEDf9o1wI31+0/2hxWy8vdA5nCnn5JihrMU35r6gSK+AOMgQ1kyHJAJ74guyj EKHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723475286; x=1724080086; h=content-transfer-encoding:in-reply-to:autocrypt:content-language :references:cc:to:from:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/v7BUAEgYr8GlWGbE7BhY3aAeG180w5SKev0iotZyGA=; b=pBAoW173N0SoEoHjJUyKPD90IOCXTcxZSvv3JLHZdkScWp6AG0o7kk+pyGLqxP3106 EOpMftpUDdjK4bXue7rzUB26r5VDtVApAdmDLDW48YwzX4YwFMomdAmzpb5GzQ7ncUGx G5qfPKGSr5DfQ/a+jztTf212TrRkwSJlg0jIMmZc1yFd0+GaiyHLA2HilBSx/MaGzl9J plf96oh+TUI+TkkH7RiSaDhv7u2WrikIz1XUdAvE+jEmFdf3S2+L0mdFmtwsGdAIP4Dl gcNtz9L9Zji9FsslnxHMaF+3aG1g0ZwdYRnQQzUijNJSNIvQ+rjfQWJEl0aA1fcaC3Ar aTtQ== X-Gm-Message-State: AOJu0YwURZLwgyVj37F8sqQk7WoKxLSmqotCEjieHx9BJ+MfVM4pPHCX D86u9upC7islkTNhsilv+3uYRwU0Qqi55RuZJZvER2J682MnNGvekANU21aRHTrggI8JZQpu34w = X-Google-Smtp-Source: AGHT+IGjnlJk0dF25c5CUleJg4KiueodC9IYqQVNXccFcFBeMyvXO4myutON2NMrT1ddgXLcdIvyog== X-Received: by 2002:a05:6512:2256:b0:52e:91ff:4709 with SMTP id 2adb3069b0e04-5321365430emr331525e87.21.1723475285545; Mon, 12 Aug 2024 08:08:05 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80bb1d14d1sm238249966b.111.2024.08.12.08.08.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Aug 2024 08:08:05 -0700 (PDT) Message-ID: Date: Mon, 12 Aug 2024 17:08:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/3] RISC-V: correct alignment directive handling for text sections From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu References: <78240b26-005c-4db3-940d-da618e06cb66@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <78240b26-005c-4db3-940d-da618e06cb66@suse.com> X-Spam-Status: No, score=-3023.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org .insn or data emitted inside text sections can lead to positions not being at insn granularity. In such situations using alignment directives should reliably enforce the requested alignment. Specifically requests to align back to insn granularity may not be ignored (where, as a subcase thereof, the ordering of ".option norvc" and e.g. ".p2align 2" should not matter; so far the alignment directive needs to come first to have any effect). Similarly ahead of emitting NOPs alignment first needs to be forced back to insn granularity. The new testcases actually point out a corner case issue in the disassembler as well, which is being corrected at the same time: We don't want to print "0x" without any subsequent digits. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -183,6 +183,9 @@ static enum float_abi float_abi = FLOAT_ static unsigned elf_flags = 0; +/* Indicate we are already assemble any instructions or not. */ +static bool start_assemble = false; + static bool probing_insn_operands; /* Set the default_isa_spec. Return 0 if the spec isn't supported. @@ -280,6 +283,16 @@ riscv_set_rvc (bool rvc_value) if (rvc_value) elf_flags |= EF_RISCV_RVC; + if (start_assemble && subseg_text_p (now_seg) + && riscv_opts.rvc && !rvc_value) + { + struct riscv_segment_info_type *info + = &seg_info(now_seg)->tc_segment_info_data; + + info->last_insn16 = true; + info->rvc = rvc_value; + } + riscv_opts.rvc = rvc_value; } @@ -349,10 +362,8 @@ riscv_set_arch (const char *s) riscv_parse_subset (&riscv_rps_as, s); riscv_reset_subsets_list_arch_str (); - riscv_set_rvc (false); - if (riscv_subset_supports (&riscv_rps_as, "c") - || riscv_subset_supports (&riscv_rps_as, "zca")) - riscv_set_rvc (true); + riscv_set_rvc (riscv_subset_supports (&riscv_rps_as, "c") + || riscv_subset_supports (&riscv_rps_as, "zca")); if (riscv_subset_supports (&riscv_rps_as, "ztso")) riscv_set_tso (); @@ -452,9 +463,6 @@ const char EXP_CHARS[] = "eE"; As in 0f12.456 or 0d1.2345e12. */ const char FLT_CHARS[] = "rRsSfFdDxXpPhH"; -/* Indicate we are already assemble any instructions or not. */ -static bool start_assemble = false; - /* Indicate ELF attributes are explicitly set. */ static bool explicit_attr = false; @@ -622,6 +630,7 @@ riscv_mapping_state (enum riscv_seg_msta valueT value = (valueT) (frag_now_fix () - max_chars); seg_info (now_seg)->tc_segment_info_data.map_state = to_state; + seg_info (now_seg)->tc_segment_info_data.last_insn16 = false; const char *arch_str = reset_seg_arch_str ? riscv_rps_as.subset_list->arch_str : NULL; make_mapping_symbol (to_state, value, frag_now, arch_str, @@ -4148,12 +4157,13 @@ riscv_ip_hardcode (char *str, generic_bignum[num], llen); memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); - return NULL; } - - if (bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0) + else if (bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0) return _("value conflicts with instruction length"); + if (!riscv_opts.rvc && (bytes & 2)) + seg_info (now_seg)->tc_segment_info_data.last_insn16 = true; + return NULL; } @@ -4840,10 +4850,8 @@ s_riscv_option (int x ATTRIBUTE_UNUSED) riscv_update_subset (&riscv_rps_as, name); riscv_reset_subsets_list_arch_str (); - riscv_set_rvc (false); - if (riscv_subset_supports (&riscv_rps_as, "c") - || riscv_subset_supports (&riscv_rps_as, "zca")) - riscv_set_rvc (true); + riscv_set_rvc (riscv_subset_supports (&riscv_rps_as, "c") + || riscv_subset_supports (&riscv_rps_as, "zca")); if (riscv_subset_supports (&riscv_rps_as, "ztso")) riscv_set_tso (); @@ -4951,15 +4959,27 @@ riscv_frag_align_code (int n) char *nops; expressionS ex; - /* If we are moving to a smaller alignment than the instruction size, then no - alignment is required. */ + /* If we are moving to alignment no larger than the instruction size, then + no special alignment handling is required. */ if (bytes <= insn_alignment) - return true; + { + if (bytes == insn_alignment) + seg_info (now_seg)->tc_segment_info_data.last_insn16 = false; + return false; + } /* When not relaxing, riscv_handle_align handles code alignment. */ if (!riscv_opts.relax) return false; + /* If the last item emitted was not an ordinary insn, first align back to + insn granularity. Don't do this unconditionally, to avoid altering frags + when that's not actually needed. */ + if (seg_info (now_seg)->tc_segment_info_data.map_state != MAP_INSN + || seg_info (now_seg)->tc_segment_info_data.last_insn16) + frag_align_code (riscv_opts.rvc ? 1 : 2, 0); + seg_info (now_seg)->tc_segment_info_data.last_insn16 = false; + /* Maybe we should use frag_var to create a new rs_align_code fragment, rather than just use frag_more to handle an alignment here? So that we don't need to call riscv_mapping_state again later, and then only need @@ -5277,6 +5297,18 @@ tc_riscv_regname_to_dw2regnum (char *reg } void +riscv_elf_section_change_hook (void) +{ + struct riscv_segment_info_type *info + = &seg_info(now_seg)->tc_segment_info_data; + + if (info->rvc && !riscv_opts.rvc) + info->last_insn16 = true; + + info->rvc = riscv_opts.rvc; +} + +void riscv_elf_final_processing (void) { riscv_set_abi_by_arch (); --- a/gas/config/tc-riscv.h +++ b/gas/config/tc-riscv.h @@ -127,6 +127,9 @@ extern int tc_riscv_regname_to_dw2regnum /* Even on RV64, use 4-byte alignment, as F registers may be only 32 bits. */ #define DWARF2_CIE_DATA_ALIGNMENT -4 +#define md_elf_section_change_hook riscv_elf_section_change_hook +extern void riscv_elf_section_change_hook (void); + #define elf_tc_final_processing riscv_elf_final_processing extern void riscv_elf_final_processing (void); @@ -152,6 +155,8 @@ void riscv_mapping_state (enum riscv_seg struct riscv_segment_info_type { enum riscv_seg_mstate map_state; + bool rvc; + bool last_insn16; /* The current mapping symbol with architecture string. */ symbolS *arch_map_symbol; }; --- /dev/null +++ b/gas/testsuite/gas/riscv/relax-align-2.d @@ -0,0 +1,52 @@ +#as: -mrelax +#objdump: -drw + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+8082[ ]+ret +[ ]+2:[ ]+0001[ ]+nop +[ ]+4:[ ]+00000013[ ]+nop[ ]+4: R_RISCV_ALIGN[ ]+\*ABS\*\+0x4 + +0+008 : +[ ]+8:[ ]+00008067[ ]+ret + +0+00c : +[ ]+c:[ ]+00000013[ ]+nop +[ ]+10:[ ]+0000[ ]+\.insn 2, 0x0+ +[ ]+12:[ ]+0001[ ]+\.insn 2, 0x0*1 +[ ]+14:[ ]+00000013[ ]+nop[ ]+14: R_RISCV_ALIGN[ ]+\*ABS\*\+0x4 +[ ]+18:[ ]+00008067[ ]+ret + +0+001c : +[ ]+1c:[ ]+00000013[ ]+nop +[ ]+20:[ ]+0000[ ]+\.short 0x0+ +[ ]+22:[ ]+0001[ ]+\.insn 2, 0x0*1 +[ ]+24:[ ]+00000013[ ]+nop[ ]+24: R_RISCV_ALIGN[ ]+\*ABS\*\+0x4 +[ ]+28:[ ]+00008067[ ]+ret + +0+002c : +[ ]+2c:[ ]+00000013[ ]+nop +[ ]+30:[ ]+00[ ]+\.byte 0x0+ +[ ]+31:[ ]+00[ ]+\.byte 0x0+ +[ ]+32:[ ]+0001[ ]+\.insn 2, 0x0*1 +[ ]+34:[ ]+00000013[ ]+nop[ ]+34: R_RISCV_ALIGN[ ]+\*ABS\*\+0x4 +[ ]+38:[ ]+00008067[ ]+ret +[ ]+3c:[ ]+00000013[ ]+nop[ ]+3c: R_RISCV_ALIGN[ ]+\*ABS\*\+0x4 + +0+0040 : +[ ]+40:[ ]+00000013[ ]+nop +[ ]+44:[ ]+00008067[ ]+ret + +0+0048 : +[ ]+48:[ ]+8082[ ]+ret +[ ]+4a:[ ]+0001[ ]+nop +[ ]+4c:[ ]+00000013[ ]+nop[ ]+4c: R_RISCV_ALIGN[ ]+\*ABS\*\+0x4 + +0+0050 : +[ ]+50:[ ]+00000013[ ]+nop +[ ]+54:[ ]+00008067[ ]+ret +#pass --- /dev/null +++ b/gas/testsuite/gas/riscv/relax-align-2.s @@ -0,0 +1,50 @@ + .text + .option rvc +rvc_func: + ret + + .option norvc + .p2align 3 +non_rvc_func: + ret + +insn: + nop + .insn 0 + .p2align 3 + ret + +hword: + nop + .hword 0 + .p2align 3 + ret + +byte: + nop + .byte 0 + .p2align 3 + ret + + .p2align 3 +func1: + nop + ret + + .pushsection .text1, "ax", @progbits + .option rvc + nop + .popsection + +func2: + ret + + .pushsection .text1, "ax", @progbits + nop + .option norvc + .popsection + + .p2align 3 +func3: + nop + ret --- /dev/null +++ b/gas/testsuite/gas/riscv/relax-align.d @@ -0,0 +1,34 @@ +#as: -mrelax +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+8082[ ]+ret +[ ]+2:[ ]+0001[ ]+nop + +0+004 : +[ ]+4:[ ]+00008067[ ]+ret + +0+008 : +[ ]+8:[ ]+00000013[ ]+nop +[ ]+c:[ ]+0000[ ]+\.insn 2, 0x0+ +[ ]+e:[ ]+0001[ ]+\.insn 2, 0x0*1 +[ ]+10:[ ]+00008067[ ]+ret + +0+0014 : +[ ]+14:[ ]+00000013[ ]+nop +[ ]+18:[ ]+0000[ ]+\.short 0x0+ +[ ]+1a:[ ]+0001[ ]+\.insn 2, 0x0*1 +[ ]+1c:[ ]+00008067[ ]+ret + +0+0020 : +[ ]+20:[ ]+00000013[ ]+nop +[ ]+24:[ ]+00[ ]+\.byte 0x0+ +[ ]+25:[ ]+00[ ]+\.byte 0x0+ +[ ]+26:[ ]+0001[ ]+\.insn 2, 0x0*1 +[ ]+28:[ ]+00008067[ ]+ret +#pass --- /dev/null +++ b/gas/testsuite/gas/riscv/relax-align.s @@ -0,0 +1,27 @@ + .text + .option rvc +rvc_func: + ret + + .option norvc + .p2align 2 +non_rvc_func: + ret + +insn: + nop + .insn 0 + .p2align 2 + ret + +hword: + nop + .hword 0 + .p2align 2 + ret + +byte: + nop + .byte 0 + .p2align 2 + ret --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -994,7 +994,7 @@ riscv_disassemble_insn (bfd_vma memaddr, { i -= 2; word = bfd_get_bits (packet + i, 16, false); - if (!word && !printed) + if (!word && !printed && i) continue; (*info->fprintf_styled_func) (info->stream, dis_style_immediate,