diff mbox series

[4/5] aarch64: Remove disassembly restriction on OP_MOV_Z_Zi

Message ID de2b284f-5c7c-1d6f-f520-ad38388ead8a@e124511.cambridge.arm.com
State New
Headers
Series aarch64: Remove aarch64_field_kind indirection |

Checks

Context Check Description
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Commit Message

Alice Carlotti May 20, 2026, 12:09 p.m. UTC 
  Disassembly for the OP_MOV_Z_Zi opcode artificially rejected a zero
index value, to indicate that the preferred disassembly uses a different
alias.  This is more naturally indicated by specifying the other alias
as a higher priority.

Update the alias priority, and remove the zero check and the now-unused
OP_MOV_Z_Zi enum value.
diff mbox series

Patch

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6d1b414444ae65f76cb4362d1d7e861156fc2759..23e9ec66ee2c2d5d5a97012d959bcb052cad706b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1325,7 +1325,6 @@  enum aarch64_op
   OP_MOV_Z_P_Z,
   OP_MOV_Z_V,
   OP_MOV_Z_Z,
-  OP_MOV_Z_Zi,
   OP_MOVM_P_P_P,
   OP_MOVS_P_P,
   OP_MOVZS_P_P_P,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index d2e302e610022056eb174344b610a7aedebe85da..98c24a8620e7781bf83fda4c6611454c86586313 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -631,8 +631,8 @@  aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case A64_OPID_05203800_dup_SVE_Zd_Rn_SP:
       value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP;
       break;
-    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
     case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn:
+    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
     case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX:
       value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX;
       break;
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 305ac2981ce421f703d46aabc5852622017ab5d9..ef1e093ed94ef3923399e00fbd4495047b5e4969 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1968,8 +1968,6 @@  do_misc_encoding (aarch64_inst *inst)
       value = extract_field (FLD_SVE_Zn, inst->value, 0);
       insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
       break;
-    case OP_MOV_Z_Zi:
-      break;
     case OP_MOVM_P_P_P:
       /* Copy Pd to Pm.  */
       value = extract_field (FLD_SVE_Pd, inst->value, 0);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 3cbf33db77cd2540ef5298364b7deb18b05575b1..1219bf00e0669517f466c4d7cf6ddc110271b12c 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -36944,7 +36944,7 @@  aarch64_find_alias_opcode (const aarch64_opcode *opcode)
       value = A64_OPID_05203800_mov_SVE_Zd_Rn_SP;
       break;
     case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX:
-      value = A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX;
+      value = A64_OPID_05202000_mov_SVE_Zd_SVE_VZn;
       break;
     case A64_OPID_2538c000_dup_SVE_Zd_SVE_ASIMM:
       value = A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0;
@@ -37638,10 +37638,10 @@  aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
     case A64_OPID_05203800_mov_SVE_Zd_Rn_SP:
       value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP;
       break;
-    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
-      value = A64_OPID_05202000_mov_SVE_Zd_SVE_VZn;
-      break;
     case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn:
+      value = A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX;
+      break;
+    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
       value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX;
       break;
     case A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index f86c5026cf7ccf2935be67cbedb274366e6c04e0..3723defe5e019d9188b150e16f645b0551421688 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2729,11 +2729,6 @@  do_misc_decoding (aarch64_inst *inst)
       return (extract_field (FLD_SVE_Zn, inst->value, 0)
 	      == extract_field (FLD_SVE_Zm_16, inst->value, 0));
 
-    case OP_MOV_Z_Zi:
-      /* Index must be nonzero.  */
-      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
-      return value > 0 && value != (value & -value);
-
     case OP_MOVM_P_P_P:
       return (extract_field (FLD_SVE_Pd, inst->value, 0)
 	      == extract_field (FLD_SVE_Pm, inst->value, 0));
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index b9a632300df5eacbb1c608f4757100aa425fe114..a6d43a13f4cfa74447203dc81c1e895e4b4c0440 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -461,7 +461,6 @@  static const enum aarch64_opcode_idx op_enum_table [] =
   A64_OPID_0520c000_mov_SVE_Zd_SVE_Pg4_10_SVE_Zn,
   A64_OPID_05202000_mov_SVE_Zd_SVE_VZn,
   A64_OPID_04603000_mov_SVE_Zd_SVE_Zn,
-  A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX,
   A64_OPID_25004210_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn,
   A64_OPID_25c04000_movs_SVE_Pd_SVE_Pn,
   A64_OPID_25404000_movs_SVE_Pd_SVE_Pg4_10_SVE_Pn,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0a30e720d9dee56fd090c35cc70a09db7f1e7b4b..c58f4dd7972468dc81af1168f38fabab182069ed 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5268,11 +5268,11 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
   _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
-  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
+  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_P1 | F_MISC, 0),
   _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_PSEUDO | F_MISC, 0),
-  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
+  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
   _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0),