[v2,2.42,Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1

Message ID cfd7aa90-18ea-a2b5-d40c-bfff620ea74e@e124511.cambridge.arm.com
State Committed
Headers
Series [v2,2.42,Backport] aarch64: Remove B16B16, SVE2p1 and SME2p1 |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply

Commit Message

Andrew Carlotti March 8, 2024, 5:32 p.m. UTC
  Support for these extensions is broken and incomplete in the 2.42
branch, with a number of syntax and opcode bugs.  This patch removes the
flags and documentation, to avoid any further suggestion that this
extension is fully and correctly supported.
---

Is this version ok for the 2.42 branch?
  

Comments

Jan Beulich March 11, 2024, 7:10 a.m. UTC | #1
On 08.03.2024 18:32, Andrew Carlotti wrote:
> Support for these extensions is broken and incomplete in the 2.42
> branch, with a number of syntax and opcode bugs.  This patch removes the
> flags and documentation, to avoid any further suggestion that this
> extension is fully and correctly supported.
> ---
> 
> Is this version ok for the 2.42 branch?

This looks much better to me (for the purpose), so I'd say yes. But please
give Richard and/or Marcus a chance to chime in.

Jan
  
Andrew Carlotti March 11, 2024, 5:38 p.m. UTC | #2
On Mon, Mar 11, 2024 at 08:10:20AM +0100, Jan Beulich wrote:
> On 08.03.2024 18:32, Andrew Carlotti wrote:
> > Support for these extensions is broken and incomplete in the 2.42
> > branch, with a number of syntax and opcode bugs.  This patch removes the
> > flags and documentation, to avoid any further suggestion that this
> > extension is fully and correctly supported.
> > ---
> > 
> > Is this version ok for the 2.42 branch?
> 
> This looks much better to me (for the purpose), so I'd say yes. But please
> give Richard and/or Marcus a chance to chime in.
> 
> Jan

Richard expressed a preference for this approach last time, and was looking
over my shoulder when I wrote the new part of gas/NEWS, so I'll consider it ok
to merge in 24 hours if noone else objects before then.
  
Andrew Carlotti March 14, 2024, 5:18 p.m. UTC | #3
On Mon, Mar 11, 2024 at 05:38:17PM +0000, Andrew Carlotti wrote:
> On Mon, Mar 11, 2024 at 08:10:20AM +0100, Jan Beulich wrote:
> > On 08.03.2024 18:32, Andrew Carlotti wrote:
> > > Support for these extensions is broken and incomplete in the 2.42
> > > branch, with a number of syntax and opcode bugs.  This patch removes the
> > > flags and documentation, to avoid any further suggestion that this
> > > extension is fully and correctly supported.
> > > ---
> > > 
> > > Is this version ok for the 2.42 branch?
> > 
> > This looks much better to me (for the purpose), so I'd say yes. But please
> > give Richard and/or Marcus a chance to chime in.
> > 
> > Jan
> 
> Richard expressed a preference for this approach last time, and was looking
> over my shoulder when I wrote the new part of gas/NEWS, so I'll consider it ok
> to merge in 24 hours if noone else objects before then.

Pushed.

With this patch in place, the remaining incorrect behaviour is limited to:

- Assembly: some instances of incorrect error selection for unsupported
  instructions (e.g. reporting an unsupported instruction instead of wrong
  operands, or vice versa).  Supported instructions are unaffected outside of
  error cases, because these take precedence over unsupported instructions.

- Disassembly: some cases of incorrect disassembly for unsupported instructions
  (i.e. those that would otherwise be disassembled as `.inst 0xnnnnnnnn`).  Any
  supported instructions will disassemble correctly, because earlier instructions
  in the opcode table take precedence.
  

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 67d806cbf89e07ea5507968086e84934649dfec6..dfccd9f1dc779c233a4646468ff924f76387282f 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,15 +1,14 @@ 
 -*- text -*-
 
-Changes in 2.42:
-
-* Added support for AMD znver5 processor (available from GNU Binutils 2.42 release).
+Changes in 2.42.1:
 
-* Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
+* The options to enable the AArch64 SVE2.1, SME2.1 and B16B16 extensions have
+  been disabled, because of a number of known issues with their implementation
+  in the 2.42 release.
 
-* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
+Changes in 2.42:
 
-* Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
-  (B16B16).
+* Added support for AMD znver5 processor (available from GNU Binutils 2.42 release).
 
 * Add support for the AArch64 Reliability, Availability and Serviceability
   extension v2 (RASv2).
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0c6de289408f4c53633e468c610623c22a0fdec8..a7c29d2f03f74a0384dcb5b96c08a1827cda5a8d 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10425,9 +10425,6 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"ite",		AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
   {"d128",		AARCH64_FEATURE (D128),
 			AARCH64_FEATURE (LSE128)},
-  {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
-  {"sme2p1",		AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
-  {"sve2p1",		AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
   {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..77226a07973c9e9c232c595b14bd82728648170e 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -161,8 +161,6 @@  automatically cause those extensions to be disabled.
 @headitem Extension @tab Depends upon @tab Description
 @item @code{aes} @tab @code{simd}
  @tab Enable the AES and PMULL cryptographic extensions.
-@item @code{b16b16} @tab @code{sve2}
- @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
 @item @code{bf16} @tab @code{fp}
  @tab Enable BFloat16 extension.
 @item @code{chk} @tab
@@ -263,8 +261,6 @@  automatically cause those extensions to be disabled.
  @tab Enable SME I16I64 Extension.
 @item @code{sme2} @tab @code{sme}
  @tab Enable SME2.
-@item @code{sme2p1} @tab @code{sme2}
- @tab Enable SME2.1.
 @item @code{ssbs} @tab
  @tab Enable Speculative Store Bypassing Safe state read and write.
 @item @code{sve} @tab @code{fcma}
@@ -279,8 +275,6 @@  automatically cause those extensions to be disabled.
  @tab Enable the SVE2 SHA3 Extension.
 @item @code{sve2-sm4} @tab @code{sve2}, @code{sm4}
  @tab Enable the SVE2 SM4 Extension.
-@item @code{sve2p1} @tab @code{sve2}
- @tab Enable SVE2.1.
 @item @code{the} @tab
  @tab Enable the Translation Hardening Extension.
 @item @code{tme} @tab
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d
index f0d436bec585ff2aee2e007d63fc672a11a569b9..0f4ab764d24ee63602ba7c6b3141815b343e9e4a 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.d
@@ -1,6 +1,7 @@ 
 #name: Test of SVE2.1 and SME2.1 non-widening BFloat16 instructions.
 #as: -march=armv9.4-a+b16b16
 #objdump: -dr
+#xfail: *-*-*
 
 [^:]+:     file format .*
 
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..4b94cc9e4a0b86eeae64124941f35a0500637377 100644
--- a/gas/testsuite/gas/aarch64/sme2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sme2p1-1.d
@@ -1,6 +1,7 @@ 
 #name: Test of SME2.1 movaz instructions.
 #as: -march=armv9.4-a+sme2p1
 #objdump: -dr
+#xfail: *-*-*
 
 [^:]+:     file format .*
 
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index daece899b38bba4daa2ca9e58dba2d551f6cf988..72fac004141cc221b75a2714ce32d864e39d2b6b 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -1,6 +1,7 @@ 
 #name: Test of SVE2.1 min max instructions.
 #as: -march=armv9.4-a+sve2p1
 #objdump: -dr
+#xfail: *-*-*
 
 [^:]+:     file format .*