[v3,2/3] RISC-V: Add "lp64e" ABI support
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Commit Message
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Since RV32E and RV64E are now ratified, this commit prepares the ABI
support for LP64E (LP64 with reduced GPRs).
gas/ChangeLog:
* config/tc-riscv.c (riscv_set_abi_by_arch): Update the error
message. (md_parse_option): Accept "lp64e".
* doc/c-riscv.texi: Update the documentation to allow "lp64e".
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l:
Change error message.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise.
---
gas/config/tc-riscv.c | 4 +++-
gas/doc/c-riscv.texi | 5 ++---
gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +-
gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +-
gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +-
5 files changed, 8 insertions(+), 7 deletions(-)
@@ -386,7 +386,7 @@ riscv_set_abi_by_arch (void)
as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi)
- as_bad ("only the ilp32e ABI is supported for e extension");
+ as_bad ("only ilp32e/lp64e ABI are supported for e extension");
if (float_abi == FLOAT_ABI_SINGLE
&& !riscv_subset_supports (&riscv_rps_as, "f"))
@@ -3871,6 +3871,8 @@ md_parse_option (int c, const char *arg)
riscv_set_abi (32, FLOAT_ABI_QUAD, false);
else if (strcmp (arg, "lp64") == 0)
riscv_set_abi (64, FLOAT_ABI_SOFT, false);
+ else if (strcmp (arg, "lp64e") == 0)
+ riscv_set_abi (64, FLOAT_ABI_SOFT, true);
else if (strcmp (arg, "lp64f") == 0)
riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
else if (strcmp (arg, "lp64d") == 0)
@@ -65,9 +65,8 @@ aren't set, then assembler will check the default configure setting
@item -mabi=ABI
Selects the ABI, which is either "ilp32" or "lp64", optionally followed
by "f", "d", or "q" to indicate single-precision, double-precision, or
-quad-precision floating-point calling convention, or none to indicate
-the soft-float calling convention. Also, "ilp32" can optionally be followed
-by "e" to indicate the RVE ABI, which is always soft-float.
+quad-precision floating-point calling convention, or none or "e" to indicate
+the soft-float calling convention ("e" indicates a soft-float RVE ABI).
@cindex @samp{-mrelax} option, RISC-V
@item -mrelax
@@ -1,4 +1,4 @@
.*Assembler messages:
.*Error: can't have 64-bit ABI on 32-bit ISA
-.*Error: only the ilp32e ABI is supported for e extension
+.*Error: only ilp32e/lp64e ABI are supported for e extension
.*Error: ilp32d/lp64d ABI can't be used when d extension isn't supported
@@ -1,4 +1,4 @@
.*Assembler messages:
.*Error: can't have 64-bit ABI on 32-bit ISA
-.*Error: only the ilp32e ABI is supported for e extension
+.*Error: only ilp32e/lp64e ABI are supported for e extension
.*Error: ilp32f/lp64f ABI can't be used when f extension isn't supported
@@ -1,4 +1,4 @@
.*Assembler messages:
.*Error: can't have 64-bit ABI on 32-bit ISA
-.*Error: only the ilp32e ABI is supported for e extension
+.*Error: only ilp32e/lp64e ABI are supported for e extension
.*Error: ilp32q/lp64q ABI can't be used when q extension isn't supported