[3/3,2.42,Backport] aarch64: Remove B16B16

Message ID b515ecb5-e829-cf0d-4d1a-107b9bc5c5b6@e124511.cambridge.arm.com
State Superseded
Headers
Series aarch64: Remove B16B16, SVE2p1 and SME2p1 |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Testing failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Andrew Carlotti Feb. 29, 2024, 5:36 p.m. UTC
  Support for this extension is incomplete and has opcode bugs in the 2.42
branch.  This patch removes the flags and documentation, to avoid any
further suggestion that this extension is fully and correctly supported.
  

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 75e6c9465aaa3871bb5acd367d6f8feab9b6d860..3a9dbc7d2e022d360e5b1a0aaa684ad76b51b17d 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -4,9 +4,6 @@  Changes in 2.42:
 
 * Added support for AMD znver5 processor (available from GNU Binutils 2.42 release).
 
-* Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
-  (B16B16).
-
 * Add support for the AArch64 Reliability, Availability and Serviceability
   extension v2 (RASv2).
 
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 696283b456ceb7bd57ba4f021dd4b371e3ff15d4..a7c29d2f03f74a0384dcb5b96c08a1827cda5a8d 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10425,7 +10425,6 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"ite",		AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
   {"d128",		AARCH64_FEATURE (D128),
 			AARCH64_FEATURE (LSE128)},
-  {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
   {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 818f98ef8589228012fe583b56082f3027780434..77226a07973c9e9c232c595b14bd82728648170e 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -161,8 +161,6 @@  automatically cause those extensions to be disabled.
 @headitem Extension @tab Depends upon @tab Description
 @item @code{aes} @tab @code{simd}
  @tab Enable the AES and PMULL cryptographic extensions.
-@item @code{b16b16} @tab @code{sve2}
- @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
 @item @code{bf16} @tab @code{fp}
  @tab Enable BFloat16 extension.
 @item @code{chk} @tab
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d
deleted file mode 100644
index f0d436bec585ff2aee2e007d63fc672a11a569b9..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ /dev/null
@@ -1,106 +0,0 @@ 
-#name: Test of SVE2.1 and SME2.1 non-widening BFloat16 instructions.
-#as: -march=armv9.4-a+b16b16
-#objdump: -dr
-
-[^:]+:     file format .*
-
-
-[^:]+:
-
-[^:]+:
-.*:	65008200 	bfadd	z0.h, p0\/m, z0.h, z16.h
-.*:	65008501 	bfadd	z1.h, p1\/m, z1.h, z8.h
-.*:	65008882 	bfadd	z2.h, p2\/m, z2.h, z4.h
-.*:	65009044 	bfadd	z4.h, p4\/m, z4.h, z2.h
-.*:	65009828 	bfadd	z8.h, p6\/m, z8.h, z1.h
-.*:	65009c10 	bfadd	z16.h, p7\/m, z16.h, z0.h
-.*:	65068200 	bfmax	z0.h, p0\/m, z0.h, z16.h
-.*:	65068501 	bfmax	z1.h, p1\/m, z1.h, z8.h
-.*:	65068882 	bfmax	z2.h, p2\/m, z2.h, z4.h
-.*:	65069044 	bfmax	z4.h, p4\/m, z4.h, z2.h
-.*:	65069828 	bfmax	z8.h, p6\/m, z8.h, z1.h
-.*:	65069c10 	bfmax	z16.h, p7\/m, z16.h, z0.h
-.*:	65048200 	bfmaxnm	z0.h, p0\/m, z0.h, z16.h
-.*:	65048501 	bfmaxnm	z1.h, p1\/m, z1.h, z8.h
-.*:	65048882 	bfmaxnm	z2.h, p2\/m, z2.h, z4.h
-.*:	65049044 	bfmaxnm	z4.h, p4\/m, z4.h, z2.h
-.*:	65049828 	bfmaxnm	z8.h, p6\/m, z8.h, z1.h
-.*:	65049c10 	bfmaxnm	z16.h, p7\/m, z16.h, z0.h
-.*:	65078200 	bfmin	z0.h, p0\/m, z0.h, z16.h
-.*:	65078501 	bfmin	z1.h, p1\/m, z1.h, z8.h
-.*:	65078882 	bfmin	z2.h, p2\/m, z2.h, z4.h
-.*:	65079044 	bfmin	z4.h, p4\/m, z4.h, z2.h
-.*:	65079828 	bfmin	z8.h, p6\/m, z8.h, z1.h
-.*:	65079c10 	bfmin	z16.h, p7\/m, z16.h, z0.h
-.*:	65058200 	bfminnm	z0.h, p0\/m, z0.h, z16.h
-.*:	65058501 	bfminnm	z1.h, p1\/m, z1.h, z8.h
-.*:	65058882 	bfminnm	z2.h, p2\/m, z2.h, z4.h
-.*:	65059044 	bfminnm	z4.h, p4\/m, z4.h, z2.h
-.*:	65059828 	bfminnm	z8.h, p6\/m, z8.h, z1.h
-.*:	65059c10 	bfminnm	z16.h, p7\/m, z16.h, z0.h
-.*:	65100080 	bfadd	z0.h, z4.h, z16.h
-.*:	65080101 	bfadd	z1.h, z8.h, z8.h
-.*:	65040182 	bfadd	z2.h, z12.h, z4.h
-.*:	65020204 	bfadd	z4.h, z16.h, z2.h
-.*:	65010288 	bfadd	z8.h, z20.h, z1.h
-.*:	65000310 	bfadd	z16.h, z24.h, z0.h
-.*:	64302480 	bfclamp	z0.h, z4.h, z16.h
-.*:	64282501 	bfclamp	z1.h, z8.h, z8.h
-.*:	64242582 	bfclamp	z2.h, z12.h, z4.h
-.*:	64222604 	bfclamp	z4.h, z16.h, z2.h
-.*:	64212688 	bfclamp	z8.h, z20.h, z1.h
-.*:	64202710 	bfclamp	z16.h, z24.h, z0.h
-.*:	65300000 	bfmla	z0.h, p0\/m, z0.h, z16.h
-.*:	65280421 	bfmla	z1.h, p1\/m, z1.h, z8.h
-.*:	65240842 	bfmla	z2.h, p2\/m, z2.h, z4.h
-.*:	65221084 	bfmla	z4.h, p4\/m, z4.h, z2.h
-.*:	65211908 	bfmla	z8.h, p6\/m, z8.h, z1.h
-.*:	65201e10 	bfmla	z16.h, p7\/m, z16.h, z0.h
-.*:	643e0a00 	bfmla	z0.h, z16.h, z6.h\[7\]
-.*:	643d0901 	bfmla	z1.h, z8.h, z5.h\[7\]
-.*:	643409c2 	bfmla	z2.h, z14.h, z4.h\[5\]
-.*:	642a0aa4 	bfmla	z4.h, z21.h, z2.h\[3\]
-.*:	64210988 	bfmla	z8.h, z12.h, z1.h\[1\]
-.*:	64200950 	bfmla	z16.h, z10.h, z0.h\[1\]
-.*:	65302000 	bfmls	z0.h, p0\/m, z0.h, z16.h
-.*:	65282421 	bfmls	z1.h, p1\/m, z1.h, z8.h
-.*:	65242842 	bfmls	z2.h, p2\/m, z2.h, z4.h
-.*:	65223084 	bfmls	z4.h, p4\/m, z4.h, z2.h
-.*:	65213908 	bfmls	z8.h, p6\/m, z8.h, z1.h
-.*:	65203e10 	bfmls	z16.h, p7\/m, z16.h, z0.h
-.*:	643e0e00 	bfmls	z0.h, z16.h, z6.h\[7\]
-.*:	643d0d01 	bfmls	z1.h, z8.h, z5.h\[7\]
-.*:	64340dc2 	bfmls	z2.h, z14.h, z4.h\[5\]
-.*:	642a0ea4 	bfmls	z4.h, z21.h, z2.h\[3\]
-.*:	64210d88 	bfmls	z8.h, z12.h, z1.h\[1\]
-.*:	64200d50 	bfmls	z16.h, z10.h, z0.h\[1\]
-.*:	65028200 	bfmul	z0.h, p0\/m, z0.h, z16.h
-.*:	65028501 	bfmul	z1.h, p1\/m, z1.h, z8.h
-.*:	65028882 	bfmul	z2.h, p2\/m, z2.h, z4.h
-.*:	65029044 	bfmul	z4.h, p4\/m, z4.h, z2.h
-.*:	65029828 	bfmul	z8.h, p6\/m, z8.h, z1.h
-.*:	65029c10 	bfmul	z16.h, p7\/m, z16.h, z0.h
-.*:	65100880 	bfmul	z0.h, z4.h, z16.h
-.*:	65080901 	bfmul	z1.h, z8.h, z8.h
-.*:	65040982 	bfmul	z2.h, z12.h, z4.h
-.*:	65020a04 	bfmul	z4.h, z16.h, z2.h
-.*:	65010a88 	bfmul	z8.h, z20.h, z1.h
-.*:	65000b10 	bfmul	z16.h, z24.h, z0.h
-.*:	643e2a00 	bfmul	z0.h, z16.h, z6.h\[7\]
-.*:	643d2901 	bfmul	z1.h, z8.h, z5.h\[7\]
-.*:	643429c2 	bfmul	z2.h, z14.h, z4.h\[5\]
-.*:	642a2aa4 	bfmul	z4.h, z21.h, z2.h\[3\]
-.*:	64212988 	bfmul	z8.h, z12.h, z1.h\[1\]
-.*:	64202950 	bfmul	z16.h, z10.h, z0.h\[1\]
-.*:	65018200 	bfsub	z0.h, p0\/m, z0.h, z16.h
-.*:	65018501 	bfsub	z1.h, p1\/m, z1.h, z8.h
-.*:	65018882 	bfsub	z2.h, p2\/m, z2.h, z4.h
-.*:	65019044 	bfsub	z4.h, p4\/m, z4.h, z2.h
-.*:	65019828 	bfsub	z8.h, p6\/m, z8.h, z1.h
-.*:	65019c10 	bfsub	z16.h, p7\/m, z16.h, z0.h
-.*:	65100480 	bfsub	z0.h, z4.h, z16.h
-.*:	65080501 	bfsub	z1.h, z8.h, z8.h
-.*:	65040582 	bfsub	z2.h, z12.h, z4.h
-.*:	65020604 	bfsub	z4.h, z16.h, z2.h
-.*:	65010688 	bfsub	z8.h, z20.h, z1.h
-.*:	65000710 	bfsub	z16.h, z24.h, z0.h
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/bfloat16-1.s
deleted file mode 100644
index 5597d9ef01906f7316149cdf0bb69addeb849926..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-1.s
+++ /dev/null
@@ -1,112 +0,0 @@ 
-bfadd z0.h, p0/m, z0.h, z16.h
-bfadd z1.h, p1/m, z1.h, z8.h
-bfadd z2.h, p2/m, z2.h, z4.h
-bfadd z4.h, p4/m, z4.h, z2.h
-bfadd z8.h, p6/m, z8.h, z1.h
-bfadd z16.h, p7/m, z16.h, z0.h
-
-bfmax z0.h, p0/m, z0.h, z16.h
-bfmax z1.h, p1/m, z1.h, z8.h
-bfmax z2.h, p2/m, z2.h, z4.h
-bfmax z4.h, p4/m, z4.h, z2.h
-bfmax z8.h, p6/m, z8.h, z1.h
-bfmax z16.h, p7/m, z16.h, z0.h
-
-bfmaxnm z0.h, p0/m, z0.h, z16.h
-bfmaxnm z1.h, p1/m, z1.h, z8.h
-bfmaxnm z2.h, p2/m, z2.h, z4.h
-bfmaxnm z4.h, p4/m, z4.h, z2.h
-bfmaxnm z8.h, p6/m, z8.h, z1.h
-bfmaxnm z16.h, p7/m, z16.h, z0.h
-
-bfmin z0.h, p0/m, z0.h, z16.h
-bfmin z1.h, p1/m, z1.h, z8.h
-bfmin z2.h, p2/m, z2.h, z4.h
-bfmin z4.h, p4/m, z4.h, z2.h
-bfmin z8.h, p6/m, z8.h, z1.h
-bfmin z16.h, p7/m, z16.h, z0.h
-
-bfminnm z0.h, p0/m, z0.h, z16.h
-bfminnm z1.h, p1/m, z1.h, z8.h
-bfminnm z2.h, p2/m, z2.h, z4.h
-bfminnm z4.h, p4/m, z4.h, z2.h
-bfminnm z8.h, p6/m, z8.h, z1.h
-bfminnm z16.h, p7/m, z16.h, z0.h
-
-bfadd z0.h, z4.h, z16.h
-bfadd z1.h, z8.h, z8.h
-bfadd z2.h, z12.h, z4.h
-bfadd z4.h, z16.h, z2.h
-bfadd z8.h, z20.h, z1.h
-bfadd z16.h, z24.h, z0.h
-
-bfclamp z0.h, z4.h, z16.h
-bfclamp z1.h, z8.h, z8.h
-bfclamp z2.h, z12.h, z4.h
-bfclamp z4.h, z16.h, z2.h
-bfclamp z8.h, z20.h, z1.h
-bfclamp z16.h, z24.h, z0.h
-bfmla z0.h, p0/m, z0.h, z16.h
-bfmla z1.h, p1/m, z1.h, z8.h
-bfmla z2.h, p2/m, z2.h, z4.h
-bfmla z4.h, p4/m, z4.h, z2.h
-bfmla z8.h, p6/m, z8.h, z1.h
-bfmla z16.h, p7/m, z16.h, z0.h
-
-bfmla z0.h, z16.h, z6.h[7]
-bfmla z1.h, z8.h, z5.h[6]
-bfmla z2.h, z14.h, z4.h[4]
-bfmla z4.h, z21.h, z2.h[2]
-bfmla z8.h, z12.h, z1.h[1]
-bfmla z16.h, z10.h, z0.h[0]
-
-bfmls z0.h, p0/m, z0.h, z16.h
-bfmls z1.h, p1/m, z1.h, z8.h
-bfmls z2.h, p2/m, z2.h, z4.h
-bfmls z4.h, p4/m, z4.h, z2.h
-bfmls z8.h, p6/m, z8.h, z1.h
-bfmls z16.h, p7/m, z16.h, z0.h
-
-bfmls z0.h, z16.h, z6.h[7]
-bfmls z1.h, z8.h, z5.h[6]
-bfmls z2.h, z14.h, z4.h[4]
-bfmls z4.h, z21.h, z2.h[2]
-bfmls z8.h, z12.h, z1.h[1]
-bfmls z16.h, z10.h, z0.h[0]
-
-bfmul z0.h, p0/m, z0.h, z16.h
-bfmul z1.h, p1/m, z1.h, z8.h
-bfmul z2.h, p2/m, z2.h, z4.h
-bfmul z4.h, p4/m, z4.h, z2.h
-bfmul z8.h, p6/m, z8.h, z1.h
-bfmul z16.h, p7/m, z16.h, z0.h
-
-bfmul z0.h, z4.h, z16.h
-bfmul z1.h, z8.h, z8.h
-bfmul z2.h, z12.h, z4.h
-bfmul z4.h, z16.h, z2.h
-bfmul z8.h, z20.h, z1.h
-bfmul z16.h, z24.h, z0.h
-
-bfmul z0.h, z16.h, z6.h[7]
-bfmul z1.h, z8.h, z5.h[6]
-bfmul z2.h, z14.h, z4.h[4]
-bfmul z4.h, z21.h, z2.h[2]
-bfmul z8.h, z12.h, z1.h[1]
-bfmul z16.h, z10.h, z0.h[0]
-
-bfsub z0.h, p0/m, z0.h, z16.h
-bfsub z1.h, p1/m, z1.h, z8.h
-bfsub z2.h, p2/m, z2.h, z4.h
-bfsub z4.h, p4/m, z4.h, z2.h
-bfsub z8.h, p6/m, z8.h, z1.h
-bfsub z16.h, p7/m, z16.h, z0.h
-
-bfsub z0.h, z4.h, z16.h
-bfsub z1.h, z8.h, z8.h
-bfsub z2.h, z12.h, z4.h
-bfsub z4.h, z16.h, z2.h
-bfsub z8.h, z20.h, z1.h
-bfsub z16.h, z24.h, z0.h
-
-
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.d b/gas/testsuite/gas/aarch64/bfloat16-bad.d
deleted file mode 100644
index 10d2b001c1a39851ab020e20997f2774663dc3ba..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.d
+++ /dev/null
@@ -1,4 +0,0 @@ 
-#name: Negative test of Bfloat16 instructions.
-#as: -march=armv9.4-a
-#source: bfloat16-1.s
-#error_output: bfloat16-bad.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l
deleted file mode 100644
index 5a5192b329cd250914c860de5331ef3952ef846b..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.l
+++ /dev/null
@@ -1,97 +0,0 @@ 
-.*: Assembler messages:
-.*: Error: selected processor does not support `bfadd z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfadd z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfadd z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfadd z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfadd z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfadd z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmax z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmax z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmax z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmax z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmax z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmax z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmaxnm z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmaxnm z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmaxnm z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmaxnm z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmaxnm z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmaxnm z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmin z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmin z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmin z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmin z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmin z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmin z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfminnm z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfminnm z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfminnm z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfminnm z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfminnm z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfminnm z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfadd z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfadd z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfadd z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfadd z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfadd z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfadd z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfclamp z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfclamp z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfclamp z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfclamp z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfclamp z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfclamp z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmla z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmla z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmla z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmla z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmla z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmla z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmla z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmla z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmla z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmla z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmla z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmla z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmls z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmls z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmls z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmls z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmls z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmls z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmls z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmls z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmls z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmls z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmls z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmls z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmul z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmul z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmul z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmul z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmul z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmul z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmul z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfmul z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfmul z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfmul z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfmul z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfmul z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmul z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmul z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmul z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmul z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmul z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmul z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfsub z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfsub z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfsub z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfsub z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfsub z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfsub z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfsub z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfsub z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfsub z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2e7485f25adfc7001630b50d173bd7ff77b587a6..cebeb5a5fda1eaffd74e8759295023ce0a6d4e2c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -220,8 +220,6 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_PMUv3_ICNTR,
   /* Performance Monitors Synchronous-Exception-Based Event Extension.  */
   AARCH64_FEATURE_SEBEP,
-  /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
-  AARCH64_FEATURE_B16B16,
   /* RCPC3 instructions.  */
   AARCH64_FEATURE_RCPC3,
   AARCH64_NUM_FEATURES
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1c9fa61c8f89b32ed1deb1db33cb1b55206dd3a3..a7556a48f45292898705ca87f8df814b41c5fcfc 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2641,8 +2641,6 @@  static const aarch64_feature_set aarch64_feature_the =
   AARCH64_FEATURE (THE);
 static const aarch64_feature_set aarch64_feature_d128_the =
   AARCH64_FEATURES (2, D128, THE);
-static const aarch64_feature_set aarch64_feature_b16b16 =
-  AARCH64_FEATURE (B16B16);
 static const aarch64_feature_set aarch64_feature_rcpc3 =
   AARCH64_FEATURE (RCPC3);
 
@@ -2708,7 +2706,6 @@  static const aarch64_feature_set aarch64_feature_rcpc3 =
 #define D128	  &aarch64_feature_d128
 #define THE	  &aarch64_feature_the
 #define D128_THE  &aarch64_feature_d128_the
-#define B16B16  &aarch64_feature_b16b16
 #define RCPC3	  &aarch64_feature_rcpc3
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2779,12 +2776,6 @@  static const aarch64_feature_set aarch64_feature_rcpc3 =
 #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
-    FLAGS | F_STRICT, 0, TIED, NULL }
-#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
-    FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
 #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
@@ -6315,24 +6306,6 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   D128_THE_INSN("rcwsswppal", 0x59e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
   D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
 
-/* BFloat16 SVE Instructions.  */
-  B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
-  B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
-  B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
-
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };