diff mbox series

x86: rename SPACE_{,E}VEX_MAP<N>

Message ID aa290d5e-5204-49ca-ab47-a4c61a5f1cb1@suse.com
State New
Headers
Series x86: rename SPACE_{,E}VEX_MAP<N> |

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Commit Message

Jan Beulich Nov. 15, 2024, 12:38 p.m. UTC 
  Map7 already has dual purpose for USER-MSR (and is to gain more for
MSR-IMM), while Map5 is about to gain VEX uses for AMX extensions. Drop
the not really meaningful infixes and (in the opcode table) prefixes,
retaining merely EVexMap4 for encoding EVex128 at the same time.

Comments

Hu, Lin1 Nov. 18, 2024, 1:45 a.m. UTC | #1 
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, November 15, 2024 8:39 PM
> To: Binutils <binutils@sourceware.org>
> Cc: H.J. Lu <hjl.tools@gmail.com>; Hu, Lin1 <lin1.hu@intel.com>; Jiang,
> Haochen <haochen.jiang@intel.com>
> Subject: [PATCH] x86: rename SPACE_{,E}VEX_MAP<N>
> 
> Map7 already has dual purpose for USER-MSR (and is to gain more for MSR-
> IMM), while Map5 is about to gain VEX uses for AMX extensions. Drop the not
> really meaningful infixes and (in the opcode table) prefixes, retaining merely
> EVexMap4 for encoding EVex128 at the same time.
>

I think it's good to unify the changes, it seems fine to me, and my related patches (like MSR_IMM) will be reissued based on this patch rebase of yours.

BRs,
Lin
 
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -4211,7 +4211,7 @@ build_vex_prefix (const insn_template *t
>  	case SPACE_0F:
>  	case SPACE_0F38:
>  	case SPACE_0F3A:
> -	case SPACE_VEXMAP7:
> +	case SPACE_MAP7:
>  	  i.vex.bytes[0] = 0xc4;
>  	  break;
>  	case SPACE_XOP08:
> @@ -4246,7 +4246,7 @@ is_any_vex_encoding (const insn_template  static
> INLINE bool  is_apx_evex_encoding (void)  {
> -  return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 || pp.has_nf
> +  return i.rex2 || i.tm.opcode_space == SPACE_MAP4 || pp.has_nf
>      || (i.vex.register_specifier
>  	&& (i.vex.register_specifier->reg_flags & RegRex2));  } @@ -4370,7
> +4370,7 @@ build_evex_prefix (void)
>    /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
>       bits from REX.  */
>    gas_assert (i.tm.opcode_space >= SPACE_0F);
> -  gas_assert (i.tm.opcode_space <= SPACE_VEXMAP7);
> +  gas_assert (i.tm.opcode_space <= SPACE_MAP7);
>    i.vex.bytes[1] = ((~i.rex & 7) << 5)
>  		   | (!dot_insn () ? i.tm.opcode_space
>  				   : i.insn_opcode_space);
> @@ -4543,7 +4543,7 @@ build_apx_evex_prefix (void)  {
>    /* To mimic behavior for legacy insns, transform use of DATA16 and REX64
> into
>       their embedded-prefix representations.  */
> -  if (i.tm.opcode_space == SPACE_EVEXMAP4)
> +  if (i.tm.opcode_space == SPACE_MAP4)
>      {
>        if (i.prefix[DATA_PREFIX])
>  	{
> @@ -4585,7 +4585,7 @@ build_apx_evex_prefix (void)
> 
>    /* Encode the NDD bit of the instruction promoted from the legacy
>       space. ZU shares the same bit with NDD.  */
> -  if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
> +  if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_MAP4)
>        || i.tm.opcode_modifier.operandconstraint == ZERO_UPPER)
>      i.vex.bytes[3] |= 0x10;
> 
> @@ -4965,7 +4965,7 @@ optimize_encoding (void)
>    if (optimize_for_space
>        && (i.tm.mnem_off == MN_test
>            || (i.tm.base_opcode == 0xf6
> -              && i.tm.opcode_space == SPACE_EVEXMAP4))
> +              && i.tm.opcode_space == SPACE_MAP4))
>        && i.reg_operands == 1
>        && i.imm_operands == 1
>        && !i.types[1].bitfield.byte
> @@ -5133,7 +5133,7 @@ optimize_encoding (void)
>  	   && i.tm.base_opcode == 0xd0
>  	   && i.tm.extension_opcode == 4
>  	   && (i.tm.opcode_space == SPACE_BASE
> -	       || i.tm.opcode_space == SPACE_EVEXMAP4)
> +	       || i.tm.opcode_space == SPACE_MAP4)
>  	   && !i.mem_operands)
>      {
>        /* Optimize: -O:
> @@ -5198,7 +5198,7 @@ optimize_encoding (void)
>      }
>    else if (optimize > 1
>  	   && (i.tm.base_opcode | 0xf) == 0x4f
> -	   && i.tm.opcode_space == SPACE_EVEXMAP4
> +	   && i.tm.opcode_space == SPACE_MAP4
>  	   && i.reg_operands == 3
>  	   && i.tm.opcode_modifier.operandconstraint == EVEX_NF
>  	   && !i.types[0].bitfield.word)
> @@ -6536,7 +6536,7 @@ static INLINE bool may_need_pass2 (const
>  	   || (t->opcode_space == SPACE_BASE
>  	       && t->base_opcode == 0x63)
>  	   || (intel_syntax /* shld / shrd may mean suffixed shl / shr.  */
> -	       && t->opcode_space == SPACE_EVEXMAP4
> +	       && t->opcode_space == SPACE_MAP4
>  	       && (t->base_opcode | 8) == 0x2c);  }
> 
> @@ -7248,7 +7248,7 @@ i386_assemble (char *line)
>      }
>  #endif
> 
> -  if ((is_any_vex_encoding (&i.tm) && i.tm.opcode_space != SPACE_EVEXMAP4)
> +  if ((is_any_vex_encoding (&i.tm) && i.tm.opcode_space != SPACE_MAP4)
>        || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX
>        || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)
>      {
> @@ -7405,7 +7405,7 @@ i386_assemble (char *line)
> 
>        /* Check for explicit REX prefix.  */
>        if ((i.prefix[REX_PREFIX]
> -	   && (i.tm.opcode_space != SPACE_EVEXMAP4
> +	   && (i.tm.opcode_space != SPACE_MAP4
>  	       /* To mimic behavior for legacy insns, permit use of REX64 for
> promoted
>  		  legacy instructions.  */
>  	       || i.prefix[REX_PREFIX] != (REX_OPCODE | REX_W))) @@ -9325,7
> +9325,7 @@ match_template (char mnem_suffix)
>  	     - the non-default (swapped) form is requested.  */
>  	  overlap1 = operand_type_and (operand_types[0], operand_types[1]);
> 
> -	  j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4
> +	  j = i.operands - 1 - (t->opcode_space == SPACE_MAP4
>  				&& t->opcode_modifier.vexvvvv);
> 
>  	  if (t->opcode_modifier.d && i.reg_operands == i.operands @@ -
> 9421,7 +9421,7 @@ match_template (char mnem_suffix)
>  		  found_reverse_match = Opcode_VexW;
>  		  goto check_operands_345;
>  		}
> -	      else if (t->opcode_space == SPACE_EVEXMAP4
> +	      else if (t->opcode_space == SPACE_MAP4
>  		       && t->operands >= 3)
>  		{
>  		  found_reverse_match = Opcode_D;
> @@ -9429,11 +9429,11 @@ match_template (char mnem_suffix)
>  		}
>  	      else if (t->opcode_modifier.commutative
>  		       /* CFCMOVcc also wants its major opcode unaltered.  */
> -		       || (t->opcode_space == SPACE_EVEXMAP4
> +		       || (t->opcode_space == SPACE_MAP4
>  			   && (t->base_opcode | 0xf) == 0x4f))
>  		found_reverse_match = ~0;
>  	      else if (t->opcode_space != SPACE_BASE
> -		       && (t->opcode_space != SPACE_EVEXMAP4
> +		       && (t->opcode_space != SPACE_MAP4
>  			   /* MOVBE, originating from SPACE_0F38, also
>  			      belongs here.  */
>  			   || t->mnem_off == MN_movbe)
> @@ -9692,7 +9692,7 @@ match_template (char mnem_suffix)
> 
>    /* APX insns acting on byte operands are WIG, yet that can't be expressed
>       in the templates (they're also covering word/dword/qword operands).  */
> -  if (t->opcode_space == SPACE_EVEXMAP4 && !t->opcode_modifier.vexw &&
> +  if (t->opcode_space == SPACE_MAP4 && !t->opcode_modifier.vexw &&
>        i.types[i.operands - 1].bitfield.byte)
>      {
>        gas_assert (t->opcode_modifier.w); @@ -9717,7 +9717,7 @@
> match_template (char mnem_suffix)
> 
>        i.tm.base_opcode ^= found_reverse_match;
> 
> -      if (i.tm.opcode_space == SPACE_EVEXMAP4)
> +      if (i.tm.opcode_space == SPACE_MAP4)
>  	goto swap_first_2;
> 
>        /* Certain SIMD insns have their load forms specified in the opcode @@ -
> 9730,7 +9730,7 @@ match_template (char mnem_suffix)
> 
>        /* Fall through.  */
>      case ~0:
> -      if (i.tm.opcode_space == SPACE_EVEXMAP4
> +      if (i.tm.opcode_space == SPACE_MAP4
>  	  && !t->opcode_modifier.commutative)
>  	i.tm.opcode_modifier.operandconstraint = EVEX_NF;
>        i.tm.operand_types[0] = operand_types[i.operands - 1]; @@ -10170,7
> +10170,7 @@ process_suffix (const insn_template *t)
>        if (i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
>  	  && !i.tm.opcode_modifier.floatmf
>  	  && (!is_any_vex_encoding (&i.tm)
> -	      || i.tm.opcode_space == SPACE_EVEXMAP4)
> +	      || i.tm.opcode_space == SPACE_MAP4)
>  	  && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
>  	      || (flag_code == CODE_64BIT
>  		  && i.tm.opcode_modifier.jump == JUMP_BYTE))) @@ -
> 10182,7 +10182,7 @@ process_suffix (const insn_template *t)
> 
>  	  /* The DATA PREFIX of EVEX promoted from legacy APX instructions
>  	     needs to be adjusted.  */
> -	  if (i.tm.opcode_space == SPACE_EVEXMAP4)
> +	  if (i.tm.opcode_space == SPACE_MAP4)
>  	    {
>  	      gas_assert (!i.tm.opcode_modifier.opcodeprefix);
>  	      i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; @@ -12752,7
> +12752,7 @@ output_disp (fragS *insn_start_frag, off
>  		fixP->fx_signed = 1;
> 
>  	      if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF
> -		  && i.tm.opcode_space == SPACE_EVEXMAP4)
> +		  && i.tm.opcode_space == SPACE_MAP4)
>  		{
>  		  /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is
>  		     allowed in md_assemble.  Set fx_tcbit2 for EVEX
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -1139,10 +1139,10 @@ process_i386_opcode_modifier (FILE *tabl
>      SPACE(0F),
>      SPACE(0F38),
>      SPACE(0F3A),
> -    SPACE(EVEXMAP4),
> -    SPACE(EVEXMAP5),
> -    SPACE(EVEXMAP6),
> -    SPACE(VEXMAP7),
> +    SPACE(MAP4),
> +    SPACE(MAP5),
> +    SPACE(MAP6),
> +    SPACE(MAP7),
>      SPACE(XOP08),
>      SPACE(XOP09),
>      SPACE(XOP0A),
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -987,15 +987,15 @@ typedef struct insn_template
>    /* opcode space */
>    unsigned int opcode_space:4;
>    /* Opcode encoding space (values chosen to be usable directly in
> -     VEX/XOP mmmmm and EVEX mm fields):
> +     VEX/XOP mmmmm and EVEX mmm fields):
>       0: Base opcode space.
>       1: 0F opcode prefix / space.
>       2: 0F38 opcode prefix / space.
>       3: 0F3A opcode prefix / space.
> -     4: EVEXMAP4 opcode prefix / space.
> -     5: EVEXMAP5 opcode prefix / space.
> -     6: EVEXMAP6 opcode prefix / space.
> -     7: VEXMAP7 opcode prefix / space.
> +     4: MAP4 opcode prefix / space.
> +     5: MAP5 opcode prefix / space.
> +     6: MAP6 opcode prefix / space.
> +     7: MAP7 opcode prefix / space.
>       8: XOP 08 opcode space.
>       9: XOP 09 opcode space.
>       A: XOP 0A opcode space.
> @@ -1004,10 +1004,10 @@ typedef struct insn_template
>  #define SPACE_0F	1
>  #define SPACE_0F38	2
>  #define SPACE_0F3A	3
> -#define SPACE_EVEXMAP4	4
> -#define SPACE_EVEXMAP5	5
> -#define SPACE_EVEXMAP6	6
> -#define SPACE_VEXMAP7	7
> +#define SPACE_MAP4	4
> +#define SPACE_MAP5	5
> +#define SPACE_MAP6	6
> +#define SPACE_MAP7	7
>  #define SPACE_XOP08	8
>  #define SPACE_XOP09	9
>  #define SPACE_XOP0A	0xA
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -116,11 +116,11 @@
>  #define SpaceXOP09 OpcodeSpace=SPACE_XOP09  #define SpaceXOP0A
> OpcodeSpace=SPACE_XOP0A
> 
> -#define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4|EVex128
> -#define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 -#define EVexMap6
> OpcodeSpace=SPACE_EVEXMAP6
> +#define EVexMap4 OpcodeSpace=SPACE_MAP4|EVex128
> 
> -#define VexMap7 OpcodeSpace=SPACE_VEXMAP7
> +#define Map5 OpcodeSpace=SPACE_MAP5
> +#define Map6 OpcodeSpace=SPACE_MAP6
> +#define Map7 OpcodeSpace=SPACE_MAP7
> 
>  #define VexW0 VexW=VEXW0
>  #define VexW1 VexW=VEXW1
> @@ -1933,7 +1933,7 @@ vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Spa
> <sdh:cpu:cpudq:fma:ppfx:spfx:pfx:spc1:spc2:opc:vex:vexlig:vexw:elem, +
> 
> s:AVX512F:AVX512DQ:FMA|AVX512F::f3:66:Space0F:Space0F38:0:Vex|EVexDYN
> :VexLIG|EVexLIG:VexW0:Dword, +
> 
> d:AVX512F:AVX512DQ:FMA|AVX512F:66:f2:66:Space0F:Space0F38:1:Vex|EVexD
> YN:VexLIG|EVexLIG:VexW1:Qword, +
> -
> h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::EVexMap5:EVexMap6:0::EVexL
> IG:VexW0:Word>
> +
> +
> h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::Map5:Map6:0::EVexLIG:VexW
> 0:
> + Word>
> 
>  v<fm><fma>p<sdh>, 0x66<fm:opc3> | 0x<fma:opc>, <sdh:fma>,
> Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp
> 8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> v<fm><fma>s<sdh>, 0x66<fm:opc3> | 1 | 0x<fma:opc>, <sdh:fma>,
> Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemSh
> ift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex,
> RegXMM, RegXMM } @@ -3251,17 +3251,17 @@ hreset, 0xf30f3af0c0, HRESET,
> NoSuf, { I
> 
>  // FP16 (HFNI) instructions.
> 
> -vfcmaddcph, 0xf256, AVX512_FP16,
> Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|Check
> OperandSize|DistinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmaddcsh,
> 0xf257, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|Dis
> tinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vfcmaddcph, 0xf256, AVX512_FP16,
> +Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOpe
> randSi
> +ze|DistinctDest|NoSuf|StaticRounding|SAE, {
> +RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM,
> +RegXMM|RegYMM|RegZMM } vfcmaddcsh, 0xf257, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|Distinc
> tDest|
> +NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex,
> RegXMM,
> +RegXMM }
> 
> -vfmaddcph, 0xf356, AVX512_FP16,
> Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|Check
> OperandSize|DistinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmaddcsh,
> 0xf357, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|Dis
> tinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vfmaddcph, 0xf356, AVX512_FP16,
> +Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOpe
> randSi
> +ze|DistinctDest|NoSuf|StaticRounding|SAE, {
> +RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM,
> +RegXMM|RegYMM|RegZMM } vfmaddcsh, 0xf357, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|Distinc
> tDest|
> +NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex,
> RegXMM,
> +RegXMM }
> 
> -vfcmulcph, 0xf2d6, AVX512_FP16,
> Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|Check
> OperandSize|DistinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmulcsh,
> 0xf2d7, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|Dis
> tinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vfcmulcph, 0xf2d6, AVX512_FP16,
> +Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOpe
> randSi
> +ze|DistinctDest|NoSuf|StaticRounding|SAE, {
> +RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM,
> +RegXMM|RegYMM|RegZMM } vfcmulcsh, 0xf2d7, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|Distinc
> tDest|
> +NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex,
> RegXMM,
> +RegXMM }
> 
> -vfmulcph, 0xf3d6, AVX512_FP16,
> Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|Check
> OperandSize|DistinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmulcsh, 0xf3d7,
> AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|Dis
> tinctDest|NoSuf|StaticRounding|SAE,
> { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vfmulcph, 0xf3d6, AVX512_FP16,
> +Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOpe
> randSi
> +ze|DistinctDest|NoSuf|StaticRounding|SAE, {
> +RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM,
> +RegXMM|RegYMM|RegZMM } vfmulcsh, 0xf3d7, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|Distinc
> tDest|
> +NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex,
> RegXMM,
> +RegXMM }
> 
>  vcmp<frel>ph, 0xc2/0x<frel:imm>, AVX512_FP16,
> Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|Check
> OperandSize|NoSuf|ImmExt|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegMask }  vcmpph, 0xc2, AVX512_FP16,
> Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|Check
> OperandSize|NoSuf|SAE, { Imm8,
> RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegMask } @@ -3269,93 +3269,93 @@ vcmpph,
> 0xc2, AVX512_FP16, Modrm|Masking  vcmp<frel>sh, 0xf3c2/0x<frel:imm>,
> AVX512_FP16,
> Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|No
> Suf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM,
> RegMask }  vcmpsh, 0xf3c2, AVX512_FP16,
> Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|No
> Suf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
> 
> -vcvtdq2ph<Exy>, 0x5b, AVX512_FP16&<Exy:vl>,
> Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>,
> { <Exy:src>|Dword, <Exy:dst> } -vcvtudq2ph<Exy>, 0xf27a,
> AVX512_FP16&<Exy:vl>,
> Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>,
> { <Exy:src>|Dword, <Exy:dst> }
> +vcvtdq2ph<Exy>, 0x5b, AVX512_FP16&<Exy:vl>,
> +Modrm|<Exy:attr>|Masking|Map5|VexW0|Broadcast|NoSuf|<Exy:sr>, {
> +<Exy:src>|Dword, <Exy:dst> } vcvtudq2ph<Exy>, 0xf27a,
> +AVX512_FP16&<Exy:vl>,
> +Modrm|<Exy:attr>|Masking|Map5|VexW0|Broadcast|NoSuf|<Exy:sr>, {
> +<Exy:src>|Dword, <Exy:dst> }
> 
> -vcvtqq2ph<xyz>, 0x5b, AVX512_FP16&<xyz:vl>,
> Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xy
> z:att>, { <xyz:src>|Qword, RegXMM } -vcvtuqq2ph<xyz>, 0xf27a,
> AVX512_FP16&<xyz:vl>,
> Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xy
> z:att>, { <xyz:src>|Qword, RegXMM }
> +vcvtqq2ph<xyz>, 0x5b, AVX512_FP16&<xyz:vl>,
> +Modrm|<xyz:attr>|Masking|Map5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:at
> t>,
> +{ <xyz:src>|Qword, RegXMM } vcvtuqq2ph<xyz>, 0xf27a,
> +AVX512_FP16&<xyz:vl>,
> +Modrm|<xyz:attr>|Masking|Map5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:at
> t>,
> +{ <xyz:src>|Qword, RegXMM }
> 
> -vcvtpd2ph<xyz>, 0x665a, AVX512_FP16&<xyz:vl>,
> Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xy
> z:att>, { <xyz:src>|Qword, RegXMM }
> +vcvtpd2ph<xyz>, 0x665a, AVX512_FP16&<xyz:vl>,
> +Modrm|<xyz:attr>|Masking|Map5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:at
> t>,
> +{ <xyz:src>|Qword, RegXMM }
> 
> -vcvtps2phx<Exy>, 0x661d, AVX512_FP16&<Exy:vl>,
> Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>,
> { <Exy:src>|Dword, <Exy:dst> }
> +vcvtps2phx<Exy>, 0x661d, AVX512_FP16&<Exy:vl>,
> +Modrm|<Exy:attr>|Masking|Map5|VexW0|Broadcast|NoSuf|<Exy:sr>, {
> +<Exy:src>|Dword, <Exy:dst> }
> 
> -vcvtw2ph, 0xf37d, AVX512_FP16,
> Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM } -vcvtuw2ph, 0xf27d, AVX512_FP16,
> Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM }
> +vcvtw2ph, 0xf37d, AVX512_FP16,
> +Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf|
> +StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> +RegXMM|RegYMM|RegZMM } vcvtuw2ph, 0xf27d, AVX512_FP16,
> +Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf|
> +StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> +RegXMM|RegYMM|RegZMM }
> 
> -vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2dq,
> 0x665b, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
> -vcvtph2dq, 0x665b, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|N
> oSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf,
> {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } vcvtph2dq, 0x665b,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |Static
> +Rounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
> vcvtph2dq,
> +0x665b, AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf
> |Static
> +Rounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvtph2udq, 0x79, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2udq,
> 0x79, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
> -vcvtph2udq, 0x79, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|N
> oSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvtph2udq, 0x79, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf,
> {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } vcvtph2udq, 0x79,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |Static
> +Rounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
> vcvtph2udq,
> +0x79, AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf
> |Static
> +Rounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|N
> oSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2qq,
> 0x667b, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex,
> RegYMM } -vcvtph2qq, 0x667b, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf,
> {
> +RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } vcvtph2qq, 0x667b,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf
> |Static
> +Rounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
> +vcvtph2qq, 0x667b, AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |Static
> +Rounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|N
> oSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2uqq,
> 0x6679, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex,
> RegYMM } -vcvtph2uqq, 0x6679, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf,
> {
> +RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } vcvtph2uqq,
> 0x6679,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf
> |Static
> +Rounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
> +vcvtph2uqq, 0x6679, AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |Static
> +Rounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|N
> oSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2pd,
> 0x5a, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -
> vcvtph2pd, 0x5a, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf,
> {
> +RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } vcvtph2pd, 0x5a,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf
> |SAE, {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } vcvtph2pd, 0x5a,
> +AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvtph2w, 0x667d, AVX512_FP16,
> Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM } -vcvtph2uw, 0x7d, AVX512_FP16,
> Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf|StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM }
> +vcvtph2w, 0x667d, AVX512_FP16,
> +Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf|
> +StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> +RegXMM|RegYMM|RegZMM } vcvtph2uw, 0x7d, AVX512_FP16,
> +Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf|
> +StaticRounding|SAE,
> { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> +RegXMM|RegYMM|RegZMM }
> 
> -vcvtsd2sh, 0xf25a, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW1|Disp8MemShift=3|No
> Suf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM,
> RegXMM } -vcvtss2sh, 0x1d, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=2|No
> Suf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM,
> RegXMM }
> +vcvtsd2sh, 0xf25a, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|
> StaticR
> +ounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vcvtss2sh, 0x1d, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|
> StaticR
> +ounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
> 
> -vcvtsi2sh, 0xf32a, AVX512_FP16,
> Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_
> wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax,
> { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sh, 0xf32a,
> AVX512_FP16,
> Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sS
> uf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex,
> RegXMM, RegXMM }
> +vcvtsi2sh, 0xf32a, AVX512_FP16,
> +Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSu
> f|No_
> +sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex,
> +RegXMM, RegXMM } vcvtsi2sh, 0xf32a, AVX512_FP16,
> +Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|
> Static
> +Rounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM,
> +RegXMM }
> 
> -vcvtusi2sh, 0xf37b, AVX512_FP16,
> Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_
> wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax,
> { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sh,
> 0xf37b, AVX512_FP16,
> Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sS
> uf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex,
> RegXMM, RegXMM }
> +vcvtusi2sh, 0xf37b, AVX512_FP16,
> +Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSu
> f|No_
> +sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex,
> +RegXMM, RegXMM } vcvtusi2sh, 0xf37b, AVX512_FP16,
> +Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|
> Static
> +Rounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM,
> +RegXMM }
> 
> -vcvtsh2sd, 0xf35a, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=1|No
> Suf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -
> vcvtsh2ss, 0x13, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|No
> Suf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vcvtsh2sd, 0xf35a, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map5|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|
> SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsh2ss, 0x13,
> +AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|
> SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> 
> -vcvtsh2si, 0xf32d, AVX512_FP16,
> Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE,
> { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
> +vcvtsh2si, 0xf32d, AVX512_FP16,
> +Modrm|EVexLIG|Map5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
> 
> -vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2dq,
> 0xf35b, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2dq,
> 0xf35b, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|N
> oSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf,
> {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } vcvttph2dq,
> 0xf35b,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegYMM } vcvttph2dq, 0xf35b,
> +AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf
> |SAE, {
> +RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvttph2udq, 0x78, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -
> vcvttph2udq, 0x78, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2udq,
> 0x78, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|N
> oSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvttph2udq, 0x78, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf,
> {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } vcvttph2udq, 0x78,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegYMM } vcvttph2udq, 0x78,
> +AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf
> |SAE, {
> +RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|N
> oSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2qq,
> 0x667a, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -
> vcvttph2qq, 0x667a, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf,
> {
> +RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } vcvttph2qq,
> 0x667a,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf
> |SAE, {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } vcvttph2qq,
> 0x667a,
> +AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|N
> oSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2uqq,
> 0x6678, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -
> vcvttph2uqq, 0x6678, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf,
> {
> +RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } vcvttph2uqq,
> 0x6678,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf
> |SAE, {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } vcvttph2uqq,
> 0x6678,
> +AVX512_FP16,
> +Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL,
> Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|N
> oSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2psx,
> 0x6613, AVX512_FP16&AVX512VL,
> Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|N
> oSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2psx,
> 0x6613, AVX512_FP16,
> Modrm|EVex512|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|N
> oSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> +vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL,
> +Modrm|EVex128|Masking|Map6|VexW0|Broadcast|Disp8MemShift=3|NoSuf,
> {
> +RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } vcvtph2psx,
> 0x6613,
> +AVX512_FP16&AVX512VL,
> +Modrm|EVex256|Masking|Map6|VexW0|Broadcast|Disp8MemShift=4|NoSuf
> |SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, RegYMM } vcvtph2psx, 0x6613,
> +AVX512_FP16,
> +Modrm|EVex512|Masking|Map6|VexW0|Broadcast|Disp8MemShift=5|NoSuf
> |SAE, {
> +RegYMM|Word|Unspecified|BaseIndex, RegZMM }
> 
> -vcvttph2w, 0x667c, AVX512_FP16,
> Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM } -vcvttph2uw, 0x7c, AVX512_FP16,
> Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM }
> +vcvttph2w, 0x667c, AVX512_FP16,
> +Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf|
> +SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> +RegXMM|RegYMM|RegZMM } vcvttph2uw, 0x7c, AVX512_FP16,
> +Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf|
> +SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> +RegXMM|RegYMM|RegZMM }
> 
> -vcvttsh2si, 0xf32c, AVX512_FP16,
> Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE,
> { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
> +vcvttsh2si, 0xf32c, AVX512_FP16,
> +Modrm|EVexLIG|Map5|Disp8MemShift=1|NoSuf|SAE, {
> +RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
> 
>  vfpclassph<xyz>, 0x66, AVX512_FP16&<xyz:vl>,
> Modrm|<xyz:attr>|Masking|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>,
> { Imm8|Imm8S, <xyz:src>|Word, RegMask }
> 
> -vmovw, 0x666e, AVX512_FP16,
> D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf,
> { Word|Unspecified|BaseIndex, RegXMM } -vmovw, 0x667e, AVX512_FP16,
> D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 }
> +vmovw, 0x666e, AVX512_FP16,
> +D|Modrm|EVex128|VexWIG|Map5|Disp8MemShift=1|NoSuf, {
> +Word|Unspecified|BaseIndex, RegXMM } vmovw, 0x667e, AVX512_FP16,
> +D|RegMem|EVex128|VexWIG|Map5|NoSuf, { RegXMM, Reg32 }
> 
> -vrcpph, 0x664c, AVX512_FP16,
> Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM }
> +vrcpph, 0x664c, AVX512_FP16,
> +Modrm|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf,
> +{ RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM
> +}
> 
> -vrcpsh, 0x664d, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|No
> Suf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrcpsh, 0x664d, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf,
> {
> +RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> 
> -vrsqrtph, 0x664e, AVX512_FP16,
> Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSiz
> e|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM }
> +vrsqrtph, 0x664e, AVX512_FP16,
> +Modrm|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|N
> oSuf,
> +{ RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM
> +}
> 
> -vrsqrtsh, 0x664f, AVX512_FP16,
> Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|No
> Suf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> +vrsqrtsh, 0x664f, AVX512_FP16,
> +Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf,
> {
> +RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
> 
>  // FP16 (HFNI) instructions end.
> 
> @@ -3412,12 +3412,12 @@ eretu, 0xf30f01ca, FRED, NoSuf, {}
> 
>  urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
> urdmsr, 0xf2f8, USER_MSR&APX_F, RegMem|EVexMap4|VexW0|NoSuf,
> { Reg64, Reg64 } -urdmsr, 0xf2f8/0, APX_F(USER_MSR),
> Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
> +urdmsr, 0xf2f8/0, APX_F(USER_MSR),
> +Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
>  uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
> uwrmsr, 0xf3f8, USER_MSR&APX_F, Modrm|EVexMap4|VexW0|NoSuf, { Reg64,
> Reg64 }  // Immediates want to be first; md_assemble() takes care of swapping
> operands  // accordingly.
> -uwrmsr, 0xf3f8/0, APX_F(USER_MSR),
> Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
> +uwrmsr, 0xf3f8/0, APX_F(USER_MSR),
> +Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
> 
>  // USER_MSR instructions end.
> 
> @@ -3441,9 +3441,9 @@ vcvt2ps2phx, 0x6667, AVX10_2, Modrm|Spac
> 
>  <cvt8:opc:spc, +
>      bf8:74:Space0F38, +
> -    bf8s:74:EVexMap5, +
> -    hf8:18:EVexMap5, +
> -    hf8s:1b:EVexMap5>
> +    bf8s:74:Map5, +
> +    hf8:18:Map5, +
> +    hf8s:1b:Map5>
> 
>  vcvtbiasph2<cvt8>, 0x<cvt8:opc>, AVX10_2,
> Modrm|<cvt8:spc>|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|Check
> OperandSize|NoSuf, { RegXMM|RegYMM|Word|Unspecified|BaseIndex,
> RegXMM|RegYMM, RegXMM }  vcvtbiasph2<cvt8>, 0x<cvt8:opc>, AVX10_2,
> Modrm|<cvt8:spc>|EVex512|Src1VVVV|VexW0|Masking|Broadcast|Disp8Mem
> Shift=6|NoSuf, { RegZMM|Word|Unspecified|BaseIndex, RegZMM, RegYMM }
> @@ -3452,8 +3452,8 @@ vcvtneph2<cvt8><Exy>, 0xf3<cvt8:opc>, AV
> 
>  <cvt8>
> 
> -vcvthf82ph, 0xf21e, AVX10_2,
> Modrm|EVexMap5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf,
> { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvthf82ph, 0xf21e,
> AVX10_2,
> Modrm|EVexMap5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf,
> { RegXMM|Unspecified|BaseIndex, RegYMM } -vcvthf82ph, 0xf21e, AVX10_2,
> Modrm|EVexMap5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf,
> { RegYMM|Unspecified|BaseIndex, RegZMM }
> +vcvthf82ph, 0xf21e, AVX10_2,
> +Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, {
> +RegXMM|Qword|Unspecified|BaseIndex, RegXMM } vcvthf82ph, 0xf21e,
> +AVX10_2, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf,
> {
> +RegXMM|Unspecified|BaseIndex, RegYMM } vcvthf82ph, 0xf21e, AVX10_2,
> +Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, {
> +RegYMM|Unspecified|BaseIndex, RegZMM }
> 
>  // AVX10.2 instructions end.
diff mbox series

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4211,7 +4211,7 @@  build_vex_prefix (const insn_template *t
 	case SPACE_0F:
 	case SPACE_0F38:
 	case SPACE_0F3A:
-	case SPACE_VEXMAP7:
+	case SPACE_MAP7:
 	  i.vex.bytes[0] = 0xc4;
 	  break;
 	case SPACE_XOP08:
@@ -4246,7 +4246,7 @@  is_any_vex_encoding (const insn_template
 static INLINE bool
 is_apx_evex_encoding (void)
 {
-  return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 || pp.has_nf
+  return i.rex2 || i.tm.opcode_space == SPACE_MAP4 || pp.has_nf
     || (i.vex.register_specifier
 	&& (i.vex.register_specifier->reg_flags & RegRex2));
 }
@@ -4370,7 +4370,7 @@  build_evex_prefix (void)
   /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
      bits from REX.  */
   gas_assert (i.tm.opcode_space >= SPACE_0F);
-  gas_assert (i.tm.opcode_space <= SPACE_VEXMAP7);
+  gas_assert (i.tm.opcode_space <= SPACE_MAP7);
   i.vex.bytes[1] = ((~i.rex & 7) << 5)
 		   | (!dot_insn () ? i.tm.opcode_space
 				   : i.insn_opcode_space);
@@ -4543,7 +4543,7 @@  build_apx_evex_prefix (void)
 {
   /* To mimic behavior for legacy insns, transform use of DATA16 and REX64 into
      their embedded-prefix representations.  */
-  if (i.tm.opcode_space == SPACE_EVEXMAP4)
+  if (i.tm.opcode_space == SPACE_MAP4)
     {
       if (i.prefix[DATA_PREFIX])
 	{
@@ -4585,7 +4585,7 @@  build_apx_evex_prefix (void)
 
   /* Encode the NDD bit of the instruction promoted from the legacy
      space. ZU shares the same bit with NDD.  */
-  if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
+  if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_MAP4)
       || i.tm.opcode_modifier.operandconstraint == ZERO_UPPER)
     i.vex.bytes[3] |= 0x10;
 
@@ -4965,7 +4965,7 @@  optimize_encoding (void)
   if (optimize_for_space
       && (i.tm.mnem_off == MN_test
           || (i.tm.base_opcode == 0xf6
-              && i.tm.opcode_space == SPACE_EVEXMAP4))
+              && i.tm.opcode_space == SPACE_MAP4))
       && i.reg_operands == 1
       && i.imm_operands == 1
       && !i.types[1].bitfield.byte
@@ -5133,7 +5133,7 @@  optimize_encoding (void)
 	   && i.tm.base_opcode == 0xd0
 	   && i.tm.extension_opcode == 4
 	   && (i.tm.opcode_space == SPACE_BASE
-	       || i.tm.opcode_space == SPACE_EVEXMAP4)
+	       || i.tm.opcode_space == SPACE_MAP4)
 	   && !i.mem_operands)
     {
       /* Optimize: -O:
@@ -5198,7 +5198,7 @@  optimize_encoding (void)
     }
   else if (optimize > 1
 	   && (i.tm.base_opcode | 0xf) == 0x4f
-	   && i.tm.opcode_space == SPACE_EVEXMAP4
+	   && i.tm.opcode_space == SPACE_MAP4
 	   && i.reg_operands == 3
 	   && i.tm.opcode_modifier.operandconstraint == EVEX_NF
 	   && !i.types[0].bitfield.word)
@@ -6536,7 +6536,7 @@  static INLINE bool may_need_pass2 (const
 	   || (t->opcode_space == SPACE_BASE
 	       && t->base_opcode == 0x63)
 	   || (intel_syntax /* shld / shrd may mean suffixed shl / shr.  */
-	       && t->opcode_space == SPACE_EVEXMAP4
+	       && t->opcode_space == SPACE_MAP4
 	       && (t->base_opcode | 8) == 0x2c);
 }
 
@@ -7248,7 +7248,7 @@  i386_assemble (char *line)
     }
 #endif
 
-  if ((is_any_vex_encoding (&i.tm) && i.tm.opcode_space != SPACE_EVEXMAP4)
+  if ((is_any_vex_encoding (&i.tm) && i.tm.opcode_space != SPACE_MAP4)
       || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX
       || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)
     {
@@ -7405,7 +7405,7 @@  i386_assemble (char *line)
 
       /* Check for explicit REX prefix.  */
       if ((i.prefix[REX_PREFIX]
-	   && (i.tm.opcode_space != SPACE_EVEXMAP4
+	   && (i.tm.opcode_space != SPACE_MAP4
 	       /* To mimic behavior for legacy insns, permit use of REX64 for promoted
 		  legacy instructions.  */
 	       || i.prefix[REX_PREFIX] != (REX_OPCODE | REX_W)))
@@ -9325,7 +9325,7 @@  match_template (char mnem_suffix)
 	     - the non-default (swapped) form is requested.  */
 	  overlap1 = operand_type_and (operand_types[0], operand_types[1]);
 
-	  j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4
+	  j = i.operands - 1 - (t->opcode_space == SPACE_MAP4
 				&& t->opcode_modifier.vexvvvv);
 
 	  if (t->opcode_modifier.d && i.reg_operands == i.operands
@@ -9421,7 +9421,7 @@  match_template (char mnem_suffix)
 		  found_reverse_match = Opcode_VexW;
 		  goto check_operands_345;
 		}
-	      else if (t->opcode_space == SPACE_EVEXMAP4
+	      else if (t->opcode_space == SPACE_MAP4
 		       && t->operands >= 3)
 		{
 		  found_reverse_match = Opcode_D;
@@ -9429,11 +9429,11 @@  match_template (char mnem_suffix)
 		}
 	      else if (t->opcode_modifier.commutative
 		       /* CFCMOVcc also wants its major opcode unaltered.  */
-		       || (t->opcode_space == SPACE_EVEXMAP4
+		       || (t->opcode_space == SPACE_MAP4
 			   && (t->base_opcode | 0xf) == 0x4f))
 		found_reverse_match = ~0;
 	      else if (t->opcode_space != SPACE_BASE
-		       && (t->opcode_space != SPACE_EVEXMAP4
+		       && (t->opcode_space != SPACE_MAP4
 			   /* MOVBE, originating from SPACE_0F38, also
 			      belongs here.  */
 			   || t->mnem_off == MN_movbe)
@@ -9692,7 +9692,7 @@  match_template (char mnem_suffix)
 
   /* APX insns acting on byte operands are WIG, yet that can't be expressed
      in the templates (they're also covering word/dword/qword operands).  */
-  if (t->opcode_space == SPACE_EVEXMAP4 && !t->opcode_modifier.vexw &&
+  if (t->opcode_space == SPACE_MAP4 && !t->opcode_modifier.vexw &&
       i.types[i.operands - 1].bitfield.byte)
     {
       gas_assert (t->opcode_modifier.w);
@@ -9717,7 +9717,7 @@  match_template (char mnem_suffix)
 
       i.tm.base_opcode ^= found_reverse_match;
 
-      if (i.tm.opcode_space == SPACE_EVEXMAP4)
+      if (i.tm.opcode_space == SPACE_MAP4)
 	goto swap_first_2;
 
       /* Certain SIMD insns have their load forms specified in the opcode
@@ -9730,7 +9730,7 @@  match_template (char mnem_suffix)
 
       /* Fall through.  */
     case ~0:
-      if (i.tm.opcode_space == SPACE_EVEXMAP4
+      if (i.tm.opcode_space == SPACE_MAP4
 	  && !t->opcode_modifier.commutative)
 	i.tm.opcode_modifier.operandconstraint = EVEX_NF;
       i.tm.operand_types[0] = operand_types[i.operands - 1];
@@ -10170,7 +10170,7 @@  process_suffix (const insn_template *t)
       if (i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
 	  && !i.tm.opcode_modifier.floatmf
 	  && (!is_any_vex_encoding (&i.tm)
-	      || i.tm.opcode_space == SPACE_EVEXMAP4)
+	      || i.tm.opcode_space == SPACE_MAP4)
 	  && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
 	      || (flag_code == CODE_64BIT
 		  && i.tm.opcode_modifier.jump == JUMP_BYTE)))
@@ -10182,7 +10182,7 @@  process_suffix (const insn_template *t)
 
 	  /* The DATA PREFIX of EVEX promoted from legacy APX instructions
 	     needs to be adjusted.  */
-	  if (i.tm.opcode_space == SPACE_EVEXMAP4)
+	  if (i.tm.opcode_space == SPACE_MAP4)
 	    {
 	      gas_assert (!i.tm.opcode_modifier.opcodeprefix);
 	      i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
@@ -12752,7 +12752,7 @@  output_disp (fragS *insn_start_frag, off
 		fixP->fx_signed = 1;
 
 	      if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF
-		  && i.tm.opcode_space == SPACE_EVEXMAP4)
+		  && i.tm.opcode_space == SPACE_MAP4)
 		{
 		  /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is
 		     allowed in md_assemble.  Set fx_tcbit2 for EVEX
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -1139,10 +1139,10 @@  process_i386_opcode_modifier (FILE *tabl
     SPACE(0F),
     SPACE(0F38),
     SPACE(0F3A),
-    SPACE(EVEXMAP4),
-    SPACE(EVEXMAP5),
-    SPACE(EVEXMAP6),
-    SPACE(VEXMAP7),
+    SPACE(MAP4),
+    SPACE(MAP5),
+    SPACE(MAP6),
+    SPACE(MAP7),
     SPACE(XOP08),
     SPACE(XOP09),
     SPACE(XOP0A),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -987,15 +987,15 @@  typedef struct insn_template
   /* opcode space */
   unsigned int opcode_space:4;
   /* Opcode encoding space (values chosen to be usable directly in
-     VEX/XOP mmmmm and EVEX mm fields):
+     VEX/XOP mmmmm and EVEX mmm fields):
      0: Base opcode space.
      1: 0F opcode prefix / space.
      2: 0F38 opcode prefix / space.
      3: 0F3A opcode prefix / space.
-     4: EVEXMAP4 opcode prefix / space.
-     5: EVEXMAP5 opcode prefix / space.
-     6: EVEXMAP6 opcode prefix / space.
-     7: VEXMAP7 opcode prefix / space.
+     4: MAP4 opcode prefix / space.
+     5: MAP5 opcode prefix / space.
+     6: MAP6 opcode prefix / space.
+     7: MAP7 opcode prefix / space.
      8: XOP 08 opcode space.
      9: XOP 09 opcode space.
      A: XOP 0A opcode space.
@@ -1004,10 +1004,10 @@  typedef struct insn_template
 #define SPACE_0F	1
 #define SPACE_0F38	2
 #define SPACE_0F3A	3
-#define SPACE_EVEXMAP4	4
-#define SPACE_EVEXMAP5	5
-#define SPACE_EVEXMAP6	6
-#define SPACE_VEXMAP7	7
+#define SPACE_MAP4	4
+#define SPACE_MAP5	5
+#define SPACE_MAP6	6
+#define SPACE_MAP7	7
 #define SPACE_XOP08	8
 #define SPACE_XOP09	9
 #define SPACE_XOP0A	0xA
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -116,11 +116,11 @@ 
 #define SpaceXOP09 OpcodeSpace=SPACE_XOP09
 #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A
 
-#define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4|EVex128
-#define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5
-#define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6
+#define EVexMap4 OpcodeSpace=SPACE_MAP4|EVex128
 
-#define VexMap7 OpcodeSpace=SPACE_VEXMAP7
+#define Map5 OpcodeSpace=SPACE_MAP5
+#define Map6 OpcodeSpace=SPACE_MAP6
+#define Map7 OpcodeSpace=SPACE_MAP7
 
 #define VexW0 VexW=VEXW0
 #define VexW1 VexW=VEXW1
@@ -1933,7 +1933,7 @@  vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Spa
 <sdh:cpu:cpudq:fma:ppfx:spfx:pfx:spc1:spc2:opc:vex:vexlig:vexw:elem, +
     s:AVX512F:AVX512DQ:FMA|AVX512F::f3:66:Space0F:Space0F38:0:Vex|EVexDYN:VexLIG|EVexLIG:VexW0:Dword, +
     d:AVX512F:AVX512DQ:FMA|AVX512F:66:f2:66:Space0F:Space0F38:1:Vex|EVexDYN:VexLIG|EVexLIG:VexW1:Qword, +
-    h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::EVexMap5:EVexMap6:0::EVexLIG:VexW0:Word>
+    h:AVX512_FP16:AVX512_FP16:AVX512_FP16::f3::Map5:Map6:0::EVexLIG:VexW0:Word>
 
 v<fm><fma>p<sdh>, 0x66<fm:opc3> | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vex>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 v<fm><fma>s<sdh>, 0x66<fm:opc3> | 1 | 0x<fma:opc>, <sdh:fma>, Modrm|<sdh:vexlig>|Masking|<sdh:spc2>|Src1VVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
@@ -3251,17 +3251,17 @@  hreset, 0xf30f3af0c0, HRESET, NoSuf, { I
 
 // FP16 (HFNI) instructions.
 
-vfcmaddcph, 0xf256, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vfcmaddcsh, 0xf257, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vfcmaddcph, 0xf256, AVX512_FP16, Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfcmaddcsh, 0xf257, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vfmaddcph, 0xf356, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vfmaddcsh, 0xf357, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vfmaddcph, 0xf356, AVX512_FP16, Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfmaddcsh, 0xf357, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vfcmulcph, 0xf2d6, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vfcmulcsh, 0xf2d7, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vfcmulcph, 0xf2d6, AVX512_FP16, Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfcmulcsh, 0xf2d7, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vfmulcph, 0xf3d6, AVX512_FP16, Modrm|Src1VVVV|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vfmulcsh, 0xf3d7, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vfmulcph, 0xf3d6, AVX512_FP16, Modrm|Src1VVVV|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vfmulcsh, 0xf3d7, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
 vcmp<frel>ph, 0xc2/0x<frel:imm>, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
 vcmpph, 0xc2, AVX512_FP16, Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
@@ -3269,93 +3269,93 @@  vcmpph, 0xc2, AVX512_FP16, Modrm|Masking
 vcmp<frel>sh, 0xf3c2/0x<frel:imm>, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
 vcmpsh, 0xf3c2, AVX512_FP16, Modrm|EVexLIG|Masking|Space0F3A|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
 
-vcvtdq2ph<Exy>, 0x5b, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
-vcvtudq2ph<Exy>, 0xf27a, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
+vcvtdq2ph<Exy>, 0x5b, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|Map5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
+vcvtudq2ph<Exy>, 0xf27a, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|Map5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
 
-vcvtqq2ph<xyz>, 0x5b, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
-vcvtuqq2ph<xyz>, 0xf27a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
+vcvtqq2ph<xyz>, 0x5b, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|Map5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
+vcvtuqq2ph<xyz>, 0xf27a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|Map5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
 
-vcvtpd2ph<xyz>, 0x665a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
+vcvtpd2ph<xyz>, 0x665a, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|Map5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM }
 
-vcvtps2phx<Exy>, 0x661d, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
+vcvtps2phx<Exy>, 0x661d, AVX512_FP16&<Exy:vl>, Modrm|<Exy:attr>|Masking|Map5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> }
 
-vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtw2ph, 0xf37d, AVX512_FP16, Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtuw2ph, 0xf27d, AVX512_FP16, Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
-vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtph2dq, 0x665b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvtph2dq, 0x665b, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
-vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtph2udq, 0x79, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvtph2udq, 0x79, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
-vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtph2qq, 0x667b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtph2qq, 0x667b, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
-vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtph2uqq, 0x6679, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtph2uqq, 0x6679, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
-vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtph2pd, 0x5a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtph2pd, 0x5a, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtph2w, 0x667d, AVX512_FP16, Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvtph2uw, 0x7d, AVX512_FP16, Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsd2sh, 0xf25a, AVX512_FP16, Modrm|EVexLIG|Masking|Map5|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtss2sh, 0x1d, AVX512_FP16, Modrm|EVexLIG|Masking|Map5|Src1VVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sh, 0xf32a, AVX512_FP16, Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sh, 0xf37b, AVX512_FP16, Modrm|EVexLIG|Map5|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vcvtsh2sd, 0xf35a, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap5|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsh2sd, 0xf35a, AVX512_FP16, Modrm|EVexLIG|Masking|Map5|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsh2ss, 0x13, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvtsh2si, 0xf32d, AVX512_FP16, Modrm|EVexLIG|Map5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 
-vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
-vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
+vcvttph2dq, 0xf35b, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvttph2dq, 0xf35b, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
-vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
+vcvttph2udq, 0x78, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvttph2udq, 0x78, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
-vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
+vcvttph2qq, 0x667a, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvttph2qq, 0x667a, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
-vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
-vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM }
+vcvttph2uqq, 0x6678, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map5|VexW0|Broadcast|Disp8MemShift=3|NoSuf|SAE, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM }
+vcvttph2uqq, 0x6678, AVX512_FP16, Modrm|EVex512|Masking|Map5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
-vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
-vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
+vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex128|Masking|Map6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtph2psx, 0x6613, AVX512_FP16&AVX512VL, Modrm|EVex256|Masking|Map6|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegYMM }
+vcvtph2psx, 0x6613, AVX512_FP16, Modrm|EVex512|Masking|Map6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM }
 
-vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttph2w, 0x667c, AVX512_FP16, Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Masking|Map5|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|Map5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 
 vfpclassph<xyz>, 0x66, AVX512_FP16&<xyz:vl>, Modrm|<xyz:attr>|Masking|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8|Imm8S, <xyz:src>|Word, RegMask }
 
-vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM }
-vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 }
+vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|Map5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM }
+vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|Map5|NoSuf, { RegXMM, Reg32 }
 
-vrcpph, 0x664c, AVX512_FP16, Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vrcpph, 0x664c, AVX512_FP16, Modrm|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vrcpsh, 0x664d, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
+vrcpsh, 0x664d, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vrsqrtph, 0x664e, AVX512_FP16, Modrm|Masking|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vrsqrtph, 0x664e, AVX512_FP16, Modrm|Masking|Map6|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vrsqrtsh, 0x664f, AVX512_FP16, Modrm|EVexLIG|Masking|EVexMap6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
+vrsqrtsh, 0x664f, AVX512_FP16, Modrm|EVexLIG|Masking|Map6|Src1VVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
 
 // FP16 (HFNI) instructions end.
 
@@ -3412,12 +3412,12 @@  eretu, 0xf30f01ca, FRED, NoSuf, {}
 
 urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
 urdmsr, 0xf2f8, USER_MSR&APX_F, RegMem|EVexMap4|VexW0|NoSuf, { Reg64, Reg64 }
-urdmsr, 0xf2f8/0, APX_F(USER_MSR), Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
+urdmsr, 0xf2f8/0, APX_F(USER_MSR), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
 uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
 uwrmsr, 0xf3f8, USER_MSR&APX_F, Modrm|EVexMap4|VexW0|NoSuf, { Reg64, Reg64 }
 // Immediates want to be first; md_assemble() takes care of swapping operands
 // accordingly.
-uwrmsr, 0xf3f8/0, APX_F(USER_MSR), Modrm|Vex128|VexMap7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
+uwrmsr, 0xf3f8/0, APX_F(USER_MSR), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
 
 // USER_MSR instructions end.
 
@@ -3441,9 +3441,9 @@  vcvt2ps2phx, 0x6667, AVX10_2, Modrm|Spac
 
 <cvt8:opc:spc, +
     bf8:74:Space0F38, +
-    bf8s:74:EVexMap5, +
-    hf8:18:EVexMap5, +
-    hf8s:1b:EVexMap5>
+    bf8s:74:Map5, +
+    hf8:18:Map5, +
+    hf8s:1b:Map5>
 
 vcvtbiasph2<cvt8>, 0x<cvt8:opc>, AVX10_2, Modrm|<cvt8:spc>|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM }
 vcvtbiasph2<cvt8>, 0x<cvt8:opc>, AVX10_2, Modrm|<cvt8:spc>|EVex512|Src1VVVV|VexW0|Masking|Broadcast|Disp8MemShift=6|NoSuf, { RegZMM|Word|Unspecified|BaseIndex, RegZMM, RegYMM }
@@ -3452,8 +3452,8 @@  vcvtneph2<cvt8><Exy>, 0xf3<cvt8:opc>, AV
 
 <cvt8>
 
-vcvthf82ph, 0xf21e, AVX10_2, Modrm|EVexMap5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
-vcvthf82ph, 0xf21e, AVX10_2, Modrm|EVexMap5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
-vcvthf82ph, 0xf21e, AVX10_2, Modrm|EVexMap5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
+vcvthf82ph, 0xf21e, AVX10_2, Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvthf82ph, 0xf21e, AVX10_2, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
+vcvthf82ph, 0xf21e, AVX10_2, Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
 
 // AVX10.2 instructions end.