From patchwork Mon Feb 3 07:29:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongyan Chen X-Patchwork-Id: 105895 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4F24E3858416 for ; Mon, 3 Feb 2025 07:30:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4F24E3858416 X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id 8C7EB3858C98 for ; Mon, 3 Feb 2025 07:30:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8C7EB3858C98 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8C7EB3858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1738567802; cv=none; b=j0CySA2vMYc5Dchhqc/gGg+aMnQOjlTPEZMs6Jpoq4muZhuR882kSKl1pcI7r9QmELXiQ0pe2C71EMmPp3TgB+0exsIFks1Pi1nXq6wedgzLuxvaJWCRn2LIMA3fpVnSQlhdJzevVSI8LXXtXILKzIpYdOGdgW4Jp1aotXMMpl8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1738567802; c=relaxed/simple; bh=ZEpKF/PqXl55BVSY/EA1Tpj+GoZmf3jaYSXLhWRo5Q8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=IE+SXzNYAYXpKWIhMDaTKyuNuR0NhUHxdEHLd3MGvPAR9Zju96w9zShR6zXmodtyMLjsVQg8KwJv0cm41sd7aPQ9BdtBWsvrajMx+s2SqeDLhy5GXPHBWJThQIorSSno4dPLB9ZC2Atu+WrMGYxzMo5rtli8rQ5X4tvfrR7hLBc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C7EB3858C98 Received: from TYZPR03MB6623.apcprd03.prod.outlook.com (unknown [40.99.22.45]) by APP-01 (Coremail) with SMTP id qwCowAD3_dFwcKBnl4l9Cg--.10083S2; Mon, 03 Feb 2025 15:29:54 +0800 (CST) From: "chendongyan@isrc.iscas.ac.cn" To: "binutils@sourceware.org" CC: "kito.cheng@gmail.com" , "nelson@rivosinc.com" , "wuwei2016@iscas.ac.cn" , "jiawei@iscas.ac.cn" , "chenyixuan@iscas.ac.cn" , Jan Beulich , Dongyan Chen Subject: [PATCH v3] RISC-V: Add support for svvptc extension. Thread-Topic: [PATCH v3] RISC-V: Add support for svvptc extension. Thread-Index: AQHbdghAKky4ynMVNU225hG8dhn4OQ== X-MS-Exchange-MessageSentRepresentingType: 1 Date: Mon, 3 Feb 2025 07:29:52 +0000 Message-ID: Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-Exchange-Organization-SCL: -1 X-MS-TNEF-Correlator: X-MS-Exchange-Organization-RecordReviewCfmType: 0 msip_labels: MIME-Version: 1.0 X-CM-TRANSID: qwCowAD3_dFwcKBnl4l9Cg--.10083S2 X-Coremail-Antispam: 1UD129KBjvJXoW7tFW3GF13Zr47Jr4DCrW7Arb_yoW8KFyfpF s5Ca1jkr93JFn7Xrn3KF1UKr4fJw4I9r129r4Fywn8t3sxJr45Xr92yas09an5ZFs3W3W3 uw43trW5ua98u3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r1j6r 4UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVC20s02628v4x8GjsIEw4AK0wAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcVAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACY4xI67k04243AVAKzVAK j4xxM4xvF2IEb7IF0Fy26I8I3I1lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUGVWUWwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVA0820Y0xCF62I06xkIj41lx4CE17CEb7AF67AKxVWUtVW8ZwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr 1lIxAIcVC2z280aVCY1x0267AKxVWUJVW8JwCE64xvF2IEb7IF0Fy7YxBIdaVFxhVjvjDU 0xZFpf9x0JUxpndUUUUU= X-Originating-IP: [40.99.22.45] X-CM-SenderInfo: hfkh0v5rqj5tnq6l223fol2u1dvotugofq/ X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This implements the svvptc extensons, version 1.0[1]. [1] https://github.com/riscv/riscv-svvptc bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle svvptc. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. modify gas/NEWS --- bfd/elfxx-riscv.c | 5 +++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 1 + 3 files changed, 8 insertions(+) -- 2.43.0 diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 701c7242920..44484f12967 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1459,6 +1459,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svvptc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2726,6 +2727,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zcmt"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); + case INSN_CLASS_SVVPTC: + return riscv_subset_supports (rps, "svvptc"); case INSN_CLASS_H: return riscv_subset_supports (rps, "h"); case INSN_CLASS_XCVALU: @@ -3010,6 +3013,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "zcmt"; case INSN_CLASS_SVINVAL: return "svinval"; + case INSN_CLASS_SVVPTC: + return "svvptc"; case INSN_CLASS_H: return _("h"); case INSN_CLASS_XCVALU: diff --git a/gas/NEWS b/gas/NEWS index 67ca298d11e..848e7c14878 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -9,6 +9,8 @@ * Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi and CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0. + Add support for the RISC-V svvptc extension, version 1.0. + Changes in 2.43: * Add support for LoongArch .option for fine-grained control of assembly diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 4234b05598f..011bd6fea19 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -133,6 +133,7 @@ All available -march extensions for RISC-V: svinval 1.0 svnapot 1.0 svpbmt 1.0 + svvptc 1.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0