diff mbox series

[5/5] aarch64: Replace FLD_* macros in do_misc_{en|de}coding

Message ID 93a453e3-789a-5792-7e73-c6abc97df283@e124511.cambridge.arm.com
State New
Headers
Series aarch64: Remove aarch64_field_kind indirection |

Checks

Context Check Description
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Commit Message

Alice Carlotti May 20, 2026, 12:10 p.m. UTC 
  Replace the macros with explicit AARCH64_FIELD calls, and extend the
comments to clarify which aliased instructions are involved.
diff mbox series

Patch

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index ef1e093ed94ef3923399e00fbd4495047b5e4969..188cdd8a4770190f6a516aa3acc5a32ca662e207 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1948,42 +1948,42 @@  do_misc_encoding (aarch64_inst *inst)
     case OP_MOV_P_P:
     case OP_MOV_PN_PN:
     case OP_MOVS_P_P:
-      /* Copy Pn to Pm and Pg.  */
-      value = extract_field (FLD_SVE_Pn, inst->value, 0);
-      insert_field (FLD_SVE_Pm, &inst->value, value, 0);
-      insert_field (FLD_SVE_Pg4_10, &inst->value, value, 0);
+      /* ORR/ORRS alias.  Copy Pn to Pm and Pg.  */
+      value = extract_field (AARCH64_FIELD (5, 4), inst->value, 0);
+      insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0);
+      insert_field (AARCH64_FIELD (10, 4), &inst->value, value, 0);
       break;
     case OP_MOV_Z_P_Z:
-      /* Copy Zd to Zm.  */
-      value = extract_field (FLD_SVE_Zd, inst->value, 0);
-      insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
+      /* SEL alias.  Copy Zd to Zm.  */
+      value = extract_field (AARCH64_FIELD (0, 5), inst->value, 0);
+      insert_field (AARCH64_FIELD (16, 5), &inst->value, value, 0);
       break;
     case OP_MOV_Z_V:
-      /* Fill in the zero immediate.  */
+      /* DUP alias.  Fill in the zero index and element size.  */
       insert_fields (&inst->value, 1 << aarch64_get_variant (inst), 0,
-		     2, FLD_imm5, FLD_SVE_tszh);
+		     2, AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 2));
       break;
     case OP_MOV_Z_Z:
-      /* Copy Zn to Zm.  */
-      value = extract_field (FLD_SVE_Zn, inst->value, 0);
-      insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
+      /* ORR alias.  Copy Zn to Zm.  */
+      value = extract_field (AARCH64_FIELD (5, 5), inst->value, 0);
+      insert_field (AARCH64_FIELD (16, 5), &inst->value, value, 0);
       break;
     case OP_MOVM_P_P_P:
-      /* Copy Pd to Pm.  */
-      value = extract_field (FLD_SVE_Pd, inst->value, 0);
-      insert_field (FLD_SVE_Pm, &inst->value, value, 0);
+      /* SEL alias.  Copy Pd to Pm.  */
+      value = extract_field (AARCH64_FIELD (0, 4), inst->value, 0);
+      insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0);
       break;
     case OP_MOVZS_P_P_P:
     case OP_MOVZ_P_P_P:
-      /* Copy Pn to Pm.  */
-      value = extract_field (FLD_SVE_Pn, inst->value, 0);
-      insert_field (FLD_SVE_Pm, &inst->value, value, 0);
+      /* AND/ANDS alias.  Copy Pn to Pm.  */
+      value = extract_field (AARCH64_FIELD (5, 4), inst->value, 0);
+      insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0);
       break;
     case OP_NOTS_P_P_P_Z:
     case OP_NOT_P_P_P_Z:
-      /* Copy Pg to Pm.  */
-      value = extract_field (FLD_SVE_Pg4_10, inst->value, 0);
-      insert_field (FLD_SVE_Pm, &inst->value, value, 0);
+      /* EOR/EORS alias.  Copy Pg to Pm.  */
+      value = extract_field (AARCH64_FIELD (10, 4), inst->value, 0);
+      insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0);
       break;
     default: break;
     }
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 3723defe5e019d9188b150e16f645b0551421688..3b3ad7615de9eec3a25aaaa03a7ebb4cbc64aabc 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2712,36 +2712,46 @@  do_misc_decoding (aarch64_inst *inst)
 
     case OP_MOV_P_P:
     case OP_MOVS_P_P:
-      value = extract_field (FLD_SVE_Pn, inst->value, 0);
-      return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
-	      && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
+      /* ORR/ORRS alias with Pn == Pm == Pg.  */
+      value = extract_field (AARCH64_FIELD (5, 4), inst->value, 0);
+      return (value == extract_field (AARCH64_FIELD (16, 4), inst->value, 0)
+	      && value == extract_field (AARCH64_FIELD (10, 4),
+					 inst->value, 0));
 
     case OP_MOV_Z_P_Z:
-      return (extract_field (FLD_SVE_Zd, inst->value, 0)
-	      == extract_field (FLD_SVE_Zm_16, inst->value, 0));
+      /* SEL alias with Zd == Zm.  */
+      return (extract_field (AARCH64_FIELD (0, 5), inst->value, 0)
+	      == extract_field (AARCH64_FIELD (16, 5), inst->value, 0));
 
     case OP_MOV_Z_V:
-      /* Index must be zero.  */
-      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
-      return value > 0 && value <= 16 && value == (value & -value);
+      /* DUP alias with zero index.  Index and size use a triangle encoding,
+	 and we already know that one of the bottom 5 bits is nonzero, so we
+	 just need to check that the bitcount is at most 1.  */
+      value = extract_fields (inst->value, 0, 2, AARCH64_FIELD (22, 2),
+			      AARCH64_FIELD (16, 5));
+      return value == (value & -value);
 
     case OP_MOV_Z_Z:
-      return (extract_field (FLD_SVE_Zn, inst->value, 0)
-	      == extract_field (FLD_SVE_Zm_16, inst->value, 0));
+      /* ORR alias with Zn == Zm.  */
+      return (extract_field (AARCH64_FIELD (5, 5), inst->value, 0)
+	      == extract_field (AARCH64_FIELD (16, 5), inst->value, 0));
 
     case OP_MOVM_P_P_P:
-      return (extract_field (FLD_SVE_Pd, inst->value, 0)
-	      == extract_field (FLD_SVE_Pm, inst->value, 0));
+      /* SEL alias with Pd == Pm.  */
+      return (extract_field (AARCH64_FIELD (0, 4), inst->value, 0)
+	      == extract_field (AARCH64_FIELD (16, 4), inst->value, 0));
 
     case OP_MOVZS_P_P_P:
     case OP_MOVZ_P_P_P:
-      return (extract_field (FLD_SVE_Pn, inst->value, 0)
-	      == extract_field (FLD_SVE_Pm, inst->value, 0));
+      /* AND/ANDS alias with Pn == Pm.  */
+      return (extract_field (AARCH64_FIELD (5, 4), inst->value, 0)
+	      == extract_field (AARCH64_FIELD (16, 4), inst->value, 0));
 
     case OP_NOTS_P_P_P_Z:
     case OP_NOT_P_P_P_Z:
-      return (extract_field (FLD_SVE_Pm, inst->value, 0)
-	      == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
+      /* EOR/EORS alias with Pm == Pg.  */
+      return (extract_field (AARCH64_FIELD (16, 4), inst->value, 0)
+	      == extract_field (AARCH64_FIELD (10, 4), inst->value, 0));
 
     default:
       return 0;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index a0553f8fd940c1a0e994bc4a0c8dd945fdb96494..772f485f50ab9bd9d32f53b5f2f87e6034a74682 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -88,13 +88,6 @@  typedef struct aarch64_field aarch64_field;
 #define FLD_SVE_M_4            AARCH64_FIELD( 4,  1)
 #define FLD_SVE_M_14           AARCH64_FIELD(14,  1)
 #define FLD_SVE_M_16           AARCH64_FIELD(16,  1)
-#define FLD_SVE_Pd             AARCH64_FIELD( 0,  4)
-#define FLD_SVE_Pg4_10         AARCH64_FIELD(10,  4)
-#define FLD_SVE_Pm             AARCH64_FIELD(16,  4)
-#define FLD_SVE_Pn             AARCH64_FIELD( 5,  4)
-#define FLD_SVE_Zd             AARCH64_FIELD( 0,  5)
-#define FLD_SVE_Zm_16          AARCH64_FIELD(16,  5)
-#define FLD_SVE_Zn             AARCH64_FIELD( 5,  5)
 #define FLD_SVE_imm4           AARCH64_FIELD(16,  4)
 #define FLD_SVE_imm6           AARCH64_FIELD(16,  6)
 #define FLD_SVE_msz            AARCH64_FIELD(10,  2)