From patchwork Mon Dec 9 22:47:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Bergner X-Patchwork-Id: 102719 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 823E2385841C for ; Mon, 9 Dec 2024 22:48:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 823E2385841C Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=hfE6ksc4 X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 417F83858D33 for ; Mon, 9 Dec 2024 22:47:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 417F83858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 417F83858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733784472; cv=none; b=ln3v60YJNyGQfdfCpRyOnu0WCQA2ttzS23OJ08iyTZxjmt4k3O0pXjWBXO3jWZWbfJxRX0rjRUwfVFzh+H/fhHsSewG9qoXSFEZ5hOkQvAvg5uO1vknOPZqETQcO0wJbNPYOzV0lnCBXVtUEgNZRxFfh5kd+h2raeqLWGS58jpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1733784472; c=relaxed/simple; bh=7zcEmTfvHbp99f8P1y+qKAefvGpFo4tmZq+HfemvCuA=; h=DKIM-Signature:Message-ID:Date:MIME-Version:To:From:Subject; b=wVJ+xDSJL5fgh0CdsgHzu5lrbsDLkbywNpAbUusLVf7C0rGrf2BoNALN4CyCQHlyTsxeVnH9ATUnkyGBOSr4DgUx4YRAk4M0jXkinq4/+pCYq0pOEe0WncNgR9IdKwdhJ5kRrZTgX+BT6iQeumfa1+YN4WQLLkhtvZV2AMg6zj4= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 417F83858D33 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B9MIJcX009464 for ; Mon, 9 Dec 2024 22:47:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pp1; bh=AUlsfD8k77FgpHdwqPUtGuWMfcDJ UsdGIOlPup26M+0=; b=hfE6ksc4hKskM0Z0TfLvQ0YA+86ztMO0qpHeUvqHemR9 MzCcxobkTn6CR/3H9NDYmg4l5gTFra9xeSNjmYFVyC+LfGH+p3ZYpVMHC/fZ2QHO axoc/YxlgoFrDPBQ1oHRIayUu/hItFnTmwfssYJdpiAAkxlw1XcEzUSPwRnPkgbf ua/fimvsY7oKtGuZYJW1MJYo4StzghPJkEhZkPwaLfF3oIw7dLAV1vNVPrBiDFXF qB43UNiZlCuxNju5Q3maz0ccTF1fbKerj9JeVEMFrkhgljVUkdTWLHCBNg01rDpt G8fWuw5b0woBU5f7W0LsOq74VMuqHTn6nzZ04XkW7g== Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 43ce38kvuk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 09 Dec 2024 22:47:50 +0000 (GMT) Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 4B9M0Vkv016926 for ; Mon, 9 Dec 2024 22:47:49 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 43d12y0wb8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 09 Dec 2024 22:47:49 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4B9Mlm9S10158610 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 9 Dec 2024 22:47:48 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 957125805C; Mon, 9 Dec 2024 22:47:48 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3681658051; Mon, 9 Dec 2024 22:47:48 +0000 (GMT) Received: from [9.61.241.157] (unknown [9.61.241.157]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 9 Dec 2024 22:47:48 +0000 (GMT) Message-ID: <8a42a2b7-8805-4eca-9f3a-b2e7362fdf0a@linux.ibm.com> Date: Mon, 9 Dec 2024 16:47:47 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: Binutils Cc: Surya Kumari Jangala , Sachin Monga From: Peter Bergner Subject: [PATCH, Committed] PowerPC: Disallow r0 as a base register for the hashst and hashchk insns X-TM-AS-GCONF: 00 X-Proofpoint-GUID: CYtnx6txIeyjQKnsyhZXxSQb2ybi_m0D X-Proofpoint-ORIG-GUID: CYtnx6txIeyjQKnsyhZXxSQb2ybi_m0D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 spamscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090175 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org I noticed while Sachin and I were adding ROP support to GLIBC, that the assembler failed to emit an error when we erroneously tried using r0 as the base address register in a hashst instruction. The following commit fixes that oversight. Pushed. Peter PowerPC: Disallow r0 as a base register for the hashst and hashchk insns Using r0 as a base address register in the ROP hashst and hashchk instructions is invalid. Modify the assembler to catch that illegal use and emit an error. opcodes/ * ppc-opc.c (insert_ras): Update error message and function comment. (powerpc_opcodes) : Use RAS. --- opcodes/ppc-opc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index ed5675b4f93..568a3d6d8f0 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1596,7 +1596,7 @@ insert_ras (uint64_t insn, const char **errmsg) { if (value == 0) - *errmsg = _("invalid register operand when updating"); + *errmsg = _("invalid base address register operand"); return insn | ((value & 0x1f) << 16); } @@ -3359,8 +3359,8 @@ const struct powerpc_operand powerpc_operands[] = { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, /* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ + store or an updating floating point load or a hash store or check, + which means that the RA field may not be zero. */ #define RAS RAM + 1 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, @@ -8555,7 +8555,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, -{"hashstp", X(31,658), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, +{"hashstp", X(31,658), XRC_MASK, POWER8, 0, {RB, DW, RAS}}, {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, @@ -8588,7 +8588,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, -{"hashchkp", X(31,690), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, +{"hashchkp", X(31,690), XRC_MASK, POWER8, 0, {RB, DW, RAS}}, {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, @@ -8621,7 +8621,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, -{"hashst", X(31,722), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, +{"hashst", X(31,722), XRC_MASK, POWER8, 0, {RB, DW, RAS}}, {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, @@ -8671,7 +8671,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, EXT, {0}}, {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, -{"hashchk", X(31,754), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, +{"hashchk", X(31,754), XRC_MASK, POWER8, 0, {RB, DW, RAS}}, {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},