aarch64: move SHA512 instructions to +sha3

Message ID 8655e412-ed86-a9d6-9d2c-4d553a93ea5e@e124511.cambridge.arm.com
State Committed
Headers
Series aarch64: move SHA512 instructions to +sha3 |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Andrew Carlotti Jan. 25, 2024, 5:26 p.m. UTC
  SHA512 instructions were added to the architecture at the same time as SHA3
instructions, but later than the SHA1 and SHA256 instructions.  Furthermore,
implementations must support either both or neither of the SHA512 and SHA3
instruction sets.  However, SHA512 instructions were originally (and
incorrectly) added to Binutils under the +sha2 flag.

This patch moves SHA512 instructions under the +sha3 flag, which matches the
architecture constraints and existing GCC and LLVM behaviour.

Ok for master?
  

Comments

Nick Clifton Jan. 26, 2024, 11:46 a.m. UTC | #1
Hi Andrew,

> SHA512 instructions were added to the architecture at the same time as SHA3
> instructions, but later than the SHA1 and SHA256 instructions.  Furthermore,
> implementations must support either both or neither of the SHA512 and SHA3
> instruction sets.  However, SHA512 instructions were originally (and
> incorrectly) added to Binutils under the +sha2 flag.
> 
> This patch moves SHA512 instructions under the +sha3 flag, which matches the
> architecture constraints and existing GCC and LLVM behaviour.
> 
> Ok for master?

Approved - please apply.

Cheers
   Nick
  

Patch

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 66d68c00725a7d7383afaecc015bf3f9dd36923a..9ea4de01c608d4af9d1fcc6d696e62aa2b5f6505 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6047,11 +6047,11 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   DOT_INSN ("sdot", 0xe009400,  0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
   DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
   DOT_INSN ("sdot", 0xf00e000,  0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
-/* Crypto SHA2 (optional in ARMv8.2-a).  */
-  SHA2_INSN ("sha512h",   0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
-  SHA2_INSN ("sha512h2",  0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
-  SHA2_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0),
-  SHA2_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0),
+/* Crypto SHA512 (optional in ARMv8.2-a).  */
+  SHA3_INSN ("sha512h",   0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
+  SHA3_INSN ("sha512h2",  0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
+  SHA3_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0),
+  SHA3_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0),
   /* Crypto SHA3 (optional in ARMv8.2-a).  */
   SHA3_INSN ("eor3",      0xce000000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0),
   SHA3_INSN ("rax1",      0xce608c00, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0),