@@ -1232,7 +1232,7 @@ static const struct riscv_implicit_subse
{"v", "+zve64d,+zvl128b", check_implicit_always},
{"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
{"zvfhmin", "+zve32f", check_implicit_always},
- {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
+ {"zvfbfwma", "+zfbfmin,+zvfbfmin", check_implicit_always},
{"zvfbfmin", "+zve32f", check_implicit_always},
{"zve64d", "+d,+zve64f", check_implicit_always},
{"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
@@ -27,7 +27,7 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
-[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0