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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38bf78sm14673178f8f.48.2025.01.14.05.19.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Jan 2025 05:19:29 -0800 (PST) Message-ID: <5831b6ba-ef24-4e0a-898a-45daa37ba984@suse.com> Date: Tue, 14 Jan 2025 14:19:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/2] x86/APX: widen @gotpcrel and @gottpoff support (incl to MOVRS) From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: X-Spam-Status: No, score=-3022.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org If legacy-encoded arithmetic insns are eligible for @gotpcrel relaxation, EVEX-encoded ones ought to be, too. Further anything that MOV-from-memory can be used for (and transformed from) should then also extend to MOVRS. While extending the apx-load* testcases add -mrelax-relocations=yes to the two ones which were missing this: Without this option the intended testing would not occur on configurations defaulting the option to off. --- The checks of i.operands in output_disp() look redundant to me. Drop them? In elf_x86_64_check_tls_transition() and elf_x86_64_relocate_section() why are some reads from contents[] plain array operations, while others involve bfd_get_8()? I question the altering from ADD to LEA for R_X86_64_GOTTPOFF: Besides the EFLAGS aspect, ADD (with immediate operand) also is commonly yet cheaper to execute (no address generation involved). Plus we have code for transforming to ADD-by-immediate anyway (to cover the ModRM.rm == 4 special case), so we could actually simplify the code by uniformly transforming to ADD-by-immediate. --- a/bfd/elf64-x86-64.c +++ b/bfd/elf64-x86-64.c @@ -1363,19 +1363,45 @@ elf_x86_64_check_tls_transition (bfd *ab /* Check transition from IE access model: mov foo@gottpoff(%rip), %reg add foo@gottpoff(%rip), %reg - where reg is one of r16 to r31. */ + where reg is one of r16 to r31. + For x32 also: + movrs foo@gottpoff(%rip), %reg + where no REX prefix is present. */ if (offset < 4 - || (offset + 4) > sec->size - || contents[offset - 4] != 0xd5) + || (offset + 4) > sec->size) + return elf_x86_tls_error_yes; + + if (!ABI_64_P (abfd) + && contents[offset - 4] == 0x0f + && contents[offset - 3] == 0x38 + && contents[offset - 2] == 0x8b) + goto check_gottpoff_modrm; + + if (contents[offset - 4] != 0xd5) return elf_x86_tls_error_yes; goto check_gottpoff; + case R_X86_64_CODE_5_GOTTPOFF: + /* Check transition from IE access model: + movrs foo@gottpoff(%rip), %reg + where reg isn't one of r16 to r31. */ + if (offset < 5 + || (offset + 4) > sec->size + || (contents[offset - 5] | (ABI_64_P (abfd) ? 7 : 0xf)) != 0x4f + || contents[offset - 4] != 0x0f + || contents[offset - 3] != 0x38 + || contents[offset - 2] != 0x8b) + return elf_x86_tls_error_yes; + + goto check_gottpoff_modrm; + case R_X86_64_CODE_6_GOTTPOFF: /* Check transition from IE access model: add %reg1, foo@gottpoff(%rip), %reg2 - where reg1/reg2 are one of r16 to r31. */ + movrs foo@gottpoff(%rip), %reg + where reg1/reg2/reg are one of r16 to r31. */ if (offset < 6 || (offset + 4) > sec->size @@ -1383,13 +1409,10 @@ elf_x86_64_check_tls_transition (bfd *ab return elf_x86_tls_error_yes; val = bfd_get_8 (abfd, contents + offset - 2); - if (val != 0x01 && val != 0x03) - return elf_x86_tls_error_add; + if (val != 0x01 && val != 0x03 && val != 0x8b) + return elf_x86_tls_error_add_movrs; - val = bfd_get_8 (abfd, contents + offset - 1); - return ((val & 0xc7) == 5 - ? elf_x86_tls_error_none - : elf_x86_tls_error_yes); + goto check_gottpoff_modrm; case R_X86_64_GOTTPOFF: /* Check transition from IE access model: @@ -1422,6 +1445,7 @@ elf_x86_64_check_tls_transition (bfd *ab if (val != 0x8b && val != 0x03) return elf_x86_tls_error_add_mov; + check_gottpoff_modrm: val = bfd_get_8 (abfd, contents + offset - 1); return ((val & 0xc7) == 5 ? elf_x86_tls_error_none @@ -1548,6 +1572,7 @@ elf_x86_64_tls_transition (struct bfd_li case R_X86_64_CODE_4_GOTPC32_TLSDESC: case R_X86_64_GOTTPOFF: case R_X86_64_CODE_4_GOTTPOFF: + case R_X86_64_CODE_5_GOTTPOFF: case R_X86_64_CODE_6_GOTTPOFF: if (bfd_link_executable (info)) { @@ -1582,6 +1607,8 @@ elf_x86_64_tls_transition (struct bfd_li && (from_type == to_type || (from_type == R_X86_64_CODE_4_GOTTPOFF && to_type == R_X86_64_GOTTPOFF) + || (from_type == R_X86_64_CODE_5_GOTTPOFF + && to_type == R_X86_64_GOTTPOFF) || (from_type == R_X86_64_CODE_6_GOTTPOFF && to_type == R_X86_64_GOTTPOFF))); to_type = new_to_type; @@ -1602,6 +1629,8 @@ elf_x86_64_tls_transition (struct bfd_li if (from_type == to_type || (from_type == R_X86_64_CODE_4_GOTTPOFF && to_type == R_X86_64_GOTTPOFF) + || (from_type == R_X86_64_CODE_5_GOTTPOFF + && to_type == R_X86_64_GOTTPOFF) || (from_type == R_X86_64_CODE_6_GOTTPOFF && to_type == R_X86_64_GOTTPOFF)) return true; @@ -1711,6 +1740,7 @@ elf_x86_64_need_pic (struct bfd_link_inf /* With the local symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg + movrs foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert @@ -1748,35 +1778,85 @@ elf_x86_64_convert_load_reloc (bfd *abfd bfd_signed_vma raddend; unsigned int opcode; unsigned int modrm; + unsigned char evex[3] = { 0, 0, 0 }; unsigned int r_type = *r_type_p; unsigned int r_symndx; bfd_vma roff = irel->r_offset; bfd_vma abs_relocation; - if (roff < (r_type == R_X86_64_CODE_4_GOTPCRELX - ? 4 : (r_type == R_X86_64_REX_GOTPCRELX ? 3 : 2))) - return true; + switch (r_type) + { + default: + if (roff < 2) + return true; + relocx = (r_type == R_X86_64_GOTPCRELX); + true; + break; - raddend = irel->r_addend; - /* Addend for 32-bit PC-relative relocation must be -4. */ - if (raddend != -4) - return true; + case R_X86_64_REX_GOTPCRELX: + if (roff < 3) + return true; + relocx = true; + break; - htab = elf_x86_hash_table (link_info, X86_64_ELF_DATA); - is_pic = bfd_link_pic (link_info); + case R_X86_64_CODE_4_GOTPCRELX: + if (roff < 4) + return true; - if (r_type == R_X86_64_CODE_4_GOTPCRELX) - { - /* Skip if this isn't a REX2 instruction. */ + /* Skip if this isn't a REX2 instruction, nor un-prefixed MOVRS. */ opcode = bfd_get_8 (abfd, contents + roff - 4); - if (opcode != 0xd5) + if (opcode != 0xd5 + && (opcode != 0x0f + || bfd_get_8 (abfd, contents + roff - 3) != 0x38 + || bfd_get_8 (abfd, contents + roff - 2) != 0x8b)) + return true; + + relocx = true; + break; + + case R_X86_64_CODE_5_GOTPCRELX: + if (roff < 5) + return true; + + /* Skip if this isn't REX-prefixed MOVRS. */ + if ((bfd_get_8 (abfd, contents + roff - 5) | 0xf) != 0x4f + || bfd_get_8 (abfd, contents + roff - 4) != 0x0f + || bfd_get_8 (abfd, contents + roff - 3) != 0x38 + || bfd_get_8 (abfd, contents + roff - 2) != 0x8b) + return true; + + relocx = true; + break; + + case R_X86_64_CODE_6_GOTPCRELX: + if (roff < 6) + return true; + + /* Skip if this isn't an EVEX instruction. */ + if (bfd_get_8 (abfd, contents + roff - 6) != 0x62) + return true; + + evex[0] = bfd_get_8 (abfd, contents + roff - 5); + evex[1] = bfd_get_8 (abfd, contents + roff - 4); + evex[2] = bfd_get_8 (abfd, contents + roff - 3); + + /* Skip if this isn't a Map 4 NP instruction. */ + if ((evex[0] & 7) != 4 + || (evex[1] & 3) != 0 + || (evex[2] & 0xe0) != 0) return true; relocx = true; + break; } - else - relocx = (r_type == R_X86_64_GOTPCRELX - || r_type == R_X86_64_REX_GOTPCRELX); + + raddend = irel->r_addend; + /* Addend for 32-bit PC-relative relocation must be -4. */ + if (raddend != -4) + return true; + + htab = elf_x86_hash_table (link_info, X86_64_ELF_DATA); + is_pic = bfd_link_pic (link_info); /* TRUE if --no-relax is used. */ no_overflow = link_info->disable_target_specific_optimizations > 1; @@ -1789,7 +1869,7 @@ elf_x86_64_convert_load_reloc (bfd *abfd if (opcode != 0x8b) { /* Only convert R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX - and R_X86_64_CODE_4_GOTPCRELX for call, jmp or one of adc, + and R_X86_64_CODE__GOTPCRELX for call, jmp or one of adc, add, and, cmp, or, sbb, sub, test, xor instructions. */ if (!relocx) return true; @@ -1973,18 +2053,113 @@ elf_x86_64_convert_load_reloc (bfd *abfd bfd_put_8 (abfd, modrm, contents + irel->r_offset - 1); r_type = R_X86_64_PC32; } + else if (r_type == R_X86_64_CODE_6_GOTPCRELX && opcode != 0x8b) + { + /* R_X86_64_PC32 isn't supported. */ + if (to_reloc_pc32) + return true; + + modrm = bfd_get_8 (abfd, contents + roff - 1); + if (opcode == 0x85) + { + /* Convert "ctest %reg, foo@GOTPCREL(%rip)" to + "ctest $foo, %reg". */ + modrm = 0xc0 | (modrm & 0x38) >> 3; + opcode = 0xf7; + } + else if ((opcode | 0x3a) == 0x3b) + { + /* Don't convert (non-NDD) forms with memory destination. */ + if (!(evex[2] & 0x10) && (opcode | 0x38) != 0x3b) + return true; + + /* Don't convert non-commutative insns with the memory operand + 2nd. */ + if ((evex[2] & 0x10) && (opcode | 0x38) != 0x3b + && (opcode == 0x19 /* SBB */ + || opcode == 0x29 /* SUB */)) + return true; + + /* Convert "binop foo@GOTPCREL(%rip), %reg" to + "binop $foo, %reg", or alike for 3-operand forms. */ + modrm = 0xc0 | ((modrm & 0x38) >> 3) | (opcode & 0x38); + opcode = 0x81; + } + else + return true; + + /* Use R_X86_64_32 with 32-bit operand to avoid relocation + overflow when sign-extending imm32 to 64 bits. */ + r_type = evex[1] & 0x80 ? R_X86_64_32S : R_X86_64_32; + + if (abs_relocation) /* Bogus; should be abs_symbol. */ + { + /* Check if R_X86_64_32S/R_X86_64_32 fits. */ + if (r_type == R_X86_64_32S) + { + if ((abs_relocation + 0x80000000) > 0xffffffff) + return true; + } + else + { + if (abs_relocation > 0xffffffff) + return true; + } + } + + bfd_put_8 (abfd, opcode, contents + roff - 2); + bfd_put_8 (abfd, modrm, contents + roff - 1); + + /* Move the R bits to the B bits in the first EXEX payload byte. */ + evex[0] = (evex[0] & ~0xa0) | ((evex[0] & 0x80) >> 2); /* R3 -> B3 */ + evex[0] = (evex[0] & ~0x18) | ((~evex[0] & 0x10) >> 1); /* R4 -> B4 */ + bfd_put_8 (abfd, evex[0], contents + roff - 5); + + /* No addend for R_X86_64_32/R_X86_64_32S relocations. */ + irel->r_addend = 0; + } else { unsigned int rex = 0; unsigned int rex_mask = REX_R; unsigned int rex2 = 0; unsigned int rex2_mask = REX_R | REX_R << 4; + unsigned int movrs = 0; bool rex_w = false; - if (r_type == R_X86_64_CODE_4_GOTPCRELX) + if (r_type == R_X86_64_CODE_6_GOTPCRELX) + { + /* Synthesize a REX2 prefix from EVEX, just enough for the LEA + and MOV case below. */ + unsigned int p; + + p = bfd_get_8 (abfd, contents + roff - 5); + if (!(p & 0x80)) + rex2 |= REX_R; + if (!(p & 0x10)) + rex2 |= REX_R << 4; + if (bfd_get_8 (abfd, contents + roff - 4) & 0x80) + { + rex2 |= REX_W; + rex_w = true; + } + movrs = 6; + } + else if (r_type == R_X86_64_CODE_5_GOTPCRELX) + { + rex = bfd_get_8 (abfd, contents + roff - 5); + rex_w = (rex & REX_W) != 0; + movrs = 5; + } + else if (r_type == R_X86_64_CODE_4_GOTPCRELX) { - rex2 = bfd_get_8 (abfd, contents + roff - 3); - rex_w = (rex2 & REX_W) != 0; + if (bfd_get_8 (abfd, contents + roff - 4) == 0xd5) + { + rex2 = bfd_get_8 (abfd, contents + roff - 3); + rex_w = (rex2 & REX_W) != 0; + } + else if (bfd_get_8 (abfd, contents + roff - 4) == 0x0f) + movrs = 4; } else if (r_type == R_X86_64_REX_GOTPCRELX) { @@ -2003,6 +2178,10 @@ elf_x86_64_convert_load_reloc (bfd *abfd "lea foo(%rip), %reg". */ opcode = 0x8d; r_type = R_X86_64_PC32; + + /* For MOVRS move a possible REX prefix as necessary. */ + if (movrs == 5) + bfd_put_8 (abfd, rex, contents + roff - 3); } else { @@ -2093,6 +2272,20 @@ elf_x86_64_convert_load_reloc (bfd *abfd } bfd_put_8 (abfd, opcode, contents + roff - 2); + + /* For MOVRS zap the 0f38 or EVEX prefix, applying meaningless ES + segment overrides instead. When necessary also install the REX2 + prefix and payload (which may not have been written yet). */ + if (movrs) + { + bfd_put_8 (abfd, 0x26, contents + roff - movrs); + bfd_put_8 (abfd, 0x26, contents + roff - movrs + 1); + if (movrs == 6) + { + bfd_put_8 (abfd, 0xd5, contents + roff - 4); + bfd_put_8 (abfd, rex2, contents + roff - 3); + } + } } *r_type_p = r_type; @@ -2257,7 +2450,9 @@ elf_x86_64_scan_relocs (bfd *abfd, struc if ((r_type == R_X86_64_GOTPCREL || r_type == R_X86_64_GOTPCRELX || r_type == R_X86_64_REX_GOTPCRELX - || r_type == R_X86_64_CODE_4_GOTPCRELX) + || r_type == R_X86_64_CODE_4_GOTPCRELX + || r_type == R_X86_64_CODE_5_GOTPCRELX + || r_type == R_X86_64_CODE_6_GOTPCRELX) && (h == NULL || h->type != STT_GNU_IFUNC)) { Elf_Internal_Rela *irel = (Elf_Internal_Rela *) rel; @@ -2300,6 +2495,7 @@ elf_x86_64_scan_relocs (bfd *abfd, struc case R_X86_64_GOTTPOFF: case R_X86_64_CODE_4_GOTTPOFF: + case R_X86_64_CODE_5_GOTTPOFF: case R_X86_64_CODE_6_GOTTPOFF: if (!bfd_link_executable (info)) info->flags |= DF_STATIC_TLS; @@ -2310,6 +2506,8 @@ elf_x86_64_scan_relocs (bfd *abfd, struc case R_X86_64_GOTPCRELX: case R_X86_64_REX_GOTPCRELX: case R_X86_64_CODE_4_GOTPCRELX: + case R_X86_64_CODE_5_GOTPCRELX: + case R_X86_64_CODE_6_GOTPCRELX: case R_X86_64_TLSGD: case R_X86_64_GOT64: case R_X86_64_GOTPCREL64: @@ -2338,6 +2536,7 @@ elf_x86_64_scan_relocs (bfd *abfd, struc break; case R_X86_64_GOTTPOFF: case R_X86_64_CODE_4_GOTTPOFF: + case R_X86_64_CODE_5_GOTTPOFF: case R_X86_64_CODE_6_GOTTPOFF: tls_type = GOT_TLS_IE; break; @@ -2628,10 +2827,7 @@ elf_x86_64_scan_relocs (bfd *abfd, struc } break; - case R_X86_64_CODE_5_GOTPCRELX: - case R_X86_64_CODE_5_GOTTPOFF: case R_X86_64_CODE_5_GOTPC32_TLSDESC: - case R_X86_64_CODE_6_GOTPCRELX: case R_X86_64_CODE_6_GOTPC32_TLSDESC: { /* These relocations are added only for completeness and @@ -2936,6 +3132,8 @@ elf_x86_64_relocate_section (bfd *output case R_X86_64_GOTPCRELX: case R_X86_64_REX_GOTPCRELX: case R_X86_64_CODE_4_GOTPCRELX: + case R_X86_64_CODE_5_GOTPCRELX: + case R_X86_64_CODE_6_GOTPCRELX: case R_X86_64_GOTPCREL64: base_got = htab->elf.sgot; off = h->got.offset; @@ -3162,6 +3360,8 @@ elf_x86_64_relocate_section (bfd *output case R_X86_64_GOTPCRELX: case R_X86_64_REX_GOTPCRELX: case R_X86_64_CODE_4_GOTPCRELX: + case R_X86_64_CODE_5_GOTPCRELX: + case R_X86_64_CODE_6_GOTPCRELX: case R_X86_64_GOTPCREL64: /* Use global offset table entry as symbol value. */ case R_X86_64_GOTPLT64: @@ -3253,7 +3453,9 @@ elf_x86_64_relocate_section (bfd *output && (r_type == R_X86_64_GOTPCREL || r_type == R_X86_64_GOTPCRELX || r_type == R_X86_64_REX_GOTPCRELX - || r_type == R_X86_64_CODE_4_GOTPCRELX))) + || r_type == R_X86_64_CODE_4_GOTPCRELX + || r_type == R_X86_64_CODE_5_GOTPCRELX + || r_type == R_X86_64_CODE_6_GOTPCRELX))) relative_reloc = true; } } @@ -3292,6 +3494,8 @@ elf_x86_64_relocate_section (bfd *output && r_type != R_X86_64_GOTPCRELX && r_type != R_X86_64_REX_GOTPCRELX && r_type != R_X86_64_CODE_4_GOTPCRELX + && r_type != R_X86_64_CODE_5_GOTPCRELX + && r_type != R_X86_64_CODE_6_GOTPCRELX && r_type != R_X86_64_GOTPCREL64) relocation -= htab->elf.sgotplt->output_section->vma - htab->elf.sgotplt->output_offset; @@ -3714,6 +3918,7 @@ elf_x86_64_relocate_section (bfd *output case R_X86_64_TLSDESC_CALL: case R_X86_64_GOTTPOFF: case R_X86_64_CODE_4_GOTTPOFF: + case R_X86_64_CODE_5_GOTTPOFF: case R_X86_64_CODE_6_GOTTPOFF: tls_type = GOT_UNKNOWN; if (h == NULL && local_got_offsets) @@ -4031,10 +4236,12 @@ elf_x86_64_relocate_section (bfd *output Originally it can be one of: mov foo@gottpoff(%rip), %reg add foo@gottpoff(%rip), %reg + movrs foo@gottpoff(%rip), %reg We change it into: mov $foo@tpoff, %reg add $foo@tpoff, %reg - where reg is one of r16 to r31. */ + where reg is one of r16 to r31, except for MOVRS, where + it's not one of r8 to r31 and no REX byte is present. */ unsigned int rex2, type, reg; unsigned int rex2_mask = REX_R | REX_R << 4; @@ -4049,7 +4256,16 @@ elf_x86_64_relocate_section (bfd *output /* Move the R bits to the B bits in REX2 payload byte. */ if (type == 0x8b) - type = 0xc7; + { + /* For MOVRS emit meaningless ES prefixes. */ + if (bfd_get_8 (input_bfd, contents + roff - 4) == 0x0f) + { + bfd_put_8 (output_bfd, 0x26, contents + roff - 4); + rex2 = 0x26; + rex2_mask = 0; + } + type = 0xc7; + } else type = 0x81; bfd_put_8 (output_bfd, @@ -4065,6 +4281,37 @@ elf_x86_64_relocate_section (bfd *output contents + roff); continue; } + else if (r_type == R_X86_64_CODE_5_GOTTPOFF) + { + /* IE->LE transition: + Originally it is + movrs foo@gottpoff(%rip), %reg + We change it into: + mov $foo@tpoff, %reg + where reg isn't one of r16 to r31, but a REX + byte is present. */ + unsigned int rex = bfd_get_8 (input_bfd, contents + roff - 5); + + /* Move REX.R to REX.B. */ + rex = (rex & ~(REX_R | REX_B)) + | ((rex & REX_R) / (REX_R / REX_B)); + + unsigned int reg = bfd_get_8 (input_bfd, contents + roff - 1); + reg >>= 3; + + /* Replace 0f38 by meaningless ES prefixes, shifting the REX + prefix forward. */ + bfd_put_8 (output_bfd, 0x26, contents + roff - 5); + bfd_put_8 (output_bfd, 0x26, contents + roff - 4); + bfd_put_8 (output_bfd, rex, contents + roff - 3); + bfd_put_8 (output_bfd, 0xc7, contents + roff - 2); + bfd_put_8 (output_bfd, 0xc0 | reg, contents + roff - 1); + + bfd_put_32 (output_bfd, + elf_x86_64_tpoff (info, relocation), + contents + roff); + continue; + } else if (r_type == R_X86_64_CODE_6_GOTTPOFF) { /* IE->LE transition: @@ -4072,18 +4319,53 @@ elf_x86_64_relocate_section (bfd *output add %reg1, foo@gottpoff(%rip), %reg2 or add foo@gottpoff(%rip), %reg1, %reg2 + or + movrs foo@gottpoff(%rip), %reg We change it into: add $foo@tpoff, %reg1, %reg2 - */ - unsigned int reg, byte1; + mov $foo@tpoff, %reg + where reg is one of r16 to r31. */ + unsigned int type, reg, byte1; unsigned int updated_byte1; if (roff < 6) goto corrupt_input; + byte1 = bfd_get_8 (input_bfd, contents + roff - 5); + type = bfd_get_8 (input_bfd, contents + roff - 2); + reg = bfd_get_8 (input_bfd, contents + roff - 1); + reg >>= 3; + + if (type == 0x8b) + { + /* Convert MOVRS to REX2-encoded MOV. */ + unsigned int rex2 = 0; + + /* Move the EVEX R bits to the REX2 B ones. */ + if (!(byte1 & (1 << 7))) + rex2 |= REX_B; + if (!(byte1 & (1 << 4))) + rex2 |= REX_B << 4; + /* Propagate the EVEX W bit to the REX2 one. */ + type = bfd_get_8 (input_bfd, contents + roff - 4); + if (type & (1 << 7)) + rex2 |= REX_W; + + + bfd_put_8 (output_bfd, 0x26, contents + roff - 6); + bfd_put_8 (output_bfd, 0x26, contents + roff - 5); + bfd_put_8 (output_bfd, 0xd5, contents + roff - 4); + bfd_put_8 (output_bfd, rex2, contents + roff - 3); + bfd_put_8 (output_bfd, 0xc7, contents + roff - 2); + bfd_put_8 (output_bfd, 0xc0 | reg, contents + roff - 1); + bfd_put_32 (output_bfd, + elf_x86_64_tpoff (info, relocation), + contents + roff); + continue; + } + /* Move the R bits to the B bits in EVEX payload byte 1. */ - byte1 = bfd_get_8 (input_bfd, contents + roff - 5); updated_byte1 = byte1; /* Set the R bits since they is inverted. */ @@ -4095,9 +4377,6 @@ elf_x86_64_relocate_section (bfd *output if ((byte1 & (1 << 4)) == 0) updated_byte1 |= 1 << 3; - reg = bfd_get_8 (input_bfd, contents + roff - 1); - reg >>= 3; - bfd_put_8 (output_bfd, updated_byte1, contents + roff - 5); bfd_put_8 (output_bfd, 0x81, --- a/bfd/elfxx-x86.c +++ b/bfd/elfxx-x86.c @@ -3308,19 +3308,19 @@ _bfd_x86_elf_link_report_tls_transition_ asect); break; - case elf_x86_tls_error_add: + case elf_x86_tls_error_add_mov: info->callbacks->einfo /* xgettext:c-format */ (_("%pB(%pA+0x%v): relocation %s against `%s' must be used " - "in ADD only\n"), + "in ADD or MOV only\n"), abfd, asect, rel->r_offset, from_reloc_name, name); break; - case elf_x86_tls_error_add_mov: + case elf_x86_tls_error_add_movrs: info->callbacks->einfo /* xgettext:c-format */ (_("%pB(%pA+0x%v): relocation %s against `%s' must be used " - "in ADD or MOV only\n"), + "in ADD or MOVRS only\n"), abfd, asect, rel->r_offset, from_reloc_name, name); break; --- a/bfd/elfxx-x86.h +++ b/bfd/elfxx-x86.h @@ -777,8 +777,8 @@ struct elf_x86_plt enum elf_x86_tls_error_type { elf_x86_tls_error_none, - elf_x86_tls_error_add, elf_x86_tls_error_add_mov, + elf_x86_tls_error_add_movrs, elf_x86_tls_error_add_sub_mov, elf_x86_tls_error_indirect_call, elf_x86_tls_error_lea, --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3942,12 +3942,15 @@ tc_i386_fix_adjustable (fixS *fixP) || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX + || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTPCRELX + || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTPCRELX || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF + || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTTPOFF || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTTPOFF || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 @@ -3955,6 +3958,8 @@ tc_i386_fix_adjustable (fixS *fixP) || fixP->fx_r_type == BFD_RELOC_X86_64_GOT64 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC + || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC + || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) @@ -6761,11 +6766,13 @@ x86_check_tls_relocation (enum bfd_reloc /* Check GOTTPOFF access model: mov foo@gottpoff(%rip), %reg --> Memory Reg must be %rip. + movrs foo@gottpoff(%rip), %reg --> Memory Reg must be %rip. add foo@gottpoff(%rip), %reg --> Memory Reg must be %rip. add %reg1, foo@gottpoff(%rip), %reg2 --> Memory Reg must be %rip. add foo@gottpoff(%rip), %reg1, %reg2 --> Memory Reg must be %rip. */ - if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov) + if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov + && i.tm.mnem_off != MN_movrs) return x86_tls_error_insn; if (i.imm_operands || i.disp_operands != 1 @@ -12455,6 +12462,8 @@ output_insn (const struct last_insn *las relocation for GDesc -> IE/LE optimization. */ if (x86_elf_abi == X86_64_X32_ABI && !is_apx_rex2_encoding () + && (dot_insn () ? i.insn_opcode_space + : i.tm.opcode_space) == SPACE_BASE && i.operands == 2 && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) @@ -12827,9 +12836,12 @@ output_disp (fragS *insn_start_frag, off case BFD_RELOC_X86_64_TLSLD: case BFD_RELOC_X86_64_GOTTPOFF: case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: + case BFD_RELOC_X86_64_CODE_5_GOTTPOFF: case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: case BFD_RELOC_X86_64_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_TLSDESC_CALL: i.has_gotpc_tls_reloc = true; default: @@ -12844,16 +12856,6 @@ output_disp (fragS *insn_start_frag, off && !i.prefix[ADDR_PREFIX]) fixP->fx_signed = 1; - if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF - && i.tm.opcode_space == SPACE_MAP4) - { - /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is - allowed in md_assemble. Set fx_tcbit2 for EVEX - prefix. */ - fixP->fx_tcbit2 = 1; - continue; - } - if (i.base_reg && i.base_reg->reg_num == RegIP) { if (reloc_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC) @@ -12869,35 +12871,57 @@ output_disp (fragS *insn_start_frag, off else if (object_64bit) continue; - /* Check for "call/jmp *mem", "mov mem, %reg", + /* Check for "call/jmp *mem", "mov mem, %reg", "movrs mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions without data prefix. Always generate R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ + unsigned int space = dot_insn () ? i.insn_opcode_space + : i.tm.opcode_space; if (i.prefix[DATA_PREFIX] == 0 && (i.rm.mode == 2 || (i.rm.mode == 0 && i.rm.regmem == 5)) - && i.tm.opcode_space == SPACE_BASE - && ((i.operands == 1 + && ((space == SPACE_BASE + && i.operands == 1 && i.tm.base_opcode == 0xff && (i.rm.reg == 2 || i.rm.reg == 4)) - || (i.operands == 2 - && (i.tm.base_opcode == 0x8b - || i.tm.base_opcode == 0x85 - || (i.tm.base_opcode & ~0x38) == 0x03)))) + || ((space == SPACE_BASE + || space == SPACE_0F38 + || space == SPACE_MAP4) + && i.operands == 2 + && i.tm.base_opcode == 0x8b) + || ((space == SPACE_BASE + || space == SPACE_MAP4) + && i.operands >= 2 + && (i.tm.base_opcode == 0x85 + || (i.tm.base_opcode + | (i.operands > 2 ? 0x3a : 0x38)) == 0x3b)))) { if (object_64bit) { if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF) { - /* Set fx_tcbit for REX2 prefix. */ - if (is_apx_rex2_encoding ()) + if (space == SPACE_MAP4) + fixP->fx_tcbit3 = 1; + else if (space == SPACE_0F38 && i.rex) + fixP->fx_tcbit2 = 1; + else if (space == SPACE_0F38 || is_apx_rex2_encoding ()) fixP->fx_tcbit = 1; } else if (generate_relax_relocations) { - /* Set fx_tcbit3 for REX2 prefix. */ - if (is_apx_rex2_encoding ()) + if (space == SPACE_MAP4) + { + fixP->fx_tcbit3 = 1; + fixP->fx_tcbit2 = 1; + } + else if (space == SPACE_0F38) + { + fixP->fx_tcbit3 = 1; + if (i.rex) + fixP->fx_tcbit = 1; + } + else if (is_apx_rex2_encoding ()) fixP->fx_tcbit3 = 1; else if (i.rex) fixP->fx_tcbit2 = 1; @@ -16323,9 +16347,12 @@ md_apply_fix (fixS *fixP, valueT *valP, case BFD_RELOC_X86_64_TLSLD: case BFD_RELOC_X86_64_GOTTPOFF: case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: + case BFD_RELOC_X86_64_CODE_5_GOTTPOFF: case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: case BFD_RELOC_X86_64_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC: value = 0; /* Fully resolved at runtime. No addend. */ /* Fallthrough */ case BFD_RELOC_386_TLS_LE: @@ -17947,20 +17974,25 @@ i386_validate_fix (fixS *fixp) /* BFD_RELOC_X86_64_GOTTPOFF: 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF - 2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF + 2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_5_GOTTPOFF + 3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF BFD_RELOC_X86_64_GOTPC32_TLSDESC: 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC BFD_RELOC_32_PCREL: - 1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX - 2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX - 3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX - 4. else -> BFD_RELOC_X86_64_GOTPCREL + 1. fx_tcbit && fx_tcbit3 -> BFD_RELOC_X86_64_CODE_5_GOTPCRELX + 2. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX + 3. fx_tcbit2 && fx_tcbit3 -> BFD_RELOC_X86_64_CODE_6_GOTPCRELX + 4. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX + 5. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX + 6. else -> BFD_RELOC_X86_64_GOTPCREL */ if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF) { if (fixp->fx_tcbit) fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF; else if (fixp->fx_tcbit2) + fixp->fx_r_type = BFD_RELOC_X86_64_CODE_5_GOTTPOFF; + else if (fixp->fx_tcbit3) fixp->fx_r_type = BFD_RELOC_X86_64_CODE_6_GOTTPOFF; } else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC @@ -17978,9 +18010,13 @@ i386_validate_fix (fixS *fixp) abort (); #ifdef OBJ_ELF if (fixp->fx_tcbit) - fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCRELX; + fixp->fx_r_type = fixp->fx_tcbit3 + ? BFD_RELOC_X86_64_CODE_5_GOTPCRELX + : BFD_RELOC_X86_64_GOTPCRELX; else if (fixp->fx_tcbit2) - fixp->fx_r_type = BFD_RELOC_X86_64_REX_GOTPCRELX; + fixp->fx_r_type = fixp->fx_tcbit3 + ? BFD_RELOC_X86_64_CODE_6_GOTPCRELX + : BFD_RELOC_X86_64_REX_GOTPCRELX; else if (fixp->fx_tcbit3) fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX; else @@ -18091,6 +18127,8 @@ tc_gen_reloc (asection *section ATTRIBUT case BFD_RELOC_X86_64_GOTPCRELX: case BFD_RELOC_X86_64_REX_GOTPCRELX: case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: + case BFD_RELOC_X86_64_CODE_5_GOTPCRELX: + case BFD_RELOC_X86_64_CODE_6_GOTPCRELX: case BFD_RELOC_386_PLT32: case BFD_RELOC_386_GOT32: case BFD_RELOC_386_GOT32X: @@ -18112,6 +18150,7 @@ tc_gen_reloc (asection *section ATTRIBUT case BFD_RELOC_X86_64_DTPOFF64: case BFD_RELOC_X86_64_GOTTPOFF: case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: + case BFD_RELOC_X86_64_CODE_5_GOTTPOFF: case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: case BFD_RELOC_X86_64_TPOFF32: case BFD_RELOC_X86_64_TPOFF64: @@ -18124,6 +18163,8 @@ tc_gen_reloc (asection *section ATTRIBUT case BFD_RELOC_X86_64_PLTOFF64: case BFD_RELOC_X86_64_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_TLSDESC_CALL: case BFD_RELOC_RVA: case BFD_RELOC_VTABLE_ENTRY: @@ -18253,13 +18294,18 @@ tc_gen_reloc (asection *section ATTRIBUT case BFD_RELOC_X86_64_GOTPCRELX: case BFD_RELOC_X86_64_REX_GOTPCRELX: case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: + case BFD_RELOC_X86_64_CODE_5_GOTPCRELX: + case BFD_RELOC_X86_64_CODE_6_GOTPCRELX: case BFD_RELOC_X86_64_TLSGD: case BFD_RELOC_X86_64_TLSLD: case BFD_RELOC_X86_64_GOTTPOFF: case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: + case BFD_RELOC_X86_64_CODE_5_GOTTPOFF: case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: case BFD_RELOC_X86_64_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC: + case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC: case BFD_RELOC_X86_64_TLSDESC_CALL: rel->addend = fixp->fx_offset - fixp->fx_size; break; --- a/gas/config/tc-i386.h +++ b/gas/config/tc-i386.h @@ -170,7 +170,9 @@ extern int tc_i386_fix_adjustable (struc || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL \ || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX \ || (FIX)->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX \ - || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX) + || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX \ + || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTPCRELX \ + || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTPCRELX) #define TC_FORCE_RELOCATION_ABS(FIX) \ (TC_FORCE_RELOCATION (FIX) \ @@ -179,7 +181,9 @@ extern int tc_i386_fix_adjustable (struc || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL \ || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX \ || (FIX)->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX \ - || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX) + || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX \ + || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTPCRELX \ + || (FIX)->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTPCRELX) extern void i386_start_line (void); #define md_start_line_hook i386_start_line --- a/ld/testsuite/ld-x86-64/apx-load1.s +++ b/ld/testsuite/ld-x86-64/apx-load1.s @@ -30,6 +30,7 @@ _start: subq bar@GOTPCREL(%rip), %r22 xorq bar@GOTPCREL(%rip), %r23 testq %r24, bar@GOTPCREL(%rip) + adcl foo@GOTPCREL(%rip), %r16d addl foo@GOTPCREL(%rip), %r17d andl foo@GOTPCREL(%rip), %r18d @@ -48,4 +49,74 @@ _start: subq foo@GOTPCREL(%rip), %r22 xorq foo@GOTPCREL(%rip), %r23 testq %r24, foo@GOTPCREL(%rip) + + {evex} adc bar@GOTPCREL(%rip), %r16d + {nf} add bar@GOTPCREL(%rip), %r17d + {nf} and bar@GOTPCREL(%rip), %r18d + ccmpt bar@GOTPCREL(%rip), %r19d + {nf} or bar@GOTPCREL(%rip), %r20d + {evex} sbb bar@GOTPCREL(%rip), %r21d + {nf} sub bar@GOTPCREL(%rip), %r22d + {nf} xor bar@GOTPCREL(%rip), %r23d + ctestt bar@GOTPCREL(%rip), %r24d + {evex} adc bar@GOTPCREL(%rip), %r16 + {nf} add bar@GOTPCREL(%rip), %r17 + {nf} and bar@GOTPCREL(%rip), %r18 + ccmpt bar@GOTPCREL(%rip), %r19 + {nf} or bar@GOTPCREL(%rip), %r20 + {evex} sbb bar@GOTPCREL(%rip), %r21 + {nf} sub bar@GOTPCREL(%rip), %r22 + {nf} xor bar@GOTPCREL(%rip), %r23 + ctestt bar@GOTPCREL(%rip), %r24 + + {evex} adc %r16d, bar@GOTPCREL(%rip) + {nf} add %r17d, bar@GOTPCREL(%rip) + {nf} and %r18d, bar@GOTPCREL(%rip) + ccmpt %r19d, bar@GOTPCREL(%rip) + {nf} or %r20d, bar@GOTPCREL(%rip) + {evex} sbb %r21d, bar@GOTPCREL(%rip) + {nf} sub %r22d, bar@GOTPCREL(%rip) + {nf} xor %r23d, bar@GOTPCREL(%rip) + ctestt %r24d, bar@GOTPCREL(%rip) + {evex} adc %r16, bar@GOTPCREL(%rip) + {nf} add %r17, bar@GOTPCREL(%rip) + {nf} and %r18, bar@GOTPCREL(%rip) + ccmpt %r19, bar@GOTPCREL(%rip) + {nf} or %r20, bar@GOTPCREL(%rip) + {evex} sbb %r21, bar@GOTPCREL(%rip) + {nf} sub %r22, bar@GOTPCREL(%rip) + {nf} xor %r23, bar@GOTPCREL(%rip) + ctestt %r24, bar@GOTPCREL(%rip) + + adc bar@GOTPCREL(%rip), %r16d, %eax + add bar@GOTPCREL(%rip), %r17d, %ecx + and bar@GOTPCREL(%rip), %r18d, %edx + or bar@GOTPCREL(%rip), %r19d, %ebx + sbb bar@GOTPCREL(%rip), %r20d, %esp + sub bar@GOTPCREL(%rip), %r21d, %ebp + xor bar@GOTPCREL(%rip), %r22d, %esi + adc bar@GOTPCREL(%rip), %r16, %rax + add bar@GOTPCREL(%rip), %r17, %rcx + and bar@GOTPCREL(%rip), %r18, %rdx + or bar@GOTPCREL(%rip), %r19, %rbx + sbb bar@GOTPCREL(%rip), %r20, %rsp + sub bar@GOTPCREL(%rip), %r21, %rbp + xor bar@GOTPCREL(%rip), %r22, %rsi + + adc %eax, bar@GOTPCREL(%rip), %r16d + add %ecx, bar@GOTPCREL(%rip), %r17d + and %edx, bar@GOTPCREL(%rip), %r18d + or %ebx, bar@GOTPCREL(%rip), %r19d + sbb %esp, bar@GOTPCREL(%rip), %r20d + sub %ebp, bar@GOTPCREL(%rip), %r21d + xor %esi, bar@GOTPCREL(%rip), %r22d + adc %rax, bar@GOTPCREL(%rip), %r16 + add %rcx, bar@GOTPCREL(%rip), %r17 + and %rdx, bar@GOTPCREL(%rip), %r18 + or %rbx, bar@GOTPCREL(%rip), %r19 + sbb %rsp, bar@GOTPCREL(%rip), %r20 + sub %rbp, bar@GOTPCREL(%rip), %r21 + xor %rsi, bar@GOTPCREL(%rip), %r22 + .size _start, .-_start + .p2align 12, 0x90 --- a/ld/testsuite/ld-x86-64/apx-load1a.d +++ b/ld/testsuite/ld-x86-64/apx-load1a.d @@ -7,48 +7,112 @@ SYMBOL TABLE: #... -0+6001d0 l O .data 0+1 bar +0+6..... l O .data 0+1 bar #... -0+6001d1 g O .data 0+1 foo +0+602021 g O .data 0+1 foo #... Disassembly of section .text: -0+4000b0 <_start>: - +[a-f0-9]+: d5 10 81 d0 d0 01 60 00 adc \$0x6001d0,%r16d - +[a-f0-9]+: d5 10 81 c1 d0 01 60 00 add \$0x6001d0,%r17d - +[a-f0-9]+: d5 10 81 e2 d0 01 60 00 and \$0x6001d0,%r18d - +[a-f0-9]+: d5 10 81 fb d0 01 60 00 cmp \$0x6001d0,%r19d - +[a-f0-9]+: d5 10 81 cc d0 01 60 00 or \$0x6001d0,%r20d - +[a-f0-9]+: d5 10 81 dd d0 01 60 00 sbb \$0x6001d0,%r21d - +[a-f0-9]+: d5 10 81 ee d0 01 60 00 sub \$0x6001d0,%r22d - +[a-f0-9]+: d5 10 81 f7 d0 01 60 00 xor \$0x6001d0,%r23d - +[a-f0-9]+: d5 11 f7 c0 d0 01 60 00 test \$0x6001d0,%r24d - +[a-f0-9]+: d5 18 81 d0 d0 01 60 00 adc \$0x6001d0,%r16 - +[a-f0-9]+: d5 18 81 c1 d0 01 60 00 add \$0x6001d0,%r17 - +[a-f0-9]+: d5 18 81 e2 d0 01 60 00 and \$0x6001d0,%r18 - +[a-f0-9]+: d5 18 81 fb d0 01 60 00 cmp \$0x6001d0,%r19 - +[a-f0-9]+: d5 18 81 cc d0 01 60 00 or \$0x6001d0,%r20 - +[a-f0-9]+: d5 18 81 dd d0 01 60 00 sbb \$0x6001d0,%r21 - +[a-f0-9]+: d5 18 81 ee d0 01 60 00 sub \$0x6001d0,%r22 - +[a-f0-9]+: d5 18 81 f7 d0 01 60 00 xor \$0x6001d0,%r23 - +[a-f0-9]+: d5 19 f7 c0 d0 01 60 00 test \$0x6001d0,%r24 - +[a-f0-9]+: d5 10 81 d0 d1 01 60 00 adc \$0x6001d1,%r16d - +[a-f0-9]+: d5 10 81 c1 d1 01 60 00 add \$0x6001d1,%r17d - +[a-f0-9]+: d5 10 81 e2 d1 01 60 00 and \$0x6001d1,%r18d - +[a-f0-9]+: d5 10 81 fb d1 01 60 00 cmp \$0x6001d1,%r19d - +[a-f0-9]+: d5 10 81 cc d1 01 60 00 or \$0x6001d1,%r20d - +[a-f0-9]+: d5 10 81 dd d1 01 60 00 sbb \$0x6001d1,%r21d - +[a-f0-9]+: d5 10 81 ee d1 01 60 00 sub \$0x6001d1,%r22d - +[a-f0-9]+: d5 10 81 f7 d1 01 60 00 xor \$0x6001d1,%r23d - +[a-f0-9]+: d5 11 f7 c0 d1 01 60 00 test \$0x6001d1,%r24d - +[a-f0-9]+: d5 18 81 d0 d1 01 60 00 adc \$0x6001d1,%r16 - +[a-f0-9]+: d5 18 81 c1 d1 01 60 00 add \$0x6001d1,%r17 - +[a-f0-9]+: d5 18 81 e2 d1 01 60 00 and \$0x6001d1,%r18 - +[a-f0-9]+: d5 18 81 fb d1 01 60 00 cmp \$0x6001d1,%r19 - +[a-f0-9]+: d5 18 81 cc d1 01 60 00 or \$0x6001d1,%r20 - +[a-f0-9]+: d5 18 81 dd d1 01 60 00 sbb \$0x6001d1,%r21 - +[a-f0-9]+: d5 18 81 ee d1 01 60 00 sub \$0x6001d1,%r22 - +[a-f0-9]+: d5 18 81 f7 d1 01 60 00 xor \$0x6001d1,%r23 - +[a-f0-9]+: d5 19 f7 c0 d1 01 60 00 test \$0x6001d1,%r24 +0+401000 <_start>: + +[a-f0-9]+: d5 10 81 d0 20 20 60 00 adc \$0x602020,%r16d + +[a-f0-9]+: d5 10 81 c1 20 20 60 00 add \$0x602020,%r17d + +[a-f0-9]+: d5 10 81 e2 20 20 60 00 and \$0x602020,%r18d + +[a-f0-9]+: d5 10 81 fb 20 20 60 00 cmp \$0x602020,%r19d + +[a-f0-9]+: d5 10 81 cc 20 20 60 00 or \$0x602020,%r20d + +[a-f0-9]+: d5 10 81 dd 20 20 60 00 sbb \$0x602020,%r21d + +[a-f0-9]+: d5 10 81 ee 20 20 60 00 sub \$0x602020,%r22d + +[a-f0-9]+: d5 10 81 f7 20 20 60 00 xor \$0x602020,%r23d + +[a-f0-9]+: d5 11 f7 c0 20 20 60 00 test \$0x602020,%r24d + +[a-f0-9]+: d5 18 81 d0 20 20 60 00 adc \$0x602020,%r16 + +[a-f0-9]+: d5 18 81 c1 20 20 60 00 add \$0x602020,%r17 + +[a-f0-9]+: d5 18 81 e2 20 20 60 00 and \$0x602020,%r18 + +[a-f0-9]+: d5 18 81 fb 20 20 60 00 cmp \$0x602020,%r19 + +[a-f0-9]+: d5 18 81 cc 20 20 60 00 or \$0x602020,%r20 + +[a-f0-9]+: d5 18 81 dd 20 20 60 00 sbb \$0x602020,%r21 + +[a-f0-9]+: d5 18 81 ee 20 20 60 00 sub \$0x602020,%r22 + +[a-f0-9]+: d5 18 81 f7 20 20 60 00 xor \$0x602020,%r23 + +[a-f0-9]+: d5 19 f7 c0 20 20 60 00 test \$0x602020,%r24 + +[a-f0-9]+: d5 10 81 d0 21 20 60 00 adc \$0x602021,%r16d + +[a-f0-9]+: d5 10 81 c1 21 20 60 00 add \$0x602021,%r17d + +[a-f0-9]+: d5 10 81 e2 21 20 60 00 and \$0x602021,%r18d + +[a-f0-9]+: d5 10 81 fb 21 20 60 00 cmp \$0x602021,%r19d + +[a-f0-9]+: d5 10 81 cc 21 20 60 00 or \$0x602021,%r20d + +[a-f0-9]+: d5 10 81 dd 21 20 60 00 sbb \$0x602021,%r21d + +[a-f0-9]+: d5 10 81 ee 21 20 60 00 sub \$0x602021,%r22d + +[a-f0-9]+: d5 10 81 f7 21 20 60 00 xor \$0x602021,%r23d + +[a-f0-9]+: d5 11 f7 c0 21 20 60 00 test \$0x602021,%r24d + +[a-f0-9]+: d5 18 81 d0 21 20 60 00 adc \$0x602021,%r16 + +[a-f0-9]+: d5 18 81 c1 21 20 60 00 add \$0x602021,%r17 + +[a-f0-9]+: d5 18 81 e2 21 20 60 00 and \$0x602021,%r18 + +[a-f0-9]+: d5 18 81 fb 21 20 60 00 cmp \$0x602021,%r19 + +[a-f0-9]+: d5 18 81 cc 21 20 60 00 or \$0x602021,%r20 + +[a-f0-9]+: d5 18 81 dd 21 20 60 00 sbb \$0x602021,%r21 + +[a-f0-9]+: d5 18 81 ee 21 20 60 00 sub \$0x602021,%r22 + +[a-f0-9]+: d5 18 81 f7 21 20 60 00 xor \$0x602021,%r23 + +[a-f0-9]+: d5 19 f7 c0 21 20 60 00 test \$0x602021,%r24 + +[a-f0-9]+: 62 6c 7c 08 81 d0 20 20 60 00 adc \$0x602020,%r16d + +[a-f0-9]+: 62 6c 7c 0c 81 c1 20 20 60 00 \{nf\} add \$0x602020,%r17d + +[a-f0-9]+: 62 6c 7c 0c 81 e2 20 20 60 00 \{nf\} and \$0x602020,%r18d + +[a-f0-9]+: 62 6c 04 0a 81 fb 20 20 60 00 ccmpt \{dfv=\} \$0x602020,%r19d + +[a-f0-9]+: 62 6c 7c 0c 81 cc 20 20 60 00 \{nf\} or \$0x602020,%r20d + +[a-f0-9]+: 62 6c 7c 08 81 dd 20 20 60 00 sbb \$0x602020,%r21d + +[a-f0-9]+: 62 6c 7c 0c 81 ee 20 20 60 00 \{nf\} sub \$0x602020,%r22d + +[a-f0-9]+: 62 6c 7c 0c 81 f7 20 20 60 00 \{nf\} xor \$0x602020,%r23d + +[a-f0-9]+: 62 4c 04 0a f7 c0 20 20 60 00 ctestt \{dfv=\} \$0x602020,%r24d + +[a-f0-9]+: 62 6c fc 08 81 d0 20 20 60 00 adc \$0x602020,%r16 + +[a-f0-9]+: 62 6c fc 0c 81 c1 20 20 60 00 \{nf\} add \$0x602020,%r17 + +[a-f0-9]+: 62 6c fc 0c 81 e2 20 20 60 00 \{nf\} and \$0x602020,%r18 + +[a-f0-9]+: 62 6c 84 0a 81 fb 20 20 60 00 ccmpt \{dfv=\} \$0x602020,%r19 + +[a-f0-9]+: 62 6c fc 0c 81 cc 20 20 60 00 \{nf\} or \$0x602020,%r20 + +[a-f0-9]+: 62 6c fc 08 81 dd 20 20 60 00 sbb \$0x602020,%r21 + +[a-f0-9]+: 62 6c fc 0c 81 ee 20 20 60 00 \{nf\} sub \$0x602020,%r22 + +[a-f0-9]+: 62 6c fc 0c 81 f7 20 20 60 00 \{nf\} xor \$0x602020,%r23 + +[a-f0-9]+: 62 4c 84 0a f7 c0 20 20 60 00 ctestt \{dfv=\} \$0x602020,%r24 + +[a-f0-9]+: 62 e4 7c 08 11 05 22 0e 20 00 adc %r16d,0x200e22\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 7c 0c 01 0d 18 0e 20 00 \{nf\} add %r17d,0x200e18\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 7c 0c 21 15 0e 0e 20 00 \{nf\} and %r18d,0x200e0e\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 04 0a 39 1d 04 0e 20 00 ccmpt \{dfv=\} %r19d,0x200e04\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 7c 0c 09 25 fa 0d 20 00 \{nf\} or %r20d,0x200dfa\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 7c 08 19 2d f0 0d 20 00 sbb %r21d,0x200df0\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 7c 0c 29 35 e6 0d 20 00 \{nf\} sub %r22d,0x200de6\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 7c 0c 31 3d dc 0d 20 00 \{nf\} xor %r23d,0x200ddc\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 4c 04 0a f7 c0 20 20 60 00 ctestt \{dfv=\} \$0x602020,%r24d + +[a-f0-9]+: 62 e4 fc 08 11 05 c8 0d 20 00 adc %r16,0x200dc8\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 fc 0c 01 0d be 0d 20 00 \{nf\} add %r17,0x200dbe\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 fc 0c 21 15 b4 0d 20 00 \{nf\} and %r18,0x200db4\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 84 0a 39 1d aa 0d 20 00 ccmpt \{dfv=\} %r19,0x200daa\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 fc 0c 09 25 a0 0d 20 00 \{nf\} or %r20,0x200da0\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 fc 08 19 2d 96 0d 20 00 sbb %r21,0x200d96\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 fc 0c 29 35 8c 0d 20 00 \{nf\} sub %r22,0x200d8c\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 e4 fc 0c 31 3d 82 0d 20 00 \{nf\} xor %r23,0x200d82\(%rip\) # 602000 <.*> + +[a-f0-9]+: 62 4c 84 0a f7 c0 20 20 60 00 ctestt \{dfv=\} \$0x602020,%r24 + +[a-f0-9]+: 62 6c 7c 18 81 d0 20 20 60 00 adc \$0x602020,%r16d,%eax + +[a-f0-9]+: 62 6c 74 18 81 c1 20 20 60 00 add \$0x602020,%r17d,%ecx + +[a-f0-9]+: 62 6c 6c 18 81 e2 20 20 60 00 and \$0x602020,%r18d,%edx + +[a-f0-9]+: 62 6c 64 18 81 cb 20 20 60 00 or \$0x602020,%r19d,%ebx + +[a-f0-9]+: 62 6c 5c 18 81 dc 20 20 60 00 sbb \$0x602020,%r20d,%esp + +[a-f0-9]+: 62 6c 54 18 81 ed 20 20 60 00 sub \$0x602020,%r21d,%ebp + +[a-f0-9]+: 62 6c 4c 18 81 f6 20 20 60 00 xor \$0x602020,%r22d,%esi + +[a-f0-9]+: 62 6c fc 18 81 d0 20 20 60 00 adc \$0x602020,%r16,%rax + +[a-f0-9]+: 62 6c f4 18 81 c1 20 20 60 00 add \$0x602020,%r17,%rcx + +[a-f0-9]+: 62 6c ec 18 81 e2 20 20 60 00 and \$0x602020,%r18,%rdx + +[a-f0-9]+: 62 6c e4 18 81 cb 20 20 60 00 or \$0x602020,%r19,%rbx + +[a-f0-9]+: 62 6c dc 18 81 dc 20 20 60 00 sbb \$0x602020,%r20,%rsp + +[a-f0-9]+: 62 6c d4 18 81 ed 20 20 60 00 sub \$0x602020,%r21,%rbp + +[a-f0-9]+: 62 6c cc 18 81 f6 20 20 60 00 xor \$0x602020,%r22,%rsi + +[a-f0-9]+: 62 64 7c 10 81 d0 20 20 60 00 adc \$0x602020,%eax,%r16d + +[a-f0-9]+: 62 64 74 10 81 c1 20 20 60 00 add \$0x602020,%ecx,%r17d + +[a-f0-9]+: 62 64 6c 10 81 e2 20 20 60 00 and \$0x602020,%edx,%r18d + +[a-f0-9]+: 62 64 64 10 81 cb 20 20 60 00 or \$0x602020,%ebx,%r19d + +[a-f0-9]+: 62 f4 5c 10 19 25 ba 0c 20 00 sbb %esp,0x200cba\(%rip\),%r20d # 602000 <.*> + +[a-f0-9]+: 62 f4 54 10 29 2d b0 0c 20 00 sub %ebp,0x200cb0\(%rip\),%r21d # 602000 <.*> + +[a-f0-9]+: 62 64 4c 10 81 f6 20 20 60 00 xor \$0x602020,%esi,%r22d + +[a-f0-9]+: 62 64 fc 10 81 d0 20 20 60 00 adc \$0x602020,%rax,%r16 + +[a-f0-9]+: 62 64 f4 10 81 c1 20 20 60 00 add \$0x602020,%rcx,%r17 + +[a-f0-9]+: 62 64 ec 10 81 e2 20 20 60 00 and \$0x602020,%rdx,%r18 + +[a-f0-9]+: 62 64 e4 10 81 cb 20 20 60 00 or \$0x602020,%rbx,%r19 + +[a-f0-9]+: 62 f4 dc 10 19 25 74 0c 20 00 sbb %rsp,0x200c74\(%rip\),%r20 # 602000 <.*> + +[a-f0-9]+: 62 f4 d4 10 29 2d 6a 0c 20 00 sub %rbp,0x200c6a\(%rip\),%r21 # 602000 <.*> + +[a-f0-9]+: 62 64 cc 10 81 f6 20 20 60 00 xor \$0x602020,%rsi,%r22 #pass --- a/ld/testsuite/ld-x86-64/apx-load1b.d +++ b/ld/testsuite/ld-x86-64/apx-load1b.d @@ -2,54 +2,4 @@ #as: --x32 -mrelax-relocations=yes #ld: -melf32_x86_64 -z max-page-size=0x200000 -z noseparate-code #objdump: -dw --sym - -.*: +file format .* - -SYMBOL TABLE: -#... -0+600194 l O .data 0+1 bar -#... -0+600195 g O .data 0+1 foo -#... - - -Disassembly of section .text: - -0+400074 <_start>: - +[a-f0-9]+: d5 10 81 d0 94 01 60 00 adc \$0x600194,%r16d - +[a-f0-9]+: d5 10 81 c1 94 01 60 00 add \$0x600194,%r17d - +[a-f0-9]+: d5 10 81 e2 94 01 60 00 and \$0x600194,%r18d - +[a-f0-9]+: d5 10 81 fb 94 01 60 00 cmp \$0x600194,%r19d - +[a-f0-9]+: d5 10 81 cc 94 01 60 00 or \$0x600194,%r20d - +[a-f0-9]+: d5 10 81 dd 94 01 60 00 sbb \$0x600194,%r21d - +[a-f0-9]+: d5 10 81 ee 94 01 60 00 sub \$0x600194,%r22d - +[a-f0-9]+: d5 10 81 f7 94 01 60 00 xor \$0x600194,%r23d - +[a-f0-9]+: d5 11 f7 c0 94 01 60 00 test \$0x600194,%r24d - +[a-f0-9]+: d5 18 81 d0 94 01 60 00 adc \$0x600194,%r16 - +[a-f0-9]+: d5 18 81 c1 94 01 60 00 add \$0x600194,%r17 - +[a-f0-9]+: d5 18 81 e2 94 01 60 00 and \$0x600194,%r18 - +[a-f0-9]+: d5 18 81 fb 94 01 60 00 cmp \$0x600194,%r19 - +[a-f0-9]+: d5 18 81 cc 94 01 60 00 or \$0x600194,%r20 - +[a-f0-9]+: d5 18 81 dd 94 01 60 00 sbb \$0x600194,%r21 - +[a-f0-9]+: d5 18 81 ee 94 01 60 00 sub \$0x600194,%r22 - +[a-f0-9]+: d5 18 81 f7 94 01 60 00 xor \$0x600194,%r23 - +[a-f0-9]+: d5 19 f7 c0 94 01 60 00 test \$0x600194,%r24 - +[a-f0-9]+: d5 10 81 d0 95 01 60 00 adc \$0x600195,%r16d - +[a-f0-9]+: d5 10 81 c1 95 01 60 00 add \$0x600195,%r17d - +[a-f0-9]+: d5 10 81 e2 95 01 60 00 and \$0x600195,%r18d - +[a-f0-9]+: d5 10 81 fb 95 01 60 00 cmp \$0x600195,%r19d - +[a-f0-9]+: d5 10 81 cc 95 01 60 00 or \$0x600195,%r20d - +[a-f0-9]+: d5 10 81 dd 95 01 60 00 sbb \$0x600195,%r21d - +[a-f0-9]+: d5 10 81 ee 95 01 60 00 sub \$0x600195,%r22d - +[a-f0-9]+: d5 10 81 f7 95 01 60 00 xor \$0x600195,%r23d - +[a-f0-9]+: d5 11 f7 c0 95 01 60 00 test \$0x600195,%r24d - +[a-f0-9]+: d5 18 81 d0 95 01 60 00 adc \$0x600195,%r16 - +[a-f0-9]+: d5 18 81 c1 95 01 60 00 add \$0x600195,%r17 - +[a-f0-9]+: d5 18 81 e2 95 01 60 00 and \$0x600195,%r18 - +[a-f0-9]+: d5 18 81 fb 95 01 60 00 cmp \$0x600195,%r19 - +[a-f0-9]+: d5 18 81 cc 95 01 60 00 or \$0x600195,%r20 - +[a-f0-9]+: d5 18 81 dd 95 01 60 00 sbb \$0x600195,%r21 - +[a-f0-9]+: d5 18 81 ee 95 01 60 00 sub \$0x600195,%r22 - +[a-f0-9]+: d5 18 81 f7 95 01 60 00 xor \$0x600195,%r23 - +[a-f0-9]+: d5 19 f7 c0 95 01 60 00 test \$0x600195,%r24 -#pass +#dump: apx-load1a.d --- a/ld/testsuite/ld-x86-64/apx-load1c.d +++ b/ld/testsuite/ld-x86-64/apx-load1c.d @@ -1,5 +1,5 @@ #source: apx-load1.s -#as: --64 +#as: --64 -mrelax-relocations=yes #ld: -shared -melf_x86_64 --hash-style=sysv -z max-page-size=0x200000 -z noseparate-code $NO_DT_RELR_LDFLAGS #objdump: -dw @@ -7,41 +7,105 @@ Disassembly of section .text: -0+188 <_start>: - +[a-f0-9]+: d5 40 13 05 f8 01 20 00 adc 0x2001f8\(%rip\),%r16d # 200388 <.*> - +[a-f0-9]+: d5 40 03 0d f0 01 20 00 add 0x2001f0\(%rip\),%r17d # 200388 <.*> - +[a-f0-9]+: d5 40 23 15 e8 01 20 00 and 0x2001e8\(%rip\),%r18d # 200388 <.*> - +[a-f0-9]+: d5 40 3b 1d e0 01 20 00 cmp 0x2001e0\(%rip\),%r19d # 200388 <.*> - +[a-f0-9]+: d5 40 0b 25 d8 01 20 00 or 0x2001d8\(%rip\),%r20d # 200388 <.*> - +[a-f0-9]+: d5 40 1b 2d d0 01 20 00 sbb 0x2001d0\(%rip\),%r21d # 200388 <.*> - +[a-f0-9]+: d5 40 2b 35 c8 01 20 00 sub 0x2001c8\(%rip\),%r22d # 200388 <.*> - +[a-f0-9]+: d5 40 33 3d c0 01 20 00 xor 0x2001c0\(%rip\),%r23d # 200388 <.*> - +[a-f0-9]+: d5 44 85 05 b8 01 20 00 test %r24d,0x2001b8\(%rip\) # 200388 <.*> - +[a-f0-9]+: d5 48 13 05 b0 01 20 00 adc 0x2001b0\(%rip\),%r16 # 200388 <.*> - +[a-f0-9]+: d5 48 03 0d a8 01 20 00 add 0x2001a8\(%rip\),%r17 # 200388 <.*> - +[a-f0-9]+: d5 48 23 15 a0 01 20 00 and 0x2001a0\(%rip\),%r18 # 200388 <.*> - +[a-f0-9]+: d5 48 3b 1d 98 01 20 00 cmp 0x200198\(%rip\),%r19 # 200388 <.*> - +[a-f0-9]+: d5 48 0b 25 90 01 20 00 or 0x200190\(%rip\),%r20 # 200388 <.*> - +[a-f0-9]+: d5 48 1b 2d 88 01 20 00 sbb 0x200188\(%rip\),%r21 # 200388 <.*> - +[a-f0-9]+: d5 48 2b 35 80 01 20 00 sub 0x200180\(%rip\),%r22 # 200388 <.*> - +[a-f0-9]+: d5 48 33 3d 78 01 20 00 xor 0x200178\(%rip\),%r23 # 200388 <.*> - +[a-f0-9]+: d5 4c 85 05 70 01 20 00 test %r24,0x200170\(%rip\) # 200388 <.*> - +[a-f0-9]+: d5 40 13 05 70 01 20 00 adc 0x200170\(%rip\),%r16d # 200390 <.*> - +[a-f0-9]+: d5 40 03 0d 68 01 20 00 add 0x200168\(%rip\),%r17d # 200390 <.*> - +[a-f0-9]+: d5 40 23 15 60 01 20 00 and 0x200160\(%rip\),%r18d # 200390 <.*> - +[a-f0-9]+: d5 40 3b 1d 58 01 20 00 cmp 0x200158\(%rip\),%r19d # 200390 <.*> - +[a-f0-9]+: d5 40 0b 25 50 01 20 00 or 0x200150\(%rip\),%r20d # 200390 <.*> - +[a-f0-9]+: d5 40 1b 2d 48 01 20 00 sbb 0x200148\(%rip\),%r21d # 200390 <.*> - +[a-f0-9]+: d5 40 2b 35 40 01 20 00 sub 0x200140\(%rip\),%r22d # 200390 <.*> - +[a-f0-9]+: d5 40 33 3d 38 01 20 00 xor 0x200138\(%rip\),%r23d # 200390 <.*> - +[a-f0-9]+: d5 44 85 05 30 01 20 00 test %r24d,0x200130\(%rip\) # 200390 <.*> - +[a-f0-9]+: d5 48 13 05 28 01 20 00 adc 0x200128\(%rip\),%r16 # 200390 <.*> - +[a-f0-9]+: d5 48 03 0d 20 01 20 00 add 0x200120\(%rip\),%r17 # 200390 <.*> - +[a-f0-9]+: d5 48 23 15 18 01 20 00 and 0x200118\(%rip\),%r18 # 200390 <.*> - +[a-f0-9]+: d5 48 3b 1d 10 01 20 00 cmp 0x200110\(%rip\),%r19 # 200390 <.*> - +[a-f0-9]+: d5 48 0b 25 08 01 20 00 or 0x200108\(%rip\),%r20 # 200390 <.*> - +[a-f0-9]+: d5 48 1b 2d 00 01 20 00 sbb 0x200100\(%rip\),%r21 # 200390 <.*> - +[a-f0-9]+: d5 48 2b 35 f8 00 20 00 sub 0x2000f8\(%rip\),%r22 # 200390 <.*> - +[a-f0-9]+: d5 48 33 3d f0 00 20 00 xor 0x2000f0\(%rip\),%r23 # 200390 <.*> - +[a-f0-9]+: d5 4c 85 05 e8 00 20 00 test %r24,0x2000e8\(%rip\) # 200390 <.*> +0+1000 <_start>: + +[a-f0-9]+: d5 40 13 05 d8 10 20 00 adc 0x2010d8\(%rip\),%r16d # 2020e0 <.*> + +[a-f0-9]+: d5 40 03 0d d0 10 20 00 add 0x2010d0\(%rip\),%r17d # 2020e0 <.*> + +[a-f0-9]+: d5 40 23 15 c8 10 20 00 and 0x2010c8\(%rip\),%r18d # 2020e0 <.*> + +[a-f0-9]+: d5 40 3b 1d c0 10 20 00 cmp 0x2010c0\(%rip\),%r19d # 2020e0 <.*> + +[a-f0-9]+: d5 40 0b 25 b8 10 20 00 or 0x2010b8\(%rip\),%r20d # 2020e0 <.*> + +[a-f0-9]+: d5 40 1b 2d b0 10 20 00 sbb 0x2010b0\(%rip\),%r21d # 2020e0 <.*> + +[a-f0-9]+: d5 40 2b 35 a8 10 20 00 sub 0x2010a8\(%rip\),%r22d # 2020e0 <.*> + +[a-f0-9]+: d5 40 33 3d a0 10 20 00 xor 0x2010a0\(%rip\),%r23d # 2020e0 <.*> + +[a-f0-9]+: d5 44 85 05 98 10 20 00 test %r24d,0x201098\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: d5 48 13 05 90 10 20 00 adc 0x201090\(%rip\),%r16 # 2020e0 <.*> + +[a-f0-9]+: d5 48 03 0d 88 10 20 00 add 0x201088\(%rip\),%r17 # 2020e0 <.*> + +[a-f0-9]+: d5 48 23 15 80 10 20 00 and 0x201080\(%rip\),%r18 # 2020e0 <.*> + +[a-f0-9]+: d5 48 3b 1d 78 10 20 00 cmp 0x201078\(%rip\),%r19 # 2020e0 <.*> + +[a-f0-9]+: d5 48 0b 25 70 10 20 00 or 0x201070\(%rip\),%r20 # 2020e0 <.*> + +[a-f0-9]+: d5 48 1b 2d 68 10 20 00 sbb 0x201068\(%rip\),%r21 # 2020e0 <.*> + +[a-f0-9]+: d5 48 2b 35 60 10 20 00 sub 0x201060\(%rip\),%r22 # 2020e0 <.*> + +[a-f0-9]+: d5 48 33 3d 58 10 20 00 xor 0x201058\(%rip\),%r23 # 2020e0 <.*> + +[a-f0-9]+: d5 4c 85 05 50 10 20 00 test %r24,0x201050\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: d5 40 13 05 50 10 20 00 adc 0x201050\(%rip\),%r16d # 2020e8 <.*> + +[a-f0-9]+: d5 40 03 0d 48 10 20 00 add 0x201048\(%rip\),%r17d # 2020e8 <.*> + +[a-f0-9]+: d5 40 23 15 40 10 20 00 and 0x201040\(%rip\),%r18d # 2020e8 <.*> + +[a-f0-9]+: d5 40 3b 1d 38 10 20 00 cmp 0x201038\(%rip\),%r19d # 2020e8 <.*> + +[a-f0-9]+: d5 40 0b 25 30 10 20 00 or 0x201030\(%rip\),%r20d # 2020e8 <.*> + +[a-f0-9]+: d5 40 1b 2d 28 10 20 00 sbb 0x201028\(%rip\),%r21d # 2020e8 <.*> + +[a-f0-9]+: d5 40 2b 35 20 10 20 00 sub 0x201020\(%rip\),%r22d # 2020e8 <.*> + +[a-f0-9]+: d5 40 33 3d 18 10 20 00 xor 0x201018\(%rip\),%r23d # 2020e8 <.*> + +[a-f0-9]+: d5 44 85 05 10 10 20 00 test %r24d,0x201010\(%rip\) # 2020e8 <.*> + +[a-f0-9]+: d5 48 13 05 08 10 20 00 adc 0x201008\(%rip\),%r16 # 2020e8 <.*> + +[a-f0-9]+: d5 48 03 0d 00 10 20 00 add 0x201000\(%rip\),%r17 # 2020e8 <.*> + +[a-f0-9]+: d5 48 23 15 f8 0f 20 00 and 0x200ff8\(%rip\),%r18 # 2020e8 <.*> + +[a-f0-9]+: d5 48 3b 1d f0 0f 20 00 cmp 0x200ff0\(%rip\),%r19 # 2020e8 <.*> + +[a-f0-9]+: d5 48 0b 25 e8 0f 20 00 or 0x200fe8\(%rip\),%r20 # 2020e8 <.*> + +[a-f0-9]+: d5 48 1b 2d e0 0f 20 00 sbb 0x200fe0\(%rip\),%r21 # 2020e8 <.*> + +[a-f0-9]+: d5 48 2b 35 d8 0f 20 00 sub 0x200fd8\(%rip\),%r22 # 2020e8 <.*> + +[a-f0-9]+: d5 48 33 3d d0 0f 20 00 xor 0x200fd0\(%rip\),%r23 # 2020e8 <.*> + +[a-f0-9]+: d5 4c 85 05 c8 0f 20 00 test %r24,0x200fc8\(%rip\) # 2020e8 <.*> + +[a-f0-9]+: 62 e4 7c 08 13 05 b6 0f 20 00 adc 0x200fb6\(%rip\),%r16d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 03 0d ac 0f 20 00 \{nf\} add 0x200fac\(%rip\),%r17d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 23 15 a2 0f 20 00 \{nf\} and 0x200fa2\(%rip\),%r18d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 04 0a 3b 1d 98 0f 20 00 ccmpt \{dfv=\} 0x200f98\(%rip\),%r19d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 0b 25 8e 0f 20 00 \{nf\} or 0x200f8e\(%rip\),%r20d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 08 1b 2d 84 0f 20 00 sbb 0x200f84\(%rip\),%r21d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 2b 35 7a 0f 20 00 \{nf\} sub 0x200f7a\(%rip\),%r22d # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 33 3d 70 0f 20 00 \{nf\} xor 0x200f70\(%rip\),%r23d # 2020e0 <.*> + +[a-f0-9]+: 62 64 04 0a 85 05 66 0f 20 00 ctestt \{dfv=\} %r24d,0x200f66\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 08 13 05 5c 0f 20 00 adc 0x200f5c\(%rip\),%r16 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 03 0d 52 0f 20 00 \{nf\} add 0x200f52\(%rip\),%r17 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 23 15 48 0f 20 00 \{nf\} and 0x200f48\(%rip\),%r18 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 84 0a 3b 1d 3e 0f 20 00 ccmpt \{dfv=\} 0x200f3e\(%rip\),%r19 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 0b 25 34 0f 20 00 \{nf\} or 0x200f34\(%rip\),%r20 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 08 1b 2d 2a 0f 20 00 sbb 0x200f2a\(%rip\),%r21 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 2b 35 20 0f 20 00 \{nf\} sub 0x200f20\(%rip\),%r22 # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 33 3d 16 0f 20 00 \{nf\} xor 0x200f16\(%rip\),%r23 # 2020e0 <.*> + +[a-f0-9]+: 62 64 84 0a 85 05 0c 0f 20 00 ctestt \{dfv=\} %r24,0x200f0c\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 08 11 05 02 0f 20 00 adc %r16d,0x200f02\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 01 0d f8 0e 20 00 \{nf\} add %r17d,0x200ef8\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 21 15 ee 0e 20 00 \{nf\} and %r18d,0x200eee\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 04 0a 39 1d e4 0e 20 00 ccmpt \{dfv=\} %r19d,0x200ee4\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 09 25 da 0e 20 00 \{nf\} or %r20d,0x200eda\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 08 19 2d d0 0e 20 00 sbb %r21d,0x200ed0\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 29 35 c6 0e 20 00 \{nf\} sub %r22d,0x200ec6\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 0c 31 3d bc 0e 20 00 \{nf\} xor %r23d,0x200ebc\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 64 04 0a 85 05 b2 0e 20 00 ctestt \{dfv=\} %r24d,0x200eb2\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 08 11 05 a8 0e 20 00 adc %r16,0x200ea8\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 01 0d 9e 0e 20 00 \{nf\} add %r17,0x200e9e\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 21 15 94 0e 20 00 \{nf\} and %r18,0x200e94\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 84 0a 39 1d 8a 0e 20 00 ccmpt \{dfv=\} %r19,0x200e8a\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 09 25 80 0e 20 00 \{nf\} or %r20,0x200e80\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 08 19 2d 76 0e 20 00 sbb %r21,0x200e76\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 29 35 6c 0e 20 00 \{nf\} sub %r22,0x200e6c\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 0c 31 3d 62 0e 20 00 \{nf\} xor %r23,0x200e62\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 64 84 0a 85 05 58 0e 20 00 ctestt \{dfv=\} %r24,0x200e58\(%rip\) # 2020e0 <.*> + +[a-f0-9]+: 62 e4 7c 18 13 05 4e 0e 20 00 adc 0x200e4e\(%rip\),%r16d,%eax # 2020e0 <.*> + +[a-f0-9]+: 62 e4 74 18 03 0d 44 0e 20 00 add 0x200e44\(%rip\),%r17d,%ecx # 2020e0 <.*> + +[a-f0-9]+: 62 e4 6c 18 23 15 3a 0e 20 00 and 0x200e3a\(%rip\),%r18d,%edx # 2020e0 <.*> + +[a-f0-9]+: 62 e4 64 18 0b 1d 30 0e 20 00 or 0x200e30\(%rip\),%r19d,%ebx # 2020e0 <.*> + +[a-f0-9]+: 62 e4 5c 18 1b 25 26 0e 20 00 sbb 0x200e26\(%rip\),%r20d,%esp # 2020e0 <.*> + +[a-f0-9]+: 62 e4 54 18 2b 2d 1c 0e 20 00 sub 0x200e1c\(%rip\),%r21d,%ebp # 2020e0 <.*> + +[a-f0-9]+: 62 e4 4c 18 33 35 12 0e 20 00 xor 0x200e12\(%rip\),%r22d,%esi # 2020e0 <.*> + +[a-f0-9]+: 62 e4 fc 18 13 05 08 0e 20 00 adc 0x200e08\(%rip\),%r16,%rax # 2020e0 <.*> + +[a-f0-9]+: 62 e4 f4 18 03 0d fe 0d 20 00 add 0x200dfe\(%rip\),%r17,%rcx # 2020e0 <.*> + +[a-f0-9]+: 62 e4 ec 18 23 15 f4 0d 20 00 and 0x200df4\(%rip\),%r18,%rdx # 2020e0 <.*> + +[a-f0-9]+: 62 e4 e4 18 0b 1d ea 0d 20 00 or 0x200dea\(%rip\),%r19,%rbx # 2020e0 <.*> + +[a-f0-9]+: 62 e4 dc 18 1b 25 e0 0d 20 00 sbb 0x200de0\(%rip\),%r20,%rsp # 2020e0 <.*> + +[a-f0-9]+: 62 e4 d4 18 2b 2d d6 0d 20 00 sub 0x200dd6\(%rip\),%r21,%rbp # 2020e0 <.*> + +[a-f0-9]+: 62 e4 cc 18 33 35 cc 0d 20 00 xor 0x200dcc\(%rip\),%r22,%rsi # 2020e0 <.*> + +[a-f0-9]+: 62 f4 7c 10 11 05 c2 0d 20 00 adc %eax,0x200dc2\(%rip\),%r16d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 74 10 01 0d b8 0d 20 00 add %ecx,0x200db8\(%rip\),%r17d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 6c 10 21 15 ae 0d 20 00 and %edx,0x200dae\(%rip\),%r18d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 64 10 09 1d a4 0d 20 00 or %ebx,0x200da4\(%rip\),%r19d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 5c 10 19 25 9a 0d 20 00 sbb %esp,0x200d9a\(%rip\),%r20d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 54 10 29 2d 90 0d 20 00 sub %ebp,0x200d90\(%rip\),%r21d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 4c 10 31 35 86 0d 20 00 xor %esi,0x200d86\(%rip\),%r22d # 2020e0 <.*> + +[a-f0-9]+: 62 f4 fc 10 11 05 7c 0d 20 00 adc %rax,0x200d7c\(%rip\),%r16 # 2020e0 <.*> + +[a-f0-9]+: 62 f4 f4 10 01 0d 72 0d 20 00 add %rcx,0x200d72\(%rip\),%r17 # 2020e0 <.*> + +[a-f0-9]+: 62 f4 ec 10 21 15 68 0d 20 00 and %rdx,0x200d68\(%rip\),%r18 # 2020e0 <.*> + +[a-f0-9]+: 62 f4 e4 10 09 1d 5e 0d 20 00 or %rbx,0x200d5e\(%rip\),%r19 # 2020e0 <.*> + +[a-f0-9]+: 62 f4 dc 10 19 25 54 0d 20 00 sbb %rsp,0x200d54\(%rip\),%r20 # 2020e0 <.*> + +[a-f0-9]+: 62 f4 d4 10 29 2d 4a 0d 20 00 sub %rbp,0x200d4a\(%rip\),%r21 # 2020e0 <.*> + +[a-f0-9]+: 62 f4 cc 10 31 35 40 0d 20 00 xor %rsi,0x200d40\(%rip\),%r22 # 2020e0 <.*> #pass --- a/ld/testsuite/ld-x86-64/apx-load1d.d +++ b/ld/testsuite/ld-x86-64/apx-load1d.d @@ -1,5 +1,5 @@ #source: apx-load1.s -#as: --x32 +#as: --x32 -mrelax-relocations=yes #ld: -shared -melf32_x86_64 --hash-style=sysv -z max-page-size=0x200000 -z noseparate-code $NO_DT_RELR_LDFLAGS #objdump: -dw @@ -7,41 +7,105 @@ Disassembly of section .text: -0+100 <_start>: - +[a-f0-9]+: d5 40 13 05 88 01 20 00 adc 0x200188\(%rip\),%r16d # 200290 <.*> - +[a-f0-9]+: d5 40 03 0d 80 01 20 00 add 0x200180\(%rip\),%r17d # 200290 <.*> - +[a-f0-9]+: d5 40 23 15 78 01 20 00 and 0x200178\(%rip\),%r18d # 200290 <.*> - +[a-f0-9]+: d5 40 3b 1d 70 01 20 00 cmp 0x200170\(%rip\),%r19d # 200290 <.*> - +[a-f0-9]+: d5 40 0b 25 68 01 20 00 or 0x200168\(%rip\),%r20d # 200290 <.*> - +[a-f0-9]+: d5 40 1b 2d 60 01 20 00 sbb 0x200160\(%rip\),%r21d # 200290 <.*> - +[a-f0-9]+: d5 40 2b 35 58 01 20 00 sub 0x200158\(%rip\),%r22d # 200290 <.*> - +[a-f0-9]+: d5 40 33 3d 50 01 20 00 xor 0x200150\(%rip\),%r23d # 200290 <.*> - +[a-f0-9]+: d5 44 85 05 48 01 20 00 test %r24d,0x200148\(%rip\) # 200290 <.*> - +[a-f0-9]+: d5 48 13 05 40 01 20 00 adc 0x200140\(%rip\),%r16 # 200290 <.*> - +[a-f0-9]+: d5 48 03 0d 38 01 20 00 add 0x200138\(%rip\),%r17 # 200290 <.*> - +[a-f0-9]+: d5 48 23 15 30 01 20 00 and 0x200130\(%rip\),%r18 # 200290 <.*> - +[a-f0-9]+: d5 48 3b 1d 28 01 20 00 cmp 0x200128\(%rip\),%r19 # 200290 <.*> - +[a-f0-9]+: d5 48 0b 25 20 01 20 00 or 0x200120\(%rip\),%r20 # 200290 <.*> - +[a-f0-9]+: d5 48 1b 2d 18 01 20 00 sbb 0x200118\(%rip\),%r21 # 200290 <.*> - +[a-f0-9]+: d5 48 2b 35 10 01 20 00 sub 0x200110\(%rip\),%r22 # 200290 <.*> - +[a-f0-9]+: d5 48 33 3d 08 01 20 00 xor 0x200108\(%rip\),%r23 # 200290 <.*> - +[a-f0-9]+: d5 4c 85 05 00 01 20 00 test %r24,0x200100\(%rip\) # 200290 <.*> - +[a-f0-9]+: d5 40 13 05 00 01 20 00 adc 0x200100\(%rip\),%r16d # 200298 <.*> - +[a-f0-9]+: d5 40 03 0d f8 00 20 00 add 0x2000f8\(%rip\),%r17d # 200298 <.*> - +[a-f0-9]+: d5 40 23 15 f0 00 20 00 and 0x2000f0\(%rip\),%r18d # 200298 <.*> - +[a-f0-9]+: d5 40 3b 1d e8 00 20 00 cmp 0x2000e8\(%rip\),%r19d # 200298 <.*> - +[a-f0-9]+: d5 40 0b 25 e0 00 20 00 or 0x2000e0\(%rip\),%r20d # 200298 <.*> - +[a-f0-9]+: d5 40 1b 2d d8 00 20 00 sbb 0x2000d8\(%rip\),%r21d # 200298 <.*> - +[a-f0-9]+: d5 40 2b 35 d0 00 20 00 sub 0x2000d0\(%rip\),%r22d # 200298 <.*> - +[a-f0-9]+: d5 40 33 3d c8 00 20 00 xor 0x2000c8\(%rip\),%r23d # 200298 <.*> - +[a-f0-9]+: d5 44 85 05 c0 00 20 00 test %r24d,0x2000c0\(%rip\) # 200298 <.*> - +[a-f0-9]+: d5 48 13 05 b8 00 20 00 adc 0x2000b8\(%rip\),%r16 # 200298 <.*> - +[a-f0-9]+: d5 48 03 0d b0 00 20 00 add 0x2000b0\(%rip\),%r17 # 200298 <.*> - +[a-f0-9]+: d5 48 23 15 a8 00 20 00 and 0x2000a8\(%rip\),%r18 # 200298 <.*> - +[a-f0-9]+: d5 48 3b 1d a0 00 20 00 cmp 0x2000a0\(%rip\),%r19 # 200298 <.*> - +[a-f0-9]+: d5 48 0b 25 98 00 20 00 or 0x200098\(%rip\),%r20 # 200298 <.*> - +[a-f0-9]+: d5 48 1b 2d 90 00 20 00 sbb 0x200090\(%rip\),%r21 # 200298 <.*> - +[a-f0-9]+: d5 48 2b 35 88 00 20 00 sub 0x200088\(%rip\),%r22 # 200298 <.*> - +[a-f0-9]+: d5 48 33 3d 80 00 20 00 xor 0x200080\(%rip\),%r23 # 200298 <.*> - +[a-f0-9]+: d5 4c 85 05 78 00 20 00 test %r24,0x200078\(%rip\) # 200298 <.*> +0+1000 <_start>: + +[a-f0-9]+: d5 40 13 05 68 10 20 00 adc 0x201068\(%rip\),%r16d # 202070 <.*> + +[a-f0-9]+: d5 40 03 0d 60 10 20 00 add 0x201060\(%rip\),%r17d # 202070 <.*> + +[a-f0-9]+: d5 40 23 15 58 10 20 00 and 0x201058\(%rip\),%r18d # 202070 <.*> + +[a-f0-9]+: d5 40 3b 1d 50 10 20 00 cmp 0x201050\(%rip\),%r19d # 202070 <.*> + +[a-f0-9]+: d5 40 0b 25 48 10 20 00 or 0x201048\(%rip\),%r20d # 202070 <.*> + +[a-f0-9]+: d5 40 1b 2d 40 10 20 00 sbb 0x201040\(%rip\),%r21d # 202070 <.*> + +[a-f0-9]+: d5 40 2b 35 38 10 20 00 sub 0x201038\(%rip\),%r22d # 202070 <.*> + +[a-f0-9]+: d5 40 33 3d 30 10 20 00 xor 0x201030\(%rip\),%r23d # 202070 <.*> + +[a-f0-9]+: d5 44 85 05 28 10 20 00 test %r24d,0x201028\(%rip\) # 202070 <.*> + +[a-f0-9]+: d5 48 13 05 20 10 20 00 adc 0x201020\(%rip\),%r16 # 202070 <.*> + +[a-f0-9]+: d5 48 03 0d 18 10 20 00 add 0x201018\(%rip\),%r17 # 202070 <.*> + +[a-f0-9]+: d5 48 23 15 10 10 20 00 and 0x201010\(%rip\),%r18 # 202070 <.*> + +[a-f0-9]+: d5 48 3b 1d 08 10 20 00 cmp 0x201008\(%rip\),%r19 # 202070 <.*> + +[a-f0-9]+: d5 48 0b 25 00 10 20 00 or 0x201000\(%rip\),%r20 # 202070 <.*> + +[a-f0-9]+: d5 48 1b 2d f8 0f 20 00 sbb 0x200ff8\(%rip\),%r21 # 202070 <.*> + +[a-f0-9]+: d5 48 2b 35 f0 0f 20 00 sub 0x200ff0\(%rip\),%r22 # 202070 <.*> + +[a-f0-9]+: d5 48 33 3d e8 0f 20 00 xor 0x200fe8\(%rip\),%r23 # 202070 <.*> + +[a-f0-9]+: d5 4c 85 05 e0 0f 20 00 test %r24,0x200fe0\(%rip\) # 202070 <.*> + +[a-f0-9]+: d5 40 13 05 e0 0f 20 00 adc 0x200fe0\(%rip\),%r16d # 202078 <.*> + +[a-f0-9]+: d5 40 03 0d d8 0f 20 00 add 0x200fd8\(%rip\),%r17d # 202078 <.*> + +[a-f0-9]+: d5 40 23 15 d0 0f 20 00 and 0x200fd0\(%rip\),%r18d # 202078 <.*> + +[a-f0-9]+: d5 40 3b 1d c8 0f 20 00 cmp 0x200fc8\(%rip\),%r19d # 202078 <.*> + +[a-f0-9]+: d5 40 0b 25 c0 0f 20 00 or 0x200fc0\(%rip\),%r20d # 202078 <.*> + +[a-f0-9]+: d5 40 1b 2d b8 0f 20 00 sbb 0x200fb8\(%rip\),%r21d # 202078 <.*> + +[a-f0-9]+: d5 40 2b 35 b0 0f 20 00 sub 0x200fb0\(%rip\),%r22d # 202078 <.*> + +[a-f0-9]+: d5 40 33 3d a8 0f 20 00 xor 0x200fa8\(%rip\),%r23d # 202078 <.*> + +[a-f0-9]+: d5 44 85 05 a0 0f 20 00 test %r24d,0x200fa0\(%rip\) # 202078 <.*> + +[a-f0-9]+: d5 48 13 05 98 0f 20 00 adc 0x200f98\(%rip\),%r16 # 202078 <.*> + +[a-f0-9]+: d5 48 03 0d 90 0f 20 00 add 0x200f90\(%rip\),%r17 # 202078 <.*> + +[a-f0-9]+: d5 48 23 15 88 0f 20 00 and 0x200f88\(%rip\),%r18 # 202078 <.*> + +[a-f0-9]+: d5 48 3b 1d 80 0f 20 00 cmp 0x200f80\(%rip\),%r19 # 202078 <.*> + +[a-f0-9]+: d5 48 0b 25 78 0f 20 00 or 0x200f78\(%rip\),%r20 # 202078 <.*> + +[a-f0-9]+: d5 48 1b 2d 70 0f 20 00 sbb 0x200f70\(%rip\),%r21 # 202078 <.*> + +[a-f0-9]+: d5 48 2b 35 68 0f 20 00 sub 0x200f68\(%rip\),%r22 # 202078 <.*> + +[a-f0-9]+: d5 48 33 3d 60 0f 20 00 xor 0x200f60\(%rip\),%r23 # 202078 <.*> + +[a-f0-9]+: d5 4c 85 05 58 0f 20 00 test %r24,0x200f58\(%rip\) # 202078 <.*> + +[a-f0-9]+: 62 e4 7c 08 13 05 46 0f 20 00 adc 0x200f46\(%rip\),%r16d # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 03 0d 3c 0f 20 00 \{nf\} add 0x200f3c\(%rip\),%r17d # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 23 15 32 0f 20 00 \{nf\} and 0x200f32\(%rip\),%r18d # 202070 <.*> + +[a-f0-9]+: 62 e4 04 0a 3b 1d 28 0f 20 00 ccmpt \{dfv=\} 0x200f28\(%rip\),%r19d # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 0b 25 1e 0f 20 00 \{nf\} or 0x200f1e\(%rip\),%r20d # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 08 1b 2d 14 0f 20 00 sbb 0x200f14\(%rip\),%r21d # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 2b 35 0a 0f 20 00 \{nf\} sub 0x200f0a\(%rip\),%r22d # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 33 3d 00 0f 20 00 \{nf\} xor 0x200f00\(%rip\),%r23d # 202070 <.*> + +[a-f0-9]+: 62 64 04 0a 85 05 f6 0e 20 00 ctestt \{dfv=\} %r24d,0x200ef6\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 08 13 05 ec 0e 20 00 adc 0x200eec\(%rip\),%r16 # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 03 0d e2 0e 20 00 \{nf\} add 0x200ee2\(%rip\),%r17 # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 23 15 d8 0e 20 00 \{nf\} and 0x200ed8\(%rip\),%r18 # 202070 <.*> + +[a-f0-9]+: 62 e4 84 0a 3b 1d ce 0e 20 00 ccmpt \{dfv=\} 0x200ece\(%rip\),%r19 # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 0b 25 c4 0e 20 00 \{nf\} or 0x200ec4\(%rip\),%r20 # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 08 1b 2d ba 0e 20 00 sbb 0x200eba\(%rip\),%r21 # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 2b 35 b0 0e 20 00 \{nf\} sub 0x200eb0\(%rip\),%r22 # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 33 3d a6 0e 20 00 \{nf\} xor 0x200ea6\(%rip\),%r23 # 202070 <.*> + +[a-f0-9]+: 62 64 84 0a 85 05 9c 0e 20 00 ctestt \{dfv=\} %r24,0x200e9c\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 08 11 05 92 0e 20 00 adc %r16d,0x200e92\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 01 0d 88 0e 20 00 \{nf\} add %r17d,0x200e88\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 21 15 7e 0e 20 00 \{nf\} and %r18d,0x200e7e\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 04 0a 39 1d 74 0e 20 00 ccmpt \{dfv=\} %r19d,0x200e74\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 09 25 6a 0e 20 00 \{nf\} or %r20d,0x200e6a\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 08 19 2d 60 0e 20 00 sbb %r21d,0x200e60\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 29 35 56 0e 20 00 \{nf\} sub %r22d,0x200e56\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 0c 31 3d 4c 0e 20 00 \{nf\} xor %r23d,0x200e4c\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 64 04 0a 85 05 42 0e 20 00 ctestt \{dfv=\} %r24d,0x200e42\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 08 11 05 38 0e 20 00 adc %r16,0x200e38\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 01 0d 2e 0e 20 00 \{nf\} add %r17,0x200e2e\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 21 15 24 0e 20 00 \{nf\} and %r18,0x200e24\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 84 0a 39 1d 1a 0e 20 00 ccmpt \{dfv=\} %r19,0x200e1a\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 09 25 10 0e 20 00 \{nf\} or %r20,0x200e10\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 08 19 2d 06 0e 20 00 sbb %r21,0x200e06\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 29 35 fc 0d 20 00 \{nf\} sub %r22,0x200dfc\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 0c 31 3d f2 0d 20 00 \{nf\} xor %r23,0x200df2\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 64 84 0a 85 05 e8 0d 20 00 ctestt \{dfv=\} %r24,0x200de8\(%rip\) # 202070 <.*> + +[a-f0-9]+: 62 e4 7c 18 13 05 de 0d 20 00 adc 0x200dde\(%rip\),%r16d,%eax # 202070 <.*> + +[a-f0-9]+: 62 e4 74 18 03 0d d4 0d 20 00 add 0x200dd4\(%rip\),%r17d,%ecx # 202070 <.*> + +[a-f0-9]+: 62 e4 6c 18 23 15 ca 0d 20 00 and 0x200dca\(%rip\),%r18d,%edx # 202070 <.*> + +[a-f0-9]+: 62 e4 64 18 0b 1d c0 0d 20 00 or 0x200dc0\(%rip\),%r19d,%ebx # 202070 <.*> + +[a-f0-9]+: 62 e4 5c 18 1b 25 b6 0d 20 00 sbb 0x200db6\(%rip\),%r20d,%esp # 202070 <.*> + +[a-f0-9]+: 62 e4 54 18 2b 2d ac 0d 20 00 sub 0x200dac\(%rip\),%r21d,%ebp # 202070 <.*> + +[a-f0-9]+: 62 e4 4c 18 33 35 a2 0d 20 00 xor 0x200da2\(%rip\),%r22d,%esi # 202070 <.*> + +[a-f0-9]+: 62 e4 fc 18 13 05 98 0d 20 00 adc 0x200d98\(%rip\),%r16,%rax # 202070 <.*> + +[a-f0-9]+: 62 e4 f4 18 03 0d 8e 0d 20 00 add 0x200d8e\(%rip\),%r17,%rcx # 202070 <.*> + +[a-f0-9]+: 62 e4 ec 18 23 15 84 0d 20 00 and 0x200d84\(%rip\),%r18,%rdx # 202070 <.*> + +[a-f0-9]+: 62 e4 e4 18 0b 1d 7a 0d 20 00 or 0x200d7a\(%rip\),%r19,%rbx # 202070 <.*> + +[a-f0-9]+: 62 e4 dc 18 1b 25 70 0d 20 00 sbb 0x200d70\(%rip\),%r20,%rsp # 202070 <.*> + +[a-f0-9]+: 62 e4 d4 18 2b 2d 66 0d 20 00 sub 0x200d66\(%rip\),%r21,%rbp # 202070 <.*> + +[a-f0-9]+: 62 e4 cc 18 33 35 5c 0d 20 00 xor 0x200d5c\(%rip\),%r22,%rsi # 202070 <.*> + +[a-f0-9]+: 62 f4 7c 10 11 05 52 0d 20 00 adc %eax,0x200d52\(%rip\),%r16d # 202070 <.*> + +[a-f0-9]+: 62 f4 74 10 01 0d 48 0d 20 00 add %ecx,0x200d48\(%rip\),%r17d # 202070 <.*> + +[a-f0-9]+: 62 f4 6c 10 21 15 3e 0d 20 00 and %edx,0x200d3e\(%rip\),%r18d # 202070 <.*> + +[a-f0-9]+: 62 f4 64 10 09 1d 34 0d 20 00 or %ebx,0x200d34\(%rip\),%r19d # 202070 <.*> + +[a-f0-9]+: 62 f4 5c 10 19 25 2a 0d 20 00 sbb %esp,0x200d2a\(%rip\),%r20d # 202070 <.*> + +[a-f0-9]+: 62 f4 54 10 29 2d 20 0d 20 00 sub %ebp,0x200d20\(%rip\),%r21d # 202070 <.*> + +[a-f0-9]+: 62 f4 4c 10 31 35 16 0d 20 00 xor %esi,0x200d16\(%rip\),%r22d # 202070 <.*> + +[a-f0-9]+: 62 f4 fc 10 11 05 0c 0d 20 00 adc %rax,0x200d0c\(%rip\),%r16 # 202070 <.*> + +[a-f0-9]+: 62 f4 f4 10 01 0d 02 0d 20 00 add %rcx,0x200d02\(%rip\),%r17 # 202070 <.*> + +[a-f0-9]+: 62 f4 ec 10 21 15 f8 0c 20 00 and %rdx,0x200cf8\(%rip\),%r18 # 202070 <.*> + +[a-f0-9]+: 62 f4 e4 10 09 1d ee 0c 20 00 or %rbx,0x200cee\(%rip\),%r19 # 202070 <.*> + +[a-f0-9]+: 62 f4 dc 10 19 25 e4 0c 20 00 sbb %rsp,0x200ce4\(%rip\),%r20 # 202070 <.*> + +[a-f0-9]+: 62 f4 d4 10 29 2d da 0c 20 00 sub %rbp,0x200cda\(%rip\),%r21 # 202070 <.*> + +[a-f0-9]+: 62 f4 cc 10 31 35 d0 0c 20 00 xor %rsi,0x200cd0\(%rip\),%r22 # 202070 <.*> #pass --- /dev/null +++ b/ld/testsuite/ld-x86-64/load3.s @@ -0,0 +1,22 @@ + .section my_section,"aw",@progbits + .long 0x12345678 + .text + .type foo, @function +foo: + ret + .size foo, .-foo + .globl _start + .type _start, @function +_start: + movrs foo@GOTPCREL(%rip), %eax + movrs bar@GOTPCREL(%rip), %r11d + movrs bar@GOTPCREL(%rip), %r21d + movrs foo@GOTPCREL(%rip), %rax + movrs bar@GOTPCREL(%rip), %r11 + movrs bar@GOTPCREL(%rip), %r21 + movrs __start_my_section@GOTPCREL(%rip), %rax + movrs __stop_my_section@GOTPCREL(%rip), %r11 + .size _start, .-_start + .comm pad,4,4 + .comm bar,4,4 + .hidden bar --- /dev/null +++ b/ld/testsuite/ld-x86-64/load3a.d @@ -0,0 +1,21 @@ +#source: load3.s +#as: --64 +#ld: -melf_x86_64 +#objdump: -dw + +.*: +file format .* + + +Disassembly of section .text: + +#... +[a-f0-9]+ <_start>: +[ ]*[a-f0-9]+: 26 26 c7 c0 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%eax +[ ]*[a-f0-9]+: 26 26 41 c7 c3 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%r11d +[ ]*[a-f0-9]+: 26 26 d5 10 c7 c5 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%r21d +[ ]*[a-f0-9]+: 26 26 48 c7 c0 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%rax +[ ]*[a-f0-9]+: 26 26 49 c7 c3 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%r11 +[ ]*[a-f0-9]+: 26 26 d5 18 c7 c5 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%r21 +[ ]*[a-f0-9]+: 26 26 48 c7 c0 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%rax +[ ]*[a-f0-9]+: 26 26 49 c7 c3 ([0-9a-f]{2} ){4} * (es ){2}mov \$0x[a-f0-9]+,%r11 +#pass --- /dev/null +++ b/ld/testsuite/ld-x86-64/load3b.d @@ -0,0 +1,21 @@ +#source: load3.s +#as: --64 +#ld: -shared -melf_x86_64 +#objdump: -dw + +.*: +file format .* + + +Disassembly of section .text: + +#... +[a-f0-9]+ <_start>: +[ ]*[a-f0-9]+: 26 26 8d 05 ([0-9a-f]{2} ){4} * (es ){2}lea -0x[a-f0-9]+\(%rip\),%eax # [a-f0-9]+ +[ ]*[a-f0-9]+: 26 26 44 8d 1d ([0-9a-f]{2} ){4} * (es ){2}lea 0x[a-f0-9]+\(%rip\),%r11d # [a-f0-9]+ +[ ]*[a-f0-9]+: 26 26 d5 40 8d 2d ([0-9a-f]{2} ){4} * (es ){2}lea 0x[a-f0-9]+\(%rip\),%r21d # [a-f0-9]+ +[ ]*[a-f0-9]+: 26 26 48 8d 05 ([0-9a-f]{2} ){4} * (es ){2}lea -0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ +[ ]*[a-f0-9]+: 26 26 4c 8d 1d ([0-9a-f]{2} ){4} * (es ){2}lea 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ +[ ]*[a-f0-9]+: 26 26 d5 48 8d 2d ([0-9a-f]{2} ){4} * (es ){2}lea 0x[a-f0-9]+\(%rip\),%r21 # [a-f0-9]+ +[ ]*[a-f0-9]+: 26 26 48 8d 05 ([0-9a-f]{2} ){4} * (es ){2}lea 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <__start_my_section> +[ ]*[a-f0-9]+: 26 26 4c 8d 1d ([0-9a-f]{2} ){4} * (es ){2}lea 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <(__stop_my_section|pad)> +#pass --- a/ld/testsuite/ld-x86-64/tlsbindesc.dd +++ b/ld/testsuite/ld-x86-64/tlsbindesc.dd @@ -246,13 +246,29 @@ Disassembly of section .text: +[0-9a-f]+: d5 48 8b 25 ([0-9a-f]{2} ){3}[ ]+mov 0x[0-9a-f]+\(%rip\),%r20 +# [0-9a-f]+ # -> R_X86_64_TPOFF64 sG5 +[0-9a-f]+: 00 * + +[0-9a-f]+: 4c 0f 38 8b 15 ([0-9a-f]{2} ){2}[ ]+movrs 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ +# -> R_X86_64_TPOFF64 sG5 + +[0-9a-f]+: ([0-9a-f]{2} ){2} + +[0-9a-f]+: 62 e4 fc 08 8b 25 [0-9a-f]{2}[ ]+movrs 0x[0-9a-f]+\(%rip\),%r20 +# [0-9a-f]+ +# -> R_X86_64_TPOFF64 sG5 + +[0-9a-f]+: ([0-9a-f]{2} ){3} # IE->LE against local var +[0-9a-f]+: d5 18 c7 c5 90 ff ff[ ]+mov \$0xf+90,%r21 # sl5 +[0-9a-f]+: ff * + +[0-9a-f]+: 26 26 49 c7 c3 90 ff[ ]+(es ){2}mov \$0xf+90,%r11 +# sl5 + +[0-9a-f]+: ff ff * + +[0-9a-f]+: 26 26 d5 18 c7 c5 90[ ]+(es ){2}mov \$0xf+90,%r21 +# sl5 + +[0-9a-f]+: ff ff ff * # IE->LE against hidden var +[0-9a-f]+: d5 18 c7 c6 b0 ff ff[ ]+mov \$0xf+b0,%r22 +[0-9a-f]+: ff * + +[0-9a-f]+: 26 26 49 c7 c4 b0 ff[ ]+(es ){2}mov \$0xf+b0,%r12 + +[0-9a-f]+: ff ff * + +[0-9a-f]+: 26 26 d5 18 c7 c6 b0[ ]+(es ){2}mov \$0xf+b0,%r22 + +[0-9a-f]+: ff ff ff * # GD -> IE because variable is not defined in executable +[0-9a-f]+: d5 48 8b 05 ([0-9a-f]{2} ){3}[ ]+mov 0x[0-9a-f]+\(%rip\),%r16 +# [0-9a-f]+ # -> R_X86_64_TPOFF64 sG1 --- a/ld/testsuite/ld-x86-64/tlsbindesc.rd +++ b/ld/testsuite/ld-x86-64/tlsbindesc.rd @@ -15,12 +15,12 @@ Section Headers: +\[[ 0-9]+\] .dynsym +.* +\[[ 0-9]+\] .dynstr +.* +\[[ 0-9]+\] .rela.dyn +.* - +\[[ 0-9]+\] .text +PROGBITS +0+401000 0+1000 0+325 00 +AX +0 +0 +4096 - +\[[ 0-9]+\] .tdata +PROGBITS +0+601325 0+1325 0+60 00 WAT +0 +0 +1 - +\[[ 0-9]+\] .tbss +NOBITS +0+601385 0+1385 0+40 00 WAT +0 +0 +1 - +\[[ 0-9]+\] .dynamic +DYNAMIC +0+601388 0+1388 0+100 10 +WA +4 +0 +8 - +\[[ 0-9]+\] .got +PROGBITS +0+601488 0+1488 0+20 08 +WA +0 +0 +8 - +\[[ 0-9]+\] .got.plt +PROGBITS +0+6014a8 0+14a8 0+18 08 +WA +0 +0 +8 + +\[[ 0-9]+\] .text +PROGBITS +0+401000 0+1000 0+35e 00 +AX +0 +0 +4096 + +\[[ 0-9]+\] .tdata +PROGBITS +0+60135e 0+135e 0+60 00 WAT +0 +0 +1 + +\[[ 0-9]+\] .tbss +NOBITS +0+6013be 0+13be 0+40 00 WAT +0 +0 +1 + +\[[ 0-9]+\] .dynamic +DYNAMIC +0+6013c0 0+13c0 0+100 10 +WA +4 +0 +8 + +\[[ 0-9]+\] .got +PROGBITS +0+6014c0 0+14c0 0+20 08 +WA +0 +0 +8 + +\[[ 0-9]+\] .got.plt +PROGBITS +0+6014e0 0+14e0 0+18 08 +WA +0 +0 +8 +\[[ 0-9]+\] .symtab +.* +\[[ 0-9]+\] .strtab +.* +\[[ 0-9]+\] .shstrtab +.* @@ -28,7 +28,7 @@ Key to Flags: #... Elf file type is EXEC \(Executable file\) -Entry point 0x40122d +Entry point 0x401266 There are [0-9]+ program headers, starting at offset [0-9]+ Program Headers: @@ -36,10 +36,10 @@ Program Headers: +PHDR.* +INTERP.* .*Requesting program interpreter.* - +LOAD +0x0+ 0x0+400000 0x0+400000 0x0+1325 0x0+1325 R E 0x200000 - +LOAD +0x0+1325 0x0+601325 0x0+601325 0x0+19b 0x0+19b RW +0x200000 - +DYNAMIC +0x0+1388 0x0+601388 0x0+601388 0x0+100 0x0+100 RW +0x8 - +TLS +0x0+1325 0x0+601325 0x0+601325 0x0+60 0x0+a0 R +0x1 + +LOAD +0x0+ 0x0+400000 0x0+400000 0x0+135e 0x0+135e R E 0x200000 + +LOAD +0x0+135e 0x0+60135e 0x0+60135e 0x0+19a 0x0+19a RW +0x200000 + +DYNAMIC +0x0+13c0 0x0+6013c0 0x0+6013c0 0x0+100 0x0+100 RW +0x8 + +TLS +0x0+135e 0x0+60135e 0x0+60135e 0x0+60 0x0+a0 R +0x1 Section to Segment mapping: +Segment Sections... @@ -52,10 +52,10 @@ Program Headers: Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+601488 +0+100000012 R_X86_64_TPOFF64 +0+ sG5 \+ 0 -0+601490 +0+200000012 R_X86_64_TPOFF64 +0+ sG2 \+ 0 -0+601498 +0+300000012 R_X86_64_TPOFF64 +0+ sG6 \+ 0 -0+6014a0 +0+400000012 R_X86_64_TPOFF64 +0+ sG1 \+ 0 +0+6014c0 +0+100000012 R_X86_64_TPOFF64 +0+ sG5 \+ 0 +0+6014c8 +0+200000012 R_X86_64_TPOFF64 +0+ sG2 \+ 0 +0+6014d0 +0+300000012 R_X86_64_TPOFF64 +0+ sG6 \+ 0 +0+6014d8 +0+400000012 R_X86_64_TPOFF64 +0+ sG1 \+ 0 Symbol table '\.dynsym' contains [0-9]+ entries: +Num: +Value +Size +Type +Bind +Vis +Ndx +Name @@ -88,8 +88,8 @@ Symbol table '\.symtab' contains [0-9]+ +[0-9]+: 0+9c +0 +TLS +LOCAL +DEFAULT +8 bl8 .* FILE +LOCAL +DEFAULT +ABS +[0-9]+: 0+a0 +0 +TLS +LOCAL +DEFAULT +7 _TLS_MODULE_BASE_ - +[0-9]+: 0+601388 +0 +OBJECT +LOCAL +DEFAULT +9 _DYNAMIC - +[0-9]+: 0+6014a8 +0 +OBJECT +LOCAL +DEFAULT +11 _GLOBAL_OFFSET_TABLE_ + +[0-9]+: 0+6013c0 +0 +OBJECT +LOCAL +DEFAULT +9 _DYNAMIC + +[0-9]+: 0+6014e0 +0 +OBJECT +LOCAL +DEFAULT +11 _GLOBAL_OFFSET_TABLE_ +[0-9]+: 0+1c +0 +TLS +GLOBAL +DEFAULT +7 sg8 +[0-9]+: 0+7c +0 +TLS +GLOBAL +DEFAULT +8 bg8 +[0-9]+: 0+74 +0 +TLS +GLOBAL +DEFAULT +8 bg6 @@ -104,7 +104,7 @@ Symbol table '\.symtab' contains [0-9]+ +[0-9]+: 0+58 +0 +TLS +GLOBAL +HIDDEN +7 sh7 +[0-9]+: 0+5c +0 +TLS +GLOBAL +HIDDEN +7 sh8 +[0-9]+: 0+ +0 +TLS +GLOBAL +DEFAULT +7 sg1 - +[0-9]+: 0+40122d +0 +FUNC +GLOBAL +DEFAULT +6 _start + +[0-9]+: 0+401266 +0 +FUNC +GLOBAL +DEFAULT +6 _start +[0-9]+: 0+4c +0 +TLS +GLOBAL +HIDDEN +7 sh4 +[0-9]+: 0+78 +0 +TLS +GLOBAL +DEFAULT +8 bg7 +[0-9]+: 0+50 +0 +TLS +GLOBAL +HIDDEN +7 sh5 --- a/ld/testsuite/ld-x86-64/tlsbindesc.s +++ b/ld/testsuite/ld-x86-64/tlsbindesc.s @@ -163,12 +163,18 @@ fn2: /* IE against global var */ movq sG5@gottpoff(%rip), %r20 + movrs sG5@gottpoff(%rip), %r10 + movrs sG5@gottpoff(%rip), %r20 /* IE->LE against local var */ movq sl5@gottpoff(%rip), %r21 + movrs sl5@gottpoff(%rip), %r11 + movrs sl5@gottpoff(%rip), %r21 /* IE->LE against hidden var */ movq sh5@gottpoff(%rip), %r22 + movrs sh5@gottpoff(%rip), %r12 + movrs sh5@gottpoff(%rip), %r22 /* GD -> IE because variable is not defined in executable */ leaq sG1@tlsdesc(%rip), %r16 --- a/ld/testsuite/ld-x86-64/tlsie5.d +++ b/ld/testsuite/ld-x86-64/tlsie5.d @@ -1,4 +1,4 @@ #name: TLS IE->LE transition check (APX) #as: --64 -mtls-check=no #ld: -melf_x86_64 -#error: .*: relocation R_X86_64_CODE_6_GOTTPOFF against `foo' must be used in ADD only +#error: .*: relocation R_X86_64_CODE_6_GOTTPOFF against `foo' must be used in ADD or MOVRS only --- a/ld/testsuite/ld-x86-64/x86-64.exp +++ b/ld/testsuite/ld-x86-64/x86-64.exp @@ -651,6 +651,8 @@ run_dump_test "apx-load1b" run_dump_test "apx-load1c" run_dump_test "apx-load1d" run_dump_test "load2" +run_dump_test "load3a" +run_dump_test "load3b" run_dump_test "call1a" run_dump_test "call1b" run_dump_test "call1c"