[2/3,2.42,Backport] aarch64: Remove SVE2p1

Message ID 4eb9c2a0-acec-d2f0-146f-a197a1af89c4@e124511.cambridge.arm.com
State Superseded
Headers
Series aarch64: Remove B16B16, SVE2p1 and SME2p1 |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Andrew Carlotti Feb. 29, 2024, 5:36 p.m. UTC
  Support for this extension is incomplete and has a number of syntax and
opcode bugs in the 2.42 branch.  This patch removes the flags and
documentation, to avoid any further suggestion that this extension is
fully and correctly supported.
  

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 86aa7d7334d3b58ee4e0abeba796b7214f356b30..75e6c9465aaa3871bb5acd367d6f8feab9b6d860 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -4,8 +4,6 @@  Changes in 2.42:
 
 * Added support for AMD znver5 processor (available from GNU Binutils 2.42 release).
 
-* Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
-
 * Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
   (B16B16).
 
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 62c428cb80ba7114440c9c65f6042259e3f99df9..696283b456ceb7bd57ba4f021dd4b371e3ff15d4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10426,7 +10426,6 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"d128",		AARCH64_FEATURE (D128),
 			AARCH64_FEATURE (LSE128)},
   {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
-  {"sve2p1",		AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
   {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 748e7263428115c56db76b39371f9777248850a7..818f98ef8589228012fe583b56082f3027780434 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -277,8 +277,6 @@  automatically cause those extensions to be disabled.
  @tab Enable the SVE2 SHA3 Extension.
 @item @code{sve2-sm4} @tab @code{sve2}, @code{sm4}
  @tab Enable the SVE2 SM4 Extension.
-@item @code{sve2p1} @tab @code{sve2}
- @tab Enable SVE2.1.
 @item @code{the} @tab
  @tab Enable the Translation Hardening Extension.
 @item @code{tme} @tab
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d b/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
deleted file mode 100644
index a2ca49ef487563a55ae8c26ca4318e68da850e64..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d
+++ /dev/null
@@ -1,4 +0,0 @@ 
-#name: Illegal test of SVE2.1 min max instructions.
-#as: -march=armv9.4-a
-#source: sve2p1-1.s
-#error_output: sve2p1-1-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
deleted file mode 100644
index 50a4bacc73c20324ae50b8688dd8cf5123a238ae..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ /dev/null
@@ -1,96 +0,0 @@ 
-.*: Assembler messages:
-.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `addqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `addqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `addqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `addqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `addqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `andqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `andqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `andqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `andqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `andqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `andqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `smaxqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `smaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `smaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `smaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `smaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `smaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `umaxqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `umaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `umaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `umaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `umaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `umaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `sminqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `sminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `sminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `sminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `sminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `sminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `uminqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `uminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `uminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `uminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `uminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `uminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `dupq z10.b,z20.b\[0\]'
-.*: Error: selected processor does not support `dupq z10.b,z20.b\[15\]'
-.*: Error: selected processor does not support `dupq z10.h,z20.h\[0\]'
-.*: Error: selected processor does not support `dupq z10.h,z20.h\[7\]'
-.*: Error: selected processor does not support `dupq z10.s,z20.s\[0\]'
-.*: Error: selected processor does not support `dupq z10.s,z20.s\[3\]'
-.*: Error: selected processor does not support `dupq z10.d,z20.d\[0\]'
-.*: Error: selected processor does not support `dupq z10.d,z20.d\[1\]'
-.*: Error: selected processor does not support `eorqv v0.16b,p0,z16.b'
-.*: Error: selected processor does not support `eorqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `eorqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `eorqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `eorqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `eorqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `extq z0.b,z0.b,z10.b\[15\]'
-.*: Error: selected processor does not support `extq z1.b,z1.b,z15.b\[7\]'
-.*: Error: selected processor does not support `extq z2.b,z2.b,z5.b\[3\]'
-.*: Error: selected processor does not support `extq z4.b,z4.b,z12.b\[1\]'
-.*: Error: selected processor does not support `extq z8.b,z8.b,z7.b\[4\]'
-.*: Error: selected processor does not support `extq z16.b,z16.b,z1.b\[8\]'
-.*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `faddqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `faddqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fmaxnmqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fmaxnmqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fmaxnmqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fmaxnmqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fmaxnmqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fmaxqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fmaxqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fmaxqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fmaxqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fmaxqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fminnmqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fminnmqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fminnmqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fminnmqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fminnmqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `fminqv v1.8h,p1,z8.h'
-.*: Error: selected processor does not support `fminqv v2.4s,p2,z4.s'
-.*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d'
-.*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d'
-.*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]'
-.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
deleted file mode 100644
index daece899b38bba4daa2ca9e58dba2d551f6cf988..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ /dev/null
@@ -1,105 +0,0 @@ 
-#name: Test of SVE2.1 min max instructions.
-#as: -march=armv9.4-a+sve2p1
-#objdump: -dr
-
-[^:]+:     file format .*
-
-
-[^:]+:
-
-[^:]+:
-.*:	04052200 	addqv	v0.16b, p0, z16.b
-.*:	04452501 	addqv	v1.8h, p1, z8.h
-.*:	04852882 	addqv	v2.4s, p2, z4.s
-.*:	04c52c44 	addqv	v4.2d, p3, z2.d
-.*:	04c53028 	addqv	v8.2d, p4, z1.d
-.*:	04853c10 	addqv	v16.4s, p7, z0.s
-.*:	041e2200 	andqv	v0.16b, p0, z16.b
-.*:	045e2501 	andqv	v1.8h, p1, z8.h
-.*:	049e2882 	andqv	v2.4s, p2, z4.s
-.*:	04de2c44 	andqv	v4.2d, p3, z2.d
-.*:	04de3028 	andqv	v8.2d, p4, z1.d
-.*:	049e3c10 	andqv	v16.4s, p7, z0.s
-.*:	040c2200 	smaxqv	v0.16b, p0, z16.b
-.*:	044c2501 	smaxqv	v1.8h, p1, z8.h
-.*:	048c2882 	smaxqv	v2.4s, p2, z4.s
-.*:	04cc2c44 	smaxqv	v4.2d, p3, z2.d
-.*:	04cc3028 	smaxqv	v8.2d, p4, z1.d
-.*:	048c3c10 	smaxqv	v16.4s, p7, z0.s
-.*:	040d2200 	umaxqv	v0.16b, p0, z16.b
-.*:	044d2501 	umaxqv	v1.8h, p1, z8.h
-.*:	048d2882 	umaxqv	v2.4s, p2, z4.s
-.*:	04cd2c44 	umaxqv	v4.2d, p3, z2.d
-.*:	04cd3028 	umaxqv	v8.2d, p4, z1.d
-.*:	048d3c10 	umaxqv	v16.4s, p7, z0.s
-.*:	040e2200 	sminqv	v0.16b, p0, z16.b
-.*:	044e2501 	sminqv	v1.8h, p1, z8.h
-.*:	048e2882 	sminqv	v2.4s, p2, z4.s
-.*:	04ce2c44 	sminqv	v4.2d, p3, z2.d
-.*:	04ce3028 	sminqv	v8.2d, p4, z1.d
-.*:	048e3c10 	sminqv	v16.4s, p7, z0.s
-.*:	040f2200 	uminqv	v0.16b, p0, z16.b
-.*:	044f2501 	uminqv	v1.8h, p1, z8.h
-.*:	048f2882 	uminqv	v2.4s, p2, z4.s
-.*:	04cf2c44 	uminqv	v4.2d, p3, z2.d
-.*:	04cf3028 	uminqv	v8.2d, p4, z1.d
-.*:	048f3c10 	uminqv	v16.4s, p7, z0.s
-.*:	0530268a 	dupq	z10.b, z20.b\[0\]
-.*:	053f268a 	dupq	z10.b, z20.b\[15\]
-.*:	0521268a 	dupq	z10.h, z20.h\[0\]
-.*:	052f268a 	dupq	z10.h, z20.h\[7\]
-.*:	0522268a 	dupq	z10.s, z20.s\[0\]
-.*:	052e268a 	dupq	z10.s, z20.s\[3\]
-.*:	0524268a 	dupq	z10.d, z20.d\[0\]
-.*:	052c268a 	dupq	z10.d, z20.d\[1\]
-.*:	041d2200 	eorqv	v0.16b, p0, z16.b
-.*:	045d2501 	eorqv	v1.8h, p1, z8.h
-.*:	049d2882 	eorqv	v2.4s, p2, z4.s
-.*:	04dd2c44 	eorqv	v4.2d, p3, z2.d
-.*:	04dd3028 	eorqv	v8.2d, p4, z1.d
-.*:	049d3c10 	eorqv	v16.4s, p7, z0.s
-.*:	056a27c0 	extq	z0.b, z0.b, z10.b\[15\]
-.*:	056f25c1 	extq	z1.b, z1.b, z15.b\[7\]
-.*:	056524c2 	extq	z2.b, z2.b, z5.b\[3\]
-.*:	056c2444 	extq	z4.b, z4.b, z12.b\[1\]
-.*:	05672508 	extq	z8.b, z8.b, z7.b\[4\]
-.*:	05612610 	extq	z16.b, z16.b, z1.b\[8\]
-.*:	6450a501 	faddqv	v1.8h, p1, z8.h
-.*:	6490a882 	faddqv	v2.4s, p2, z4.s
-.*:	64d0ac44 	faddqv	v4.2d, p3, z2.d
-.*:	64d0b028 	faddqv	v8.2d, p4, z1.d
-.*:	6490bc10 	faddqv	v16.4s, p7, z0.s
-.*:	6454a501 	fmaxnmqv	v1.8h, p1, z8.h
-.*:	6494a882 	fmaxnmqv	v2.4s, p2, z4.s
-.*:	64d4ac44 	fmaxnmqv	v4.2d, p3, z2.d
-.*:	64d4b028 	fmaxnmqv	v8.2d, p4, z1.d
-.*:	6494bc10 	fmaxnmqv	v16.4s, p7, z0.s
-.*:	6456a501 	fmaxqv	v1.8h, p1, z8.h
-.*:	6496a882 	fmaxqv	v2.4s, p2, z4.s
-.*:	64d6ac44 	fmaxqv	v4.2d, p3, z2.d
-.*:	64d6b028 	fmaxqv	v8.2d, p4, z1.d
-.*:	6496bc10 	fmaxqv	v16.4s, p7, z0.s
-.*:	6455a501 	fminnmqv	v1.8h, p1, z8.h
-.*:	6495a882 	fminnmqv	v2.4s, p2, z4.s
-.*:	64d5ac44 	fminnmqv	v4.2d, p3, z2.d
-.*:	64d5b028 	fminnmqv	v8.2d, p4, z1.d
-.*:	6495bc10 	fminnmqv	v16.4s, p7, z0.s
-.*:	6457a501 	fminqv	v1.8h, p1, z8.h
-.*:	6497a882 	fminqv	v2.4s, p2, z4.s
-.*:	64d7ac44 	fminqv	v4.2d, p3, z2.d
-.*:	64d7b028 	fminqv	v8.2d, p4, z1.d
-.*:	6497bc10 	fminqv	v16.4s, p7, z0.s
-.*:	c400b200 	ld1q	z0.q, p4/z, \[z16.d, x0\]
-.*:	a49ef000 	ld2q	{z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\]
-.*:	a51ef000 	ld3q	{z0.q, z1.q, z2.q}, p4/z, \[x0, #-4, mul vl\]
-.*:	a59ef000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-4, mul vl\]
-.*:	a4a2f000 	ld2h	{z0.h-z1.h}, p4/z, \[x0, #4, mul vl\]
-.*:	a5249000 	ld3q	{z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\]
-.*:	a5a69000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\]
-.*:	e4203200 	st1q	z0.q, p4, \[z16.d, x0\]
-.*:	e44e1000 	st2q	{z0.q, z1.q}, p4, \[x0, #-4, mul vl\]
-.*:	e48e1000 	st3q	{z0.q, z1.q, z2.q}, p4, \[x0, #-4, mul vl\]
-.*:	e4ce1000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-4, mul vl\]
-.*:	e4621000 	st2q	{z0.q, z1.q}, p4, \[x0, x2, lsl #4\]
-.*:	e4a41000 	st3q	{z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\]
-.*:	e4e61000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
deleted file mode 100644
index 2a1c7c107d757ae922cec5566adbace1f03e0dce..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ /dev/null
@@ -1,107 +0,0 @@ 
-addqv v0.16b, p0, z16.b
-addqv v1.8h, p1, z8.h
-addqv v2.4s, p2, z4.s
-addqv v4.2d, p3, z2.d
-addqv v8.2d, p4, z1.d
-addqv v16.4s, p7, z0.s
-
-andqv v0.16b, p0, z16.b
-andqv v1.8h, p1, z8.h
-andqv v2.4s, p2, z4.s
-andqv v4.2d, p3, z2.d
-andqv v8.2d, p4, z1.d
-andqv v16.4s, p7, z0.s
-
-smaxqv v0.16b, p0, z16.b
-smaxqv v1.8h, p1, z8.h
-smaxqv v2.4s, p2, z4.s
-smaxqv v4.2d, p3, z2.d
-smaxqv v8.2d, p4, z1.d
-smaxqv v16.4s, p7, z0.s
-
-umaxqv v0.16b, p0, z16.b
-umaxqv v1.8h, p1, z8.h
-umaxqv v2.4s, p2, z4.s
-umaxqv v4.2d, p3, z2.d
-umaxqv v8.2d, p4, z1.d
-umaxqv v16.4s, p7, z0.s
-
-sminqv v0.16b, p0, z16.b
-sminqv v1.8h, p1, z8.h
-sminqv v2.4s, p2, z4.s
-sminqv v4.2d, p3, z2.d
-sminqv v8.2d, p4, z1.d
-sminqv v16.4s, p7, z0.s
-
-uminqv v0.16b, p0, z16.b
-uminqv v1.8h, p1, z8.h
-uminqv v2.4s, p2, z4.s
-uminqv v4.2d, p3, z2.d
-uminqv v8.2d, p4, z1.d
-uminqv v16.4s, p7, z0.s
-dupq z10.b, z20.b[0]
-dupq z10.b, z20.b[15]
-dupq z10.h, z20.h[0]
-dupq z10.h, z20.h[7]
-dupq z10.s, z20.s[0]
-dupq z10.s, z20.s[3]
-dupq z10.d, z20.d[0]
-dupq z10.d, z20.d[1]
-
-eorqv v0.16b, p0, z16.b
-eorqv v1.8h, p1, z8.h
-eorqv v2.4s, p2, z4.s
-eorqv v4.2d, p3, z2.d
-eorqv v8.2d, p4, z1.d
-eorqv v16.4s, p7, z0.s
-
-extq z0.b, z0.b, z10.b[15]
-extq z1.b, z1.b, z15.b[7]
-extq z2.b, z2.b, z5.b[3]
-extq z4.b, z4.b, z12.b[1]
-extq z8.b, z8.b, z7.b[4]
-extq z16.b, z16.b, z1.b[8]
-faddqv v1.8h, p1, z8.h
-faddqv v2.4s, p2, z4.s
-faddqv v4.2d, p3, z2.d
-faddqv v8.2d, p4, z1.d
-faddqv v16.4s, p7, z0.s
-
-fmaxnmqv v1.8h, p1, z8.h
-fmaxnmqv v2.4s, p2, z4.s
-fmaxnmqv v4.2d, p3, z2.d
-fmaxnmqv v8.2d, p4, z1.d
-fmaxnmqv v16.4s, p7, z0.s
-
-fmaxqv v1.8h, p1, z8.h
-fmaxqv v2.4s, p2, z4.s
-fmaxqv v4.2d, p3, z2.d
-fmaxqv v8.2d, p4, z1.d
-fmaxqv v16.4s, p7, z0.s
-
-fminnmqv v1.8h, p1, z8.h
-fminnmqv v2.4s, p2, z4.s
-fminnmqv v4.2d, p3, z2.d
-fminnmqv v8.2d, p4, z1.d
-fminnmqv v16.4s, p7, z0.s
-
-fminqv v1.8h, p1, z8.h
-fminqv v2.4s, p2, z4.s
-fminqv v4.2d, p3, z2.d
-fminqv v8.2d, p4, z1.d
-fminqv v16.4s, p7, z0.s
-ld1q Z0.Q, p4/Z, [Z16.D, x0]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0,  #-4, MUL VL]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0,  #-4, MUL VL]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0,  #-4, MUL VL]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl  #4]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl  #4]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl  #4]
-
-st1q Z0.Q, p4, [Z16.D, x0]
-st2q {Z0.Q, Z1.Q}, p4, [x0,  #-4, MUL VL]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0,  #-4, MUL VL]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0,  #-4, MUL VL]
-st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl  #4]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl  #4]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl  #4]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bb3151d027ccd56f83298083a2e6c744eb1f4573..2e7485f25adfc7001630b50d173bd7ff77b587a6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,8 +222,6 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_SEBEP,
   /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
   AARCH64_FEATURE_B16B16,
-  /* SVE2.1 instructions.  */
-  AARCH64_FEATURE_SVE2p1,
   /* RCPC3 instructions.  */
   AARCH64_FEATURE_RCPC3,
   AARCH64_NUM_FEATURES
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ae4363970b0b8bc6eaa342b4199d96cacac6fd8a..1c9fa61c8f89b32ed1deb1db33cb1b55206dd3a3 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2643,8 +2643,6 @@  static const aarch64_feature_set aarch64_feature_d128_the =
   AARCH64_FEATURES (2, D128, THE);
 static const aarch64_feature_set aarch64_feature_b16b16 =
   AARCH64_FEATURE (B16B16);
-static const aarch64_feature_set aarch64_feature_sve2p1 =
-  AARCH64_FEATURE (SVE2p1);
 static const aarch64_feature_set aarch64_feature_rcpc3 =
   AARCH64_FEATURE (RCPC3);
 
@@ -2711,7 +2709,6 @@  static const aarch64_feature_set aarch64_feature_rcpc3 =
 #define THE	  &aarch64_feature_the
 #define D128_THE  &aarch64_feature_d128_the
 #define B16B16  &aarch64_feature_b16b16
-#define SVE2p1  &aarch64_feature_sve2p1
 #define RCPC3	  &aarch64_feature_rcpc3
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2788,12 +2785,6 @@  static const aarch64_feature_set aarch64_feature_rcpc3 =
 #define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
-    FLAGS | F_STRICT, 0, TIED, NULL }
-#define SVE2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
-    FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
 #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
@@ -6342,39 +6333,6 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
   B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
 
-/* SVE2p1 Instructions.  */
-  SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-
-  SVE2p1_INSNC("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-
-  SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
-  SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0),
-  SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-
-  SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };