@@ -10751,18 +10751,18 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES},
{"sme-lutv2", AARCH64_FEATURE (SME_LUTv2), AARCH64_FEATURE (SME2)},
{"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)},
- {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)},
- {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)},
+ {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8)},
+ {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8)},
{"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA),
AARCH64_FEATURES (2, FP8, SME2)},
{"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4),
- AARCH64_FEATURE (SSVE_FP8FMA)},
+ AARCH64_FEATURES (2, FP8, SME2)},
{"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2),
- AARCH64_FEATURE (SSVE_FP8DOT4)},
+ AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f8f32", AARCH64_FEATURE (SME_F8F32),
AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
- AARCH64_FEATURE (SME_F8F32)},
+ AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f16f16", AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME2)},
{"sme-b16b16", AARCH64_FEATURE (SME_B16B16),
AARCH64_FEATURES (2, SVE_B16B16, SME2)},
@@ -195,9 +195,9 @@ automatically cause those extensions to be disabled.
@tab Enable floating-point extensions.
@item @code{fp8} @tab
@tab Enable the Floating Point 8 (FP8) extension.
-@item @code{fp8dot2} @tab @code{fp8dot4}
+@item @code{fp8dot2} @tab @code{fp8}
@tab Enable the FP8 2-way dot product instructions.
-@item @code{fp8dot4} @tab @code{fp8fma}
+@item @code{fp8dot4} @tab @code{fp8}
@tab Enable the FP8 4-way dot product instructions.
@item @code{fp8fma} @tab @code{fp8}
@tab Enable the FP8 FMA instructions.
@@ -271,7 +271,7 @@ automatically cause those extensions to be disabled.
@tab Enable the Scalable Matrix Extension.
@item @code{sme-b16b16} @tab @code{sme2}, @code{sve-b16b16}
@tab Enable SME ZA-targeting non-widening BFloat16 instructions.
-@item @code{sme-f8f16} @tab @code{sme-f8f32}
+@item @code{sme-f8f16} @tab @code{sme2}, @code{fp8}
@tab Enable the SME F8F16 Extension.
@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
@tab Enable the SME F8F32 Extension.
@@ -287,12 +287,12 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.1.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
-@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4}
- @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}.
-@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma}
- @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}.
+@item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
+ @tab Enable the Streaming SVE FP8 2-way dot product instructions.
+@item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
+ @tab Enable the Streaming SVE FP8 4-way dot product instructions.
@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8}
- @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}.
+ @tab Enable the Streaming SVE FP8 FMA instructions.
@item @code{sve} @tab @code{fcma}
@tab Enable the Scalable Vector Extension.
@item @code{sve-b16b16} @tab
@@ -1,2 +1,2 @@
-#as: -march=armv8-a+fp8dot2
+#as: -march=armv8-a+fp8dot2+fp8dot4+fp8fma
#error_output: fp8-mul-illegal.l
@@ -1,2 +1,2 @@
-#as: -march=armv8-a+sve2+fp8dot2
+#as: -march=armv8-a+sve2+fp8dot2+fp8dot4+fp8fma
#error_output: fp8-sve-mul-illegal.l
@@ -2858,7 +2858,7 @@ static const aarch64_feature_set aarch64_feature_fp8dot2_sve =
static const aarch64_feature_set aarch64_feature_sme_f8f32 =
AARCH64_FEATURES (2, SME_F8F32, SME2);
static const aarch64_feature_set aarch64_feature_sme_f8f16 =
- AARCH64_FEATURES (2, SME_F8F32, SME2);
+ AARCH64_FEATURES (2, SME_F8F16, SME2);
static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2);
static const aarch64_feature_set aarch64_feature_sme_f16f16 =