[v1,2/2] aarch64: Fix sve2p1 ld[1-4]q/st[1-4]q instructions encoding and syntax.

Message ID 41ed1e4d-851e-4413-842a-3bc058a86665@arm.com
State New
Headers
Series [v1,1/2,Biuntils] aarch64: Fix sve2p1 dupq/extq instructions encoding and syntax. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Testing failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Srinath Parvathaneni Feb. 23, 2024, 1:59 p.m. UTC
  Hi,

This patch fixes encoding and syntax for sve2p1 instructions as 
mentioned below,
for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html

1) ld1q and st1q first register operand to accept enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions to accept wrapping
    sequence of vector registers.
3) Fixes the encoding for bits 13 and 14 for ld2q's scalar plus scalar 
encoding.
4) ld3q/st3q and ld4q/st4q scalar plus immediate forms accepts multiple 
of 3 and 4
respectively.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master? Also ok to be backported to binutils-2.42 branch?

Regards,
Srinath.
  

Comments

Jan Beulich Feb. 26, 2024, 10:10 a.m. UTC | #1
On 23.02.2024 14:59, Srinath Parvathaneni wrote:
> This patch fixes encoding and syntax for sve2p1 instructions as 
> mentioned below,
> for the issues reported here.
> https://sourceware.org/pipermail/binutils/2024-February/132408.html
> 
> 1) ld1q and st1q first register operand to accept enclosed figure braces.
> 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions to accept wrapping
>     sequence of vector registers.

The testsuite addition does not reflect this, which I think would be
relevant.

As to the spec of the 3- and 4-forms of these insns itself: Wouldn't,
for non-wrapping sequences of registers, the shorter {z<n>.q-z<m>.q}
be nice to permit at least as alternative form? And then default to
that in disassembly?

Jan

> 3) Fixes the encoding for bits 13 and 14 for ld2q's scalar plus scalar 
> encoding.
> 4) ld3q/st3q and ld4q/st4q scalar plus immediate forms accepts multiple 
> of 3 and 4
> respectively.
> 
> Regression testing for aarch64-none-elf target and found no regressions.
> 
> Ok for binutils-master? Also ok to be backported to binutils-2.42 branch?
> 
> Regards,
> Srinath.
  

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 01e2bbf70c8b9812df8f1c6f8677bce2181701fa..64dc697fa7a4c9fbc0bdee186f6c7631af5dc304 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6748,9 +6748,10 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_ZtxN:
 	case AARCH64_OPND_SME_Zdnx2:
 	case AARCH64_OPND_SME_Zdnx4:
-	case AARCH64_OPND_SME_Zt2:
-	case AARCH64_OPND_SME_Zt3:
-	case AARCH64_OPND_SME_Zt4:
+	case AARCH64_OPND_SVE_Zt1:
+	case AARCH64_OPND_SVE_Zt2:
+	case AARCH64_OPND_SVE_Zt3:
+	case AARCH64_OPND_SVE_Zt4:
 	case AARCH64_OPND_SME_Zmx2:
 	case AARCH64_OPND_SME_Zmx4:
 	case AARCH64_OPND_SME_Znx2:
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index c4bfc1f8b5adbd929d32303a3eed9b04172cfc0a..b0736e0fcd67bec6b2fd560652462ceb56556a9e 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -35,10 +35,10 @@ 
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index b98b76faaed5d79fe068291ff3892f3c89b42617..10c2a51204b5a027f3d5b7dc19aecfccd2ab993f 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -35,10 +35,10 @@ 
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 83917440e8187252c01892ce32100213cfef998c..1b6a9683b6583ab1981d64a99cc3d8276bc3dd9c 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -66,17 +66,3 @@ 
 .*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d'
 .*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d'
 .*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]'
-.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,#-4,MUL VL\]'
-.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]'
-.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]'
-.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index ea8c5448a4181f7fc73bee8e46119cc796f2784c..81baca64b866aef060cc48c7825a9d2984a17833 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -75,17 +75,3 @@ 
 .*:	64d7ac44 	fminqv	v4.2d, p3, z2.d
 .*:	64d7b028 	fminqv	v8.2d, p4, z1.d
 .*:	6497bc10 	fminqv	v16.4s, p7, z0.s
-.*:	c400b200 	ld1q	z0.q, p4/z, \[z16.d, x0\]
-.*:	a49ef000 	ld2q	{z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\]
-.*:	a51ef000 	ld3q	{z0.q, z1.q, z2.q}, p4/z, \[x0, #-4, mul vl\]
-.*:	a59ef000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-4, mul vl\]
-.*:	a4a2f000 	ld2h	{z0.h-z1.h}, p4/z, \[x0, #4, mul vl\]
-.*:	a5249000 	ld3q	{z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\]
-.*:	a5a69000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\]
-.*:	e4203200 	st1q	z0.q, p4, \[z16.d, x0\]
-.*:	e44e1000 	st2q	{z0.q, z1.q}, p4, \[x0, #-4, mul vl\]
-.*:	e48e1000 	st3q	{z0.q, z1.q, z2.q}, p4, \[x0, #-4, mul vl\]
-.*:	e4ce1000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-4, mul vl\]
-.*:	e4621000 	st2q	{z0.q, z1.q}, p4, \[x0, x2, lsl #4\]
-.*:	e4a41000 	st3q	{z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\]
-.*:	e4e61000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 12a086b078f259b4aeb840f95b1e40e37e379fe6..1e7c2ceceba8198df018eeade0defeca7517ce17 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -75,18 +75,3 @@  fminqv v2.4s, p2, z4.s
 fminqv v4.2d, p3, z2.d
 fminqv v8.2d, p4, z1.d
 fminqv v16.4s, p7, z0.s
-ld1q Z0.Q, p4/Z, [Z16.D, x0]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0,  #-4, MUL VL]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0,  #-4, MUL VL]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0,  #-4, MUL VL]
-ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl  #4]
-ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl  #4]
-ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl  #4]
-
-st1q Z0.Q, p4, [Z16.D, x0]
-st2q {Z0.Q, Z1.Q}, p4, [x0,  #-4, MUL VL]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0,  #-4, MUL VL]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0,  #-4, MUL VL]
-st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl  #4]
-st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl  #4]
-st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl  #4]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
new file mode 100644
index 0000000000000000000000000000000000000000..2363a12484de04b760500d5c5176c173acd78cbc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
@@ -0,0 +1,3 @@ 
+#name: Test of illegal SVE2.1 ld[1-4]q/st[1-4]q instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-4-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
new file mode 100644
index 0000000000000000000000000000000000000000..075ffd82fb78dd4cd023a590f9a31ebd90b82bcb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
@@ -0,0 +1,88 @@ 
+.*: Assembler messages:
+.*: Error: missing braces at operand 1 -- `ld1q Z0.Q,P0/Z,\[Z0.D,x0\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld1q {Z0.Q},P8/Z,\[Z0.D,x0\]'
+.*: Error: invalid base register at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z31.Q,x0\]'
+
+.*: Error: invalid addressing mode at operand 3 -- `ld1q {Z0.Q},P0/Z,\[Z0.D,x31\]'
+.*: Error: operand mismatch -- `ld1q {Z31.D},P7/Z,\[Z31.D,x30\]'
+.*: Info:    did you mean this\?
+.*: Info:    	ld1q {z31.q}, p7/z, \[z31.d, x30\]
+.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,\[x0,#-2,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,#-2,MUL VL\]'
+.*: Error: immediate value must be a multiple of 2 at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,\[x30,#-3,MUL VL\]'
+.*: Error: invalid register list at operand 1 -- `ld3q {Z0.Q,Z1.Q,Z3.Q},p0/Z,\[x0,#-3,MUL VL\]'
+.*: Error: operand mismatch -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p8/M,\[x0,#-3,MUL VL\]'
+.*: Info:    did you mean this\?
+.*: Info:    	ld3q {z29.q, z30.q, z31.q}, p8/z, \[x0, #-3, mul vl\]
+.*: Error: immediate value must be a multiple of 3 at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/Z,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x31,#-3,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.Q,Z30.Q,Z31.D},p7/Z,\[x30,#-3,MUL VL\]'
+.*: Error: expected a list of 4 registers at operand 1 -- `ld4q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,#-4,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p9/Z,\[x0,#-4,MUL VL\]'
+.*: Error: immediate value must be a multiple of 4 at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,#-3,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x31,#-4,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7/Z,\[x30,#-4,MUL VL\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,x0,LSL#3\]'
+.*: Error: invalid register list at operand 1 -- `ld2q {Z31.Q,Z31.Q},p0/Z,\[x0,x0,LSL#4\]'
+.*: Error: p0-p7 expected at operand 2 -- `ld2q {Z0.Q,Z1.Q},p8/Z,\[x0,x0,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x31,x0,LSL#4\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld2q {Z0.Q,Z1.Q},p0/Z,\[x0,x31,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `ld2q {Z30.Q,Z31.Q},p7/Z,\[x31,x31,LSL#4\]'
+.*: Error: shift expression expected at operand 3 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p0/Z,\[x0,x0,#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld3q {Z29.Q,Z30.Q,Z31.Q},p0/Z,\[x0,x0,LSL#2\]'
+.*: Error: operand mismatch -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p7/M,\[x0,x0,LSL#4\]'
+.*: Info:    did you mean this\?
+.*: Info:    	ld3q {z0.q, z1.q, z2.q}, p7/z, \[x0, x0, lsl #4\]
+.*: Error: p0-p7 expected at operand 2 -- `ld3q {Z0.Q,Z1.Q,Z2.Q},p8/Z,\[x30,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld3q {Z4.Q,Z1.Q,Z2.Q},p0/Z,\[x31,x30,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld3q {Z29.D,Z30.Q,Z31.Q},p7/Z,\[x31,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x0,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z30.Q,Z29.Q,Z30.Q,Z31.Q},p8/Z,\[x0,x0,LSL#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7/Z,\[x0,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0/Z,\[x31,x0,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `ld4q {Z0.Q,Z1.Q,Z2.D,Z3.Q},p0/Z,\[x1,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `ld4q {Z2.Q,Z29.Q,Z30.Q,Z31.Q},p7/Z,\[x30,x30,LSL#4\]'
+.*: Error: missing braces at operand 1 -- `st1q Z0.Q,P0,\[Z0.D,x0\]'
+.*: Error: p0-p7 expected at operand 2 -- `st1q {Z0.Q},P8,\[Z0.D,x0\]'
+.*: Error: invalid base register at operand 3 -- `st1q {Z0.Q},P0,\[Z31.Q,x0\]'
+.*: Error: invalid addressing mode at operand 3 -- `st1q {Z0.Q},P0,\[Z0.D,x31\]'
+.*: Error: operand mismatch -- `st1q {Z31.D},P7,\[Z31.D,x30\]'
+.*: Info:    did you mean this\?
+.*: Info:    	st1q {z31.q}, p7, \[z31.d, x30\]
+.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[x0,#-2,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,#-2,MUL VL\]'
+.*: Error: immediate value must be a multiple of 2 at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[x30,#-3,MUL VL\]'
+.*: Error: invalid register list at operand 1 -- `st3q {Z0.Q,Z1.Q,Z3.Q},p0,\[x0,#-3,MUL VL\]'
+.*: Error: operand mismatch -- `st3q {Z29.Q,Z30.Q,Z31.Q},p8/M,\[x0,#-3,MUL VL\]'
+.*: Info:    did you mean this\?
+.*: Info:    	st3q {z29.q, z30.q, z31.q}, p8, \[x0, #-3, mul vl\]
+.*: Error: immediate value must be a multiple of 3 at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p7,\[x0,#-2,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x31,#-3,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.Q,Z30.Q,Z31.D},p7,\[x30,#-3,MUL VL\]'
+.*: Error: expected a list of 4 registers at operand 1 -- `st4q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,#-4,MUL VL\]'
+.*: Error: p0-p7 expected at operand 2 -- `st4q {Z28.Q,Z29.Q,Z30.Q,Z31.Q},p9,\[x0,#-4,MUL VL\]'
+.*: Error: immediate value must be a multiple of 4 at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,#-3,MUL VL\]'
+.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x31,#-4,MUL VL\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z28.Q,Z29.Q,Z30.D,Z31.Q},p7,\[x30,#-4,MUL VL\]'
+.*: Error: invalid addressing mode at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,x0,LSL#3\]'
+.*: Error: invalid register list at operand 1 -- `st2q {Z31.Q,Z31.Q},p0,\[x0,x0,LSL#4\]'
+.*: Error: p0-p7 expected at operand 2 -- `st2q {Z0.Q,Z1.Q},p8,\[x0,x0,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x31,x0,LSL#4\]'
+.*: Error: only 'MUL VL' is permitted at operand 3 -- `st2q {Z0.Q,Z1.Q},p0,\[x0,x31,LSL#4\]'
+.*: Error: invalid base register at operand 3 -- `st2q {Z30.Q,Z31.Q},p7,\[x31,x31,LSL#4\]'
+.*: Error: shift expression expected at operand 3 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p0,\[x0,x0,#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `st3q {Z29.Q,Z30.Q,Z31.Q},p0,\[x0,x0,LSL#2\]'
+.*: Error: operand mismatch -- `st3q {Z0.Q,Z1.Q,Z2.Q},p7/M,\[x0,x0,LSL#4\]'
+.*: Info:    did you mean this\?
+.*: Info:    	st3q {z0.q, z1.q, z2.q}, p7, \[x0, x0, lsl #4\]
+.*: Error: p0-p7 expected at operand 2 -- `st3q {Z0.Q,Z1.Q,Z2.Q},p8,\[x30,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st3q {Z4.Q,Z1.Q,Z2.Q},p0,\[x31,x30,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st3q {Z29.D,Z30.Q,Z31.Q},p7,\[x31,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z1.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x0,x0,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z30.Q,Z29.Q,Z30.Q,Z31.Q},p8,\[x0,x0,LSL#4\]'
+.*: Error: invalid addressing mode at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p7,\[x0,x0,LSL#2\]'
+.*: Error: invalid base register at operand 3 -- `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p0,\[x31,x0,LSL#4\]'
+.*: Error: type mismatch in vector register list at operand 1 -- `st4q {Z0.Q,Z1.Q,Z2.D,Z3.Q},p0,\[x1,x30,LSL#4\]'
+.*: Error: invalid register list at operand 1 -- `st4q {Z2.Q,Z29.Q,Z30.Q,Z31.Q},p7,\[x30,x30,LSL#4\]'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
new file mode 100644
index 0000000000000000000000000000000000000000..4c814c9924e73033a5cb3768e03099a4302a7fa2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
@@ -0,0 +1,89 @@ 
+ld1q Z0.Q , P0/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P8/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z31.Q, x0]
+ld1q { Z0.Q }, P0/Z, [Z0.D, x31]
+ld1q { Z31.D }, P7/Z, [Z31.D, x30]
+
+ld2q {Z0.Q, Z2.Q}, p0/Z, [x0,  #-2, MUL VL]
+ld2q {Z31.Q, Z31.Q}, p0/Z, [x0,  #-2, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p8/Z, [x0,  #-2, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x31,  #-2, MUL VL]
+ld2q {Z30.Q, Z31.Q}, p7/Z, [x30,  #-3, MUL VL]
+
+ld3q {Z0.Q, Z1.Q, Z3.Q}, p0/Z, [x0,  #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p8/M, [x0,  #-3, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0,  #-2, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x31,  #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.D}, p7/Z, [x30,  #-3, MUL VL]
+
+ld4q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0,  #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9/Z, [x0,  #-4, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0,  #-3, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31,  #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7/Z, [x30,  #-4, MUL VL]
+
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  x0, LSL  #3]
+ld2q {Z31.Q, Z31.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld2q {Z0.Q, Z1.Q}, p8/Z, [x0,  x0, LSL  #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x31,  x0, LSL  #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  x31, LSL  #4]
+ld2q {Z30.Q, Z31.Q}, p7/Z, [x31,  x31, LSL  #4]
+
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0,  x0,  #4]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0,  x0, LSL  #2]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/M, [x0,  x0, LSL  #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p8/Z, [x30,  x0, LSL  #4]
+ld3q {Z4.Q, Z1.Q, Z2.Q}, p0/Z, [x31,  x30, LSL  #4]
+ld3q {Z29.D, Z30.Q, Z31.Q}, p7/Z, [x31,  x30, LSL  #4]
+
+ld4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8/Z, [x0,  x0, LSL  #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0,  x0, LSL  #2]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x31,  x0, LSL  #4]
+ld4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0/Z, [x1,  x30, LSL  #4]
+ld4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30,  x30, LSL  #4]
+
+st1q Z0.Q , P0, [Z0.D, x0]
+st1q { Z0.Q }, P8, [Z0.D, x0]
+st1q { Z0.Q }, P0, [Z31.Q, x0]
+st1q { Z0.Q }, P0, [Z0.D, x31]
+st1q { Z31.D }, P7, [Z31.D, x30]
+
+st2q {Z0.Q, Z2.Q}, p0, [x0,  #-2, MUL VL]
+st2q {Z31.Q, Z31.Q}, p0, [x0,  #-2, MUL VL]
+st2q {Z0.Q, Z1.Q}, p8, [x0,  #-2, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x31,  #-2, MUL VL]
+st2q {Z30.Q, Z31.Q}, p7, [x30,  #-3, MUL VL]
+
+st3q {Z0.Q, Z1.Q, Z3.Q}, p0, [x0,  #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p8/M, [x0,  #-3, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0,  #-2, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x31,  #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.D}, p7, [x30,  #-3, MUL VL]
+
+st4q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0,  #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p9, [x0,  #-4, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0,  #-3, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31,  #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.D, Z31.Q}, p7, [x30,  #-4, MUL VL]
+
+st2q {Z0.Q, Z1.Q}, p0, [x0,  x0, LSL  #3]
+st2q {Z31.Q, Z31.Q}, p0, [x0,  x0, LSL  #4]
+st2q {Z0.Q, Z1.Q}, p8, [x0,  x0, LSL  #4]
+st2q {Z0.Q, Z1.Q}, p0, [x31,  x0, LSL  #4]
+st2q {Z0.Q, Z1.Q}, p0, [x0,  x31, LSL  #4]
+st2q {Z30.Q, Z31.Q}, p7, [x31,  x31, LSL  #4]
+
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0,  x0,  #4]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0,  x0, LSL  #2]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7/M, [x0,  x0, LSL  #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p8, [x30,  x0, LSL  #4]
+st3q {Z4.Q, Z1.Q, Z2.Q}, p0, [x31,  x30, LSL  #4]
+st3q {Z29.D, Z30.Q, Z31.Q}, p7, [x31,  x30, LSL  #4]
+
+st4q {Z1.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0,  x0, LSL  #4]
+st4q {Z30.Q, Z29.Q, Z30.Q,Z31.Q}, p8, [x0,  x0, LSL  #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0,  x0, LSL  #2]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x31,  x0, LSL  #4]
+st4q {Z0.Q, Z1.Q, Z2.D, Z3.Q}, p0, [x1,  x30, LSL  #4]
+st4q {Z2.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30,  x30, LSL  #4]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.d b/gas/testsuite/gas/aarch64/sve2p1-4.d
new file mode 100644
index 0000000000000000000000000000000000000000..0ba151cf866bed9c131706eddca4f3f442ec27da
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4.d
@@ -0,0 +1,90 @@ 
+#name: Test of SVE2.1 ld[1-4]q/st[1-4]q instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	c400a000 	ld1q	{z0.q}, p0/z, \[z0.d, x0\]
+.*:	c400a01f 	ld1q	{z31.q}, p0/z, \[z0.d, x0\]
+.*:	c400bc00 	ld1q	{z0.q}, p7/z, \[z0.d, x0\]
+.*:	c400a3e0 	ld1q	{z0.q}, p0/z, \[z31.d, x0\]
+.*:	c41ea000 	ld1q	{z0.q}, p0/z, \[z0.d, x30\]
+.*:	c41ebfff 	ld1q	{z31.q}, p7/z, \[z31.d, x30\]
+.*:	c404acef 	ld1q	{z15.q}, p3/z, \[z7.d, x4\]
+.*:	a49fe000 	ld2q	{z0.q, z1.q}, p0/z, \[x0, #-2, mul vl\]
+.*:	a49fe01e 	ld2q	{z30.q, z31.q}, p0/z, \[x0, #-2, mul vl\]
+.*:	a49ffc00 	ld2q	{z0.q, z1.q}, p7/z, \[x0, #-2, mul vl\]
+.*:	a49fe3c0 	ld2q	{z0.q, z1.q}, p0/z, \[x30, #-2, mul vl\]
+.*:	a49fffde 	ld2q	{z30.q, z31.q}, p7/z, \[x30, #-2, mul vl\]
+.*:	a51fe000 	ld3q	{z0.q, z1.q, z2.q}, p0/z, \[x0, #-3, mul vl\]
+.*:	a51fe01d 	ld3q	{z29.q, z30.q, z31.q}, p0/z, \[x0, #-3, mul vl\]
+.*:	a51ffc00 	ld3q	{z0.q, z1.q, z2.q}, p7/z, \[x0, #-3, mul vl\]
+.*:	a51fe3c0 	ld3q	{z0.q, z1.q, z2.q}, p0/z, \[x30, #-3, mul vl\]
+.*:	a51fffdd 	ld3q	{z29.q, z30.q, z31.q}, p7/z, \[x30, #-3, mul vl\]
+.*:	a59fe000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p0/z, \[x0, #-4, mul vl\]
+.*:	a59fe01c 	ld4q	{z28.q, z29.q, z30.q, z31.q}, p0/z, \[x0, #-4, mul vl\]
+.*:	a59ffc00 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p7/z, \[x0, #-4, mul vl\]
+.*:	a59fe3c0 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p0/z, \[x30, #-4, mul vl\]
+.*:	a59fffdc 	ld4q	{z28.q, z29.q, z30.q, z31.q}, p7/z, \[x30, #-4, mul vl\]
+.*:	a4a08000 	ld2q	{z0.q, z1.q}, p0/z, \[x0, x0, lsl #4\]
+.*:	a4a0801e 	ld2q	{z30.q, z31.q}, p0/z, \[x0, x0, lsl #4\]
+.*:	a4a09c00 	ld2q	{z0.q, z1.q}, p7/z, \[x0, x0, lsl #4\]
+.*:	a4a083c0 	ld2q	{z0.q, z1.q}, p0/z, \[x30, x0, lsl #4\]
+.*:	a4be8000 	ld2q	{z0.q, z1.q}, p0/z, \[x0, x30, lsl #4\]
+.*:	a4be9fde 	ld2q	{z30.q, z31.q}, p7/z, \[x30, x30, lsl #4\]
+.*:	a5208000 	ld3q	{z0.q, z1.q, z2.q}, p0/z, \[x0, x0, lsl #4\]
+.*:	a520801d 	ld3q	{z29.q, z30.q, z31.q}, p0/z, \[x0, x0, lsl #4\]
+.*:	a5209c00 	ld3q	{z0.q, z1.q, z2.q}, p7/z, \[x0, x0, lsl #4\]
+.*:	a52083c0 	ld3q	{z0.q, z1.q, z2.q}, p0/z, \[x30, x0, lsl #4\]
+.*:	a53e8000 	ld3q	{z0.q, z1.q, z2.q}, p0/z, \[x0, x30, lsl #4\]
+.*:	a53e9fdd 	ld3q	{z29.q, z30.q, z31.q}, p7/z, \[x30, x30, lsl #4\]
+.*:	a5a08000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p0/z, \[x0, x0, lsl #4\]
+.*:	a5a0801c 	ld4q	{z28.q, z29.q, z30.q, z31.q}, p0/z, \[x0, x0, lsl #4\]
+.*:	a5a09c00 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p7/z, \[x0, x0, lsl #4\]
+.*:	a5a083c0 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p0/z, \[x30, x0, lsl #4\]
+.*:	a5be8000 	ld4q	{z0.q, z1.q, z2.q, z3.q}, p0/z, \[x0, x30, lsl #4\]
+.*:	a5be9fdc 	ld4q	{z28.q, z29.q, z30.q, z31.q}, p7/z, \[x30, x30, lsl #4\]
+.*:	e4202000 	st1q	{z0.q}, p0, \[z0.d, x0\]
+.*:	e420201f 	st1q	{z31.q}, p0, \[z0.d, x0\]
+.*:	e4203c00 	st1q	{z0.q}, p7, \[z0.d, x0\]
+.*:	e42023e0 	st1q	{z0.q}, p0, \[z31.d, x0\]
+.*:	e43e2000 	st1q	{z0.q}, p0, \[z0.d, x30\]
+.*:	e43e3fff 	st1q	{z31.q}, p7, \[z31.d, x30\]
+.*:	e4242cef 	st1q	{z15.q}, p3, \[z7.d, x4\]
+.*:	e44f0000 	st2q	{z0.q, z1.q}, p0, \[x0, #-2, mul vl\]
+.*:	e44f001e 	st2q	{z30.q, z31.q}, p0, \[x0, #-2, mul vl\]
+.*:	e44f1c00 	st2q	{z0.q, z1.q}, p7, \[x0, #-2, mul vl\]
+.*:	e44f03c0 	st2q	{z0.q, z1.q}, p0, \[x30, #-2, mul vl\]
+.*:	e44f1fde 	st2q	{z30.q, z31.q}, p7, \[x30, #-2, mul vl\]
+.*:	e48f0000 	st3q	{z0.q, z1.q, z2.q}, p0, \[x0, #-3, mul vl\]
+.*:	e48f001d 	st3q	{z29.q, z30.q, z31.q}, p0, \[x0, #-3, mul vl\]
+.*:	e48f1c00 	st3q	{z0.q, z1.q, z2.q}, p7, \[x0, #-3, mul vl\]
+.*:	e48f03c0 	st3q	{z0.q, z1.q, z2.q}, p0, \[x30, #-3, mul vl\]
+.*:	e48f1fdd 	st3q	{z29.q, z30.q, z31.q}, p7, \[x30, #-3, mul vl\]
+.*:	e4cf0000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p0, \[x0, #-4, mul vl\]
+.*:	e4cf001c 	st4q	{z28.q, z29.q, z30.q, z31.q}, p0, \[x0, #-4, mul vl\]
+.*:	e4cf1c00 	st4q	{z0.q, z1.q, z2.q, z3.q}, p7, \[x0, #-4, mul vl\]
+.*:	e4cf03c0 	st4q	{z0.q, z1.q, z2.q, z3.q}, p0, \[x30, #-4, mul vl\]
+.*:	e4cf1fdc 	st4q	{z28.q, z29.q, z30.q, z31.q}, p7, \[x30, #-4, mul vl\]
+.*:	e4600000 	st2q	{z0.q, z1.q}, p0, \[x0, x0, lsl #4\]
+.*:	e460001e 	st2q	{z30.q, z31.q}, p0, \[x0, x0, lsl #4\]
+.*:	e4601c00 	st2q	{z0.q, z1.q}, p7, \[x0, x0, lsl #4\]
+.*:	e46003c0 	st2q	{z0.q, z1.q}, p0, \[x30, x0, lsl #4\]
+.*:	e47e0000 	st2q	{z0.q, z1.q}, p0, \[x0, x30, lsl #4\]
+.*:	e47e1fde 	st2q	{z30.q, z31.q}, p7, \[x30, x30, lsl #4\]
+.*:	e4a00000 	st3q	{z0.q, z1.q, z2.q}, p0, \[x0, x0, lsl #4\]
+.*:	e4a0001d 	st3q	{z29.q, z30.q, z31.q}, p0, \[x0, x0, lsl #4\]
+.*:	e4a01c00 	st3q	{z0.q, z1.q, z2.q}, p7, \[x0, x0, lsl #4\]
+.*:	e4a003c0 	st3q	{z0.q, z1.q, z2.q}, p0, \[x30, x0, lsl #4\]
+.*:	e4be0000 	st3q	{z0.q, z1.q, z2.q}, p0, \[x0, x30, lsl #4\]
+.*:	e4be1fdd 	st3q	{z29.q, z30.q, z31.q}, p7, \[x30, x30, lsl #4\]
+.*:	e4e00000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p0, \[x0, x0, lsl #4\]
+.*:	e4e0001c 	st4q	{z28.q, z29.q, z30.q, z31.q}, p0, \[x0, x0, lsl #4\]
+.*:	e4e01c00 	st4q	{z0.q, z1.q, z2.q, z3.q}, p7, \[x0, x0, lsl #4\]
+.*:	e4e003c0 	st4q	{z0.q, z1.q, z2.q, z3.q}, p0, \[x30, x0, lsl #4\]
+.*:	e4fe0000 	st4q	{z0.q, z1.q, z2.q, z3.q}, p0, \[x0, x30, lsl #4\]
+.*:	e4fe1fdc 	st4q	{z28.q, z29.q, z30.q, z31.q}, p7, \[x30, x30, lsl #4\]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-4.s b/gas/testsuite/gas/aarch64/sve2p1-4.s
new file mode 100644
index 0000000000000000000000000000000000000000..2a64a5ea630e88f061cc6dc2ac506c55e1d38998
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-4.s
@@ -0,0 +1,93 @@ 
+ld1q { Z0.Q }, P0/Z, [Z0.D, x0]
+ld1q { Z31.Q }, P0/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P7/Z, [Z0.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z31.D, x0]
+ld1q { Z0.Q }, P0/Z, [Z0.D, x30]
+ld1q { Z31.Q }, P7/Z, [Z31.D, x30]
+ld1q { Z15.Q }, P3/Z, [Z7.D, x4]
+
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  #-2, MUL VL]
+ld2q {Z30.Q, Z31.Q}, p0/Z, [x0,  #-2, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p7/Z, [x0,  #-2, MUL VL]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x30,  #-2, MUL VL]
+ld2q {Z30.Q, Z31.Q}, p7/Z, [x30,  #-2, MUL VL]
+
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0,  #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0,  #-3, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0,  #-3, MUL VL]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30,  #-3, MUL VL]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30,  #-3, MUL VL]
+
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0,  #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p0/Z, [x0,  #-4, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0,  #-4, MUL VL]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30,  #-4, MUL VL]
+ld4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30,  #-4, MUL VL]
+
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld2q {Z30.Q, Z31.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld2q {Z0.Q, Z1.Q}, p7/Z, [x0,  x0, LSL  #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x30,  x0, LSL  #4]
+ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  x30, LSL  #4]
+ld2q {Z30.Q, Z31.Q}, p7/Z, [x30,  x30, LSL  #4]
+
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p7/Z, [x0,  x0, LSL  #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x30,  x0, LSL  #4]
+ld3q {Z0.Q, Z1.Q, Z2.Q}, p0/Z, [x0,  x30, LSL  #4]
+ld3q {Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30,  x30, LSL  #4]
+
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p0/Z, [x0,  x0, LSL  #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7/Z, [x0,  x0, LSL  #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x30,  x0, LSL  #4]
+ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0/Z, [x0,  x30, LSL  #4]
+ld4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7/Z, [x30,  x30, LSL  #4]
+
+st1q { Z0.Q }, P0, [Z0.D, x0]
+st1q { Z31.Q }, P0, [Z0.D, x0]
+st1q { Z0.Q }, P7, [Z0.D, x0]
+st1q { Z0.Q }, P0, [Z31.D, x0]
+st1q { Z0.Q }, P0, [Z0.D, x30]
+st1q { Z31.Q }, P7, [Z31.D, x30]
+st1q { Z15.Q }, P3, [Z7.D, x4]
+
+st2q {Z0.Q, Z1.Q}, p0, [x0,  #-2, MUL VL]
+st2q {Z30.Q, Z31.Q}, p0, [x0,  #-2, MUL VL]
+st2q {Z0.Q, Z1.Q}, p7, [x0,  #-2, MUL VL]
+st2q {Z0.Q, Z1.Q}, p0, [x30,  #-2, MUL VL]
+st2q {Z30.Q, Z31.Q}, p7, [x30,  #-2, MUL VL]
+
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0,  #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0,  #-3, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0,  #-3, MUL VL]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30,  #-3, MUL VL]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p7, [x30,  #-3, MUL VL]
+
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0,  #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p0, [x0,  #-4, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0,  #-4, MUL VL]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30,  #-4, MUL VL]
+st4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30,  #-4, MUL VL]
+
+st2q {Z0.Q, Z1.Q}, p0, [x0,  x0, LSL  #4]
+st2q {Z30.Q, Z31.Q}, p0, [x0,  x0, LSL  #4]
+st2q {Z0.Q, Z1.Q}, p7, [x0,  x0, LSL  #4]
+st2q {Z0.Q, Z1.Q}, p0, [x30,  x0, LSL  #4]
+st2q {Z0.Q, Z1.Q}, p0, [x0,  x30, LSL  #4]
+st2q {Z30.Q, Z31.Q}, p7, [x30,  x30, LSL  #4]
+
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0,  x0, LSL  #4]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p0, [x0,  x0, LSL  #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p7, [x0,  x0, LSL  #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x30,  x0, LSL  #4]
+st3q {Z0.Q, Z1.Q, Z2.Q}, p0, [x0,  x30, LSL  #4]
+st3q {Z29.Q, Z30.Q, Z31.Q}, p7, [x30,  x30, LSL  #4]
+
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0,  x0, LSL  #4]
+st4q {Z28.Q, Z29.Q, Z30.Q,Z31.Q}, p0, [x0,  x0, LSL  #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p7, [x0,  x0, LSL  #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x30,  x0, LSL  #4]
+st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p0, [x0,  x30, LSL  #4]
+st4q {Z28.Q, Z29.Q, Z30.Q, Z31.Q}, p7, [x30,  x30, LSL  #4]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e70b9e6d348b81b6331e077f3bdf966663917e16..0b277c433dbe3bdc73c60556d07af00e1260d448 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -798,9 +798,10 @@  enum aarch64_opnd
   AARCH64_OPND_MOPS_WB_Rn,	/* Rn!, in bits [5, 9].  */
   AARCH64_OPND_CSSC_SIMM8,	/* CSSC signed 8-bit immediate.  */
   AARCH64_OPND_CSSC_UIMM8,	/* CSSC unsigned 8-bit immediate.  */
-  AARCH64_OPND_SME_Zt2,		/* Qobule SVE vector register list.  */
-  AARCH64_OPND_SME_Zt3,		/* Trible SVE vector register list.  */
-  AARCH64_OPND_SME_Zt4,		/* Quad SVE vector register list.  */
+  AARCH64_OPND_SVE_Zt1,		/* Single SVE vector register list.  */
+  AARCH64_OPND_SVE_Zt2,		/* Double SVE vector register list.  */
+  AARCH64_OPND_SVE_Zt3,		/* Triple SVE vector register list.  */
+  AARCH64_OPND_SVE_Zt4,		/* Quadruple SVE vector register list.  */
   AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND,   /* [<Xn|SP>]{, #<imm>}.  */
   AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [<Xn|SP>] or [<Xn|SP>, #<imm>]!.  */
   AARCH64_OPND_RCPC3_ADDR_POSTIND,	 /* [<Xn|SP>], #<imm>.  */
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index c6dde1c4d1b16f63665e12d0f9217481d8cbfe3b..85db92a5773ae6a7413726fb137eb7e0b80c4040 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -96,6 +96,7 @@  AARCH64_DECL_OPD_INSERTER (ins_sve_index);
 AARCH64_DECL_OPD_INSERTER (ins_sve_index_imm);
 AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
 AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
+AARCH64_DECL_OPD_INSERTER (ins_sve_triple_index);
 AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
 AARCH64_DECL_OPD_INSERTER (ins_sve_strided_reglist);
 AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 00344604e5e8b88b17daafc60fbd395fb50c7006..b76becd1178b608777a5aa82a7eb119d70956ff9 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1894,9 +1894,6 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SME_Zmx4:
 	case AARCH64_OPND_SME_Znx2:
 	case AARCH64_OPND_SME_Znx4:
-	case AARCH64_OPND_SME_Zt2:
-	case AARCH64_OPND_SME_Zt3:
-	case AARCH64_OPND_SME_Zt4:
 	  num = get_operand_specific_data (&aarch64_operands[type]);
 	  if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
 	    return 0;
@@ -1908,6 +1905,16 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	    }
 	  break;
 
+	case AARCH64_OPND_SVE_Zt1:
+	case AARCH64_OPND_SVE_Zt2:
+	case AARCH64_OPND_SVE_Zt3:
+	case AARCH64_OPND_SVE_Zt4:
+	  num = get_operand_specific_data (&aarch64_operands[type]);
+	  if (!check_reglist (opnd, mismatch_detail, idx, num,
+			      opnd->reglist.stride))
+	    return 0;
+	  break;
+
 	case AARCH64_OPND_SME_Ztx2_STRIDED:
 	case AARCH64_OPND_SME_Ztx4_STRIDED:
 	  /* 2-register lists have a stride of 8 and 4-register lists
@@ -3697,9 +3704,10 @@  print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
      more than two registers in the list, and the register numbers
      are monotonically increasing in increments of one.  */
   if (stride == 1 && num_regs > 1
-      && ((opnd->type != AARCH64_OPND_SME_Zt2)
-	  && (opnd->type != AARCH64_OPND_SME_Zt3)
-	  && (opnd->type != AARCH64_OPND_SME_Zt4)))
+      && ((opnd->type != AARCH64_OPND_SVE_Zt1)
+	  && (opnd->type != AARCH64_OPND_SVE_Zt2)
+	  && (opnd->type != AARCH64_OPND_SVE_Zt3)
+	  && (opnd->type != AARCH64_OPND_SVE_Zt4)))
     snprintf (buf, size, "{%s-%s}%s",
 	      style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
 	      style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
@@ -4144,9 +4152,10 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SME_Znx4:
     case AARCH64_OPND_SME_Ztx2_STRIDED:
     case AARCH64_OPND_SME_Ztx4_STRIDED:
-    case AARCH64_OPND_SME_Zt2:
-    case AARCH64_OPND_SME_Zt3:
-    case AARCH64_OPND_SME_Zt4:
+    case AARCH64_OPND_SVE_Zt1:
+    case AARCH64_OPND_SVE_Zt2:
+    case AARCH64_OPND_SVE_Zt3:
+    case AARCH64_OPND_SVE_Zt4:
       print_register_list (buf, size, opnd, "z", styler);
       break;
 
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 21794022721a8e40d12dde1e383e3a40f42624e5..acf29e0ef94d88dac615ac5a92d3b286de940ba1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1781,11 +1781,11 @@ 
 {                                                       \
   QLF3(S_S,P_Z,S_S),                                    \
 }
-#define OP_SVE_SZS_QD                                   \
+#define OP_SVE_QZD					\
 {                                                       \
   QLF3(S_Q,P_Z,S_D),                                    \
 }
-#define OP_SVE_SUS_QD                                   \
+#define OP_SVE_QUD	                                \
 {                                                       \
   QLF3(S_Q,NIL,S_D),                                    \
 }
@@ -6376,21 +6376,22 @@  const struct aarch64_opcode aarch64_opcode_table[] =
 
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
   SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
-  SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
 
-  SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
-  SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt1, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+
+  SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt1, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QUD, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SVE_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SVE_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SVE_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+  SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
 
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };
@@ -7030,13 +7031,16 @@  const struct aarch64_opcode aarch64_opcode_table[] =
       "an 8-bit signed immediate")					\
     Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8),		\
       "an 8-bit unsigned immediate")					\
-    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt2",	\
+    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SVE_Zt1",	\
+      1 << OPD_F_OD_LSB, F(FLD_SVE_Zt),					\
+      "a list of 1 SVE vector registers")				\
+    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SVE_Zt2",	\
       2 << OPD_F_OD_LSB, F(FLD_SVE_Zt),					\
       "a list of 2 SVE vector registers")				\
-    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt3",	\
+    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SVE_Zt3",	\
       3 << OPD_F_OD_LSB, F(FLD_SVE_Zt),					\
       "a list of 3 SVE vector registers")				\
-    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4",	\
+    X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SVE_Zt4",	\
       4 << OPD_F_OD_LSB, F(FLD_SVE_Zt),					\
       "a list of 4 SVE vector registers")				\
     X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset,		\