diff mbox series

[v4,01/12] bfd/RISC-V: Zv{b,k}* imply Zve32x

Message ID 2fa75e19-4d95-403b-876a-eeab235ddf64@suse.com
State New
Headers
Series RISC-V: assorted fixes and (hopefully) improvements |

Commit Message

Jan Beulich July 24, 2026, 10:02 a.m. UTC 
  The specification is quite explicit about this. Since only forward
references are permitted within the table, the pre-existing Zv{b,k} block
needs moving up.
---
Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While
riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it
seems unlikely to be mere chance that Zve* come ahead of all other Zv* in
riscv_supported_std_z_ext[].
---
v4: Put table entries into required order.
v3: New.

Comments

Nelson Chu July 27, 2026, 1:29 a.m. UTC | #1 
Thanks, looks good.

Nelson

On Fri, Jul 24, 2026 at 6:02 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> The specification is quite explicit about this. Since only forward
> references are permitted within the table, the pre-existing Zv{b,k} block
> needs moving up.
> ---
> Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While
> riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it
> seems unlikely to be mere chance that Zve* come ahead of all other Zv* in
> riscv_supported_std_z_ext[].
> ---
> v4: Put table entries into required order.
> v3: New.
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1244,15 +1244,35 @@ static const struct riscv_implicit_subse
>    {"zvfqwdota8f", "+zve32f", check_implicit_always},
>    {"zvfwbdota16bf", "+zve32f", check_implicit_always},
>    {"zvfwdota16bf", "+zve32f", check_implicit_always},
> +
> +  {"zvbb", "+zvkb", check_implicit_always},
> +  {"zvkng", "+zvkn,+zvkg", check_implicit_always},
> +  {"zvknc", "+zvkn,+zvbc", check_implicit_always},
> +  {"zvkn", "+zvkned,+zvknhb,+zvkb,+zvkt", check_implicit_always},
> +  {"zvksg", "+zvks,+zvkg", check_implicit_always},
> +  {"zvksc", "+zvks,+zvbc", check_implicit_always},
> +  {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
> +
> +  {"zvbc", "+zve32x", check_implicit_always},
> +  {"zvkb", "+zve32x", check_implicit_always},
> +  {"zvkg", "+zve32x", check_implicit_always},
> +  {"zvkned", "+zve32x", check_implicit_always},
> +  {"zvknha", "+zve32x", check_implicit_always},
> +  {"zvknhb", "+zve32x", check_implicit_always},
> +  {"zvksed", "+zve32x", check_implicit_always},
> +  {"zvksh", "+zve32x", check_implicit_always},
> +
>    {"zvqwbdota8i", "+zve32x", check_implicit_always},
>    {"zvqwbdota16i", "+zve64x", check_implicit_always},
>    {"zvqwdota8i", "+zve32x", check_implicit_always},
>    {"zvqwdota16i", "+zve64x", check_implicit_always},
> +
>    {"zve64d", "+d,+zve64f", check_implicit_always},
>    {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
>    {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always},
>    {"zve64x", "+zve32x,+zvl64b", check_implicit_always},
>    {"zve32x", "+zvl32b,+zicsr", check_implicit_always},
> +
>    {"zvl65536b", "+zvl32768b", check_implicit_always},
>    {"zvl32768b", "+zvl16384b", check_implicit_always},
>    {"zvl16384b", "+zvl8192b", check_implicit_always},
> @@ -1312,13 +1332,6 @@ static const struct riscv_implicit_subse
>    {"zk", "+zkn,+zkr,+zkt", check_implicit_always},
>    {"zkn", "+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh", check_implicit_always},
>    {"zks", "+zbkb,+zbkc,+zbkx,+zksed,+zksh", check_implicit_always},
> -  {"zvbb", "+zvkb", check_implicit_always},
> -  {"zvkng", "+zvkn,+zvkg", check_implicit_always},
> -  {"zvknc", "+zvkn,+zvbc", check_implicit_always},
> -  {"zvkn", "+zvkned,+zvknhb,+zvkb,+zvkt", check_implicit_always},
> -  {"zvksg", "+zvks,+zvkg", check_implicit_always},
> -  {"zvksc", "+zvks,+zvbc", check_implicit_always},
> -  {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
>
>    {"sdtrig", "+zicsr", check_implicit_always},
>
> --- a/gas/testsuite/gas/riscv/imply.d
> +++ b/gas/testsuite/gas/riscv/imply.d
> @@ -87,13 +87,13 @@ SYMBOL TABLE:
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0
>
diff mbox series

Patch

--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1244,15 +1244,35 @@  static const struct riscv_implicit_subse
   {"zvfqwdota8f", "+zve32f", check_implicit_always},
   {"zvfwbdota16bf", "+zve32f", check_implicit_always},
   {"zvfwdota16bf", "+zve32f", check_implicit_always},
+
+  {"zvbb", "+zvkb", check_implicit_always},
+  {"zvkng", "+zvkn,+zvkg", check_implicit_always},
+  {"zvknc", "+zvkn,+zvbc", check_implicit_always},
+  {"zvkn", "+zvkned,+zvknhb,+zvkb,+zvkt", check_implicit_always},
+  {"zvksg", "+zvks,+zvkg", check_implicit_always},
+  {"zvksc", "+zvks,+zvbc", check_implicit_always},
+  {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
+
+  {"zvbc", "+zve32x", check_implicit_always},
+  {"zvkb", "+zve32x", check_implicit_always},
+  {"zvkg", "+zve32x", check_implicit_always},
+  {"zvkned", "+zve32x", check_implicit_always},
+  {"zvknha", "+zve32x", check_implicit_always},
+  {"zvknhb", "+zve32x", check_implicit_always},
+  {"zvksed", "+zve32x", check_implicit_always},
+  {"zvksh", "+zve32x", check_implicit_always},
+
   {"zvqwbdota8i", "+zve32x", check_implicit_always},
   {"zvqwbdota16i", "+zve64x", check_implicit_always},
   {"zvqwdota8i", "+zve32x", check_implicit_always},
   {"zvqwdota16i", "+zve64x", check_implicit_always},
+
   {"zve64d", "+d,+zve64f", check_implicit_always},
   {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
   {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always},
   {"zve64x", "+zve32x,+zvl64b", check_implicit_always},
   {"zve32x", "+zvl32b,+zicsr", check_implicit_always},
+
   {"zvl65536b", "+zvl32768b", check_implicit_always},
   {"zvl32768b", "+zvl16384b", check_implicit_always},
   {"zvl16384b", "+zvl8192b", check_implicit_always},
@@ -1312,13 +1332,6 @@  static const struct riscv_implicit_subse
   {"zk", "+zkn,+zkr,+zkt", check_implicit_always},
   {"zkn", "+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh", check_implicit_always},
   {"zks", "+zbkb,+zbkc,+zbkx,+zksed,+zksh", check_implicit_always},
-  {"zvbb", "+zvkb", check_implicit_always},
-  {"zvkng", "+zvkn,+zvkg", check_implicit_always},
-  {"zvknc", "+zvkn,+zvbc", check_implicit_always},
-  {"zvkn", "+zvkned,+zvknhb,+zvkb,+zvkt", check_implicit_always},
-  {"zvksg", "+zvks,+zvkg", check_implicit_always},
-  {"zvksc", "+zvks,+zvbc", check_implicit_always},
-  {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
 
   {"sdtrig", "+zicsr", check_implicit_always},
 
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -87,13 +87,13 @@  SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0