diff mbox series

[14/20] s390: vlr uses instruction format VRR

Message ID 20260930081834.2948939-36-jremus@linux.ibm.com
State New
Headers
Series s390: Instruction cleanups |

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Commit Message

Jens Remus Sept. 30, 2026, 8:18 a.m. UTC 
  vlr V1,V2 uses instruction format VRR-a (VRR_VV) instead of VRX. [1, 2]
Remove erroneous instruction format VRX_VV.

[1]: IBM z/Architecture Principles of Operation, SA22-7832-10, IBM z13,
     https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr010.pdf

[2]: IBM z/Architecture Principles of Operation, SA22-7832-14, IBM z17,
     https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf

opcodes/
	* s390-opc.txt (vlr): Use instruction format VRR_VV.
	* s390-opc.c (INSTR_VRX_VV, MASK_VRX_VV): Remove.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
 opcodes/s390-opc.c   | 2 --
 opcodes/s390-opc.txt | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 86cd562807ca..92c4a37d59ce 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -495,7 +495,6 @@  unused_s390_operands_static_asserts (void)
 #define INSTR_VRI_VV0UU    6, { V_8,V_12,U8_28,U4_24,0,0 }       /* e.g. vcvdq */
 #define INSTR_VRI_VVV0UV   6, { V_8,V_12,V_16,V_32,U8_24,0 }     /* e.g. veval */
 #define INSTR_VRX_VRRD     6, { V_8,D_20,X_12,B_16,0,0 }         /* e.g. vl    */
-#define INSTR_VRX_VV       6, { V_8,V_12,0,0,0,0 }               /* e.g. vlr   */
 #define INSTR_VRX_VRRDU    6, { V_8,D_20,X_12,B_16,U4_32,0 }     /* e.g. vlrep */
 #define INSTR_VRS_RVRDU    6, { R_8,V_12,D_20,B_16,U4_32,0 }     /* e.g. vlgv  */
 #define INSTR_VRS_RVRD     6, { R_8,V_12,D_20,B_16,0,0 }         /* e.g. vlgvb */
@@ -731,7 +730,6 @@  unused_s390_operands_static_asserts (void)
 #define MASK_VRI_VV0UU    { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
 #define MASK_VRI_VVV0UV   { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff }
 #define MASK_VRX_VRRD     { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
-#define MASK_VRX_VV       { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff }
 #define MASK_VRX_VRRDU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_VRS_RVRDU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_VRS_RVRD     { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 9100b847135c..0062f87b1b62 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1200,7 +1200,7 @@  e70000000046 vgmb VRI_V0UU "vector generate mask byte" z13 zarch vx
 e70000001046 vgmh VRI_V0UU "vector generate mask halfword" z13 zarch vx
 e70000002046 vgmf VRI_V0UU "vector generate mask word" z13 zarch vx
 e70000003046 vgmg VRI_V0UU "vector generate mask double word" z13 zarch vx
-e70000000056 vlr VRX_VV "vector register load" z13 zarch vx
+e70000000056 vlr VRR_VV "vector register load" z13 zarch vx
 e70000000005 vlrep VRX_VRRDU "vector load and replicate" z13 zarch vx
 e70000000005 vlrepb VRX_VRRD "vector load and replicate byte elements" z13 zarch vx
 e70000001005 vlreph VRX_VRRD "vector load and replicate halfword elements" z13 zarch vx